core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false
  13         );
  14     port (
  15         clk          : in std_logic;
  16         rst          : in std_logic;
  17
  18         wishbone_insn_in  : in wishbone_slave_out;
  19         wishbone_insn_out : out wishbone_master_out;
  20
  21         wishbone_data_in  : in wishbone_slave_out;
  22         wishbone_data_out : out wishbone_master_out;
  23
  24         dmi_addr        : in std_ulogic_vector(3 downto 0);
  25         dmi_din         : in std_ulogic_vector(63 downto 0);
  26         dmi_dout        : out std_ulogic_vector(63 downto 0);
  27         dmi_req         : in std_ulogic;
  28         dmi_wr          : in std_ulogic;
  29         dmi_ack         : out std_ulogic;
  30
  31         terminated_out   : out std_logic
  32         );
  33 end core;
  34
  35 architecture behave of core is
  36     -- fetch signals
  37     signal fetch2_to_decode1: Fetch2ToDecode1Type;
  38
  39     -- icache signals
  40     signal fetch1_to_icache : Fetch1ToIcacheType;
  41     signal icache_to_fetch2 : IcacheToFetch2Type;
  42
  43     -- decode signals
  44     signal decode1_to_decode2: Decode1ToDecode2Type;
  45     signal decode2_to_execute1: Decode2ToExecute1Type;
  46
  47     -- register file signals
  48     signal register_file_to_decode2: RegisterFileToDecode2Type;
  49     signal decode2_to_register_file: Decode2ToRegisterFileType;
  50     signal writeback_to_register_file: WritebackToRegisterFileType;
  51
  52     -- CR file signals
  53     signal decode2_to_cr_file: Decode2ToCrFileType;
  54     signal cr_file_to_decode2: CrFileToDecode2Type;
  55     signal writeback_to_cr_file: WritebackToCrFileType;
  56
  57     -- execute signals
  58     signal execute1_to_writeback: Execute1ToWritebackType;
  59     signal execute1_to_fetch1: Execute1ToFetch1Type;
  60
  61     -- load store signals
  62     signal decode2_to_loadstore1: Decode2ToLoadstore1Type;
  63     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  64     signal dcache_to_writeback: DcacheToWritebackType;
  65
  66     -- multiply signals
  67     signal decode2_to_multiply: Decode2ToMultiplyType;
  68     signal multiply_to_writeback: MultiplyToWritebackType;
  69
  70     -- divider signals
  71     signal decode2_to_divider: Decode2ToDividerType;
  72     signal divider_to_writeback: DividerToWritebackType;
  73
  74     -- local signals
  75     signal fetch1_stall_in : std_ulogic;
  76     signal icache_stall_out : std_ulogic;
  77     signal fetch2_stall_in : std_ulogic;
  78     signal decode1_stall_in : std_ulogic;
  79     signal decode2_stall_in : std_ulogic;
  80     signal decode2_stall_out : std_ulogic;
  81     signal ex1_icache_inval: std_ulogic;
  82     signal ex1_stall_out: std_ulogic;
  83
  84     signal flush: std_ulogic;
  85
  86     signal complete: std_ulogic;
  87     signal terminate: std_ulogic;
  88     signal core_rst: std_ulogic;
  89     signal icache_rst: std_ulogic;
  90
  91     signal sim_cr_dump: std_ulogic;
  92
  93     -- Debug actions
  94     signal dbg_core_stop: std_ulogic;
  95     signal dbg_core_rst: std_ulogic;
  96     signal dbg_icache_rst: std_ulogic;
  97
  98     -- Debug status
  99     signal dbg_core_is_stopped: std_ulogic;
 100
 101     function keep_h(disable : boolean) return string is
 102     begin
 103         if disable then
 104             return "yes";
 105         else
 106             return "no";
 107         end if;
 108     end function;
 109     attribute keep_hierarchy : string;
 110     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 111     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 112     attribute keep_hierarchy of fetch2_0 : label is keep_h(DISABLE_FLATTEN);
 113     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 114     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 115     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 116     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 117     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 118     attribute keep_hierarchy of multiply_0 : label is keep_h(DISABLE_FLATTEN);
 119     attribute keep_hierarchy of divider_0 : label is keep_h(DISABLE_FLATTEN);
 120     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 121     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 122     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 123     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 124 begin
 125
 126     core_rst <= dbg_core_rst or rst;
 127
 128     fetch1_0: entity work.fetch1
 129         generic map (
 130             RESET_ADDRESS => (others => '0')
 131             )
 132         port map (
 133             clk => clk,
 134             rst => core_rst,
 135             stall_in => fetch1_stall_in,
 136             flush_in => flush,
 137             stop_in => dbg_core_stop,
 138             e_in => execute1_to_fetch1,
 139             i_out => fetch1_to_icache
 140             );
 141
 142     fetch1_stall_in <= icache_stall_out or decode2_stall_out;
 143
 144     icache_0: entity work.icache
 145         generic map(
 146             SIM => SIM,
 147             LINE_SIZE => 64,
 148             NUM_LINES => 32,
 149             NUM_WAYS => 2
 150             )
 151         port map(
 152             clk => clk,
 153             rst => icache_rst,
 154             i_in => fetch1_to_icache,
 155             i_out => icache_to_fetch2,
 156             flush_in => flush,
 157             stall_out => icache_stall_out,
 158             wishbone_out => wishbone_insn_out,
 159             wishbone_in => wishbone_insn_in
 160             );
 161
 162     icache_rst <= rst or dbg_icache_rst or ex1_icache_inval;
 163
 164     fetch2_0: entity work.fetch2
 165         port map (
 166             clk => clk,
 167             rst => core_rst,
 168             stall_in => fetch2_stall_in,
 169             flush_in => flush,
 170             i_in => icache_to_fetch2,
 171             f_out => fetch2_to_decode1
 172             );
 173
 174     fetch2_stall_in <= decode2_stall_out;
 175
 176     decode1_0: entity work.decode1
 177         port map (
 178             clk => clk,
 179             rst => core_rst,
 180             stall_in => decode1_stall_in,
 181             flush_in => flush,
 182             f_in => fetch2_to_decode1,
 183             d_out => decode1_to_decode2
 184             );
 185
 186     decode1_stall_in <= decode2_stall_out;
 187
 188     decode2_0: entity work.decode2
 189         port map (
 190             clk => clk,
 191             rst => core_rst,
 192             stall_in => decode2_stall_in,
 193             stall_out => decode2_stall_out,
 194             flush_in => flush,
 195             complete_in => complete,
 196             stopped_out => dbg_core_is_stopped,
 197             d_in => decode1_to_decode2,
 198             e_out => decode2_to_execute1,
 199             l_out => decode2_to_loadstore1,
 200             m_out => decode2_to_multiply,
 201             d_out => decode2_to_divider,
 202             r_in => register_file_to_decode2,
 203             r_out => decode2_to_register_file,
 204             c_in => cr_file_to_decode2,
 205             c_out => decode2_to_cr_file
 206             );
 207     decode2_stall_in <= ex1_stall_out;
 208
 209     register_file_0: entity work.register_file
 210         generic map (
 211             SIM => SIM
 212             )
 213         port map (
 214             clk => clk,
 215             d_in => decode2_to_register_file,
 216             d_out => register_file_to_decode2,
 217             w_in => writeback_to_register_file,
 218             sim_dump => terminate,
 219             sim_dump_done => sim_cr_dump
 220             );
 221
 222     cr_file_0: entity work.cr_file
 223         generic map (
 224             SIM => SIM
 225             )
 226         port map (
 227             clk => clk,
 228             d_in => decode2_to_cr_file,
 229             d_out => cr_file_to_decode2,
 230             w_in => writeback_to_cr_file,
 231             sim_dump => sim_cr_dump
 232             );
 233
 234     execute1_0: entity work.execute1
 235         port map (
 236             clk => clk,
 237             flush_out => flush,
 238             stall_out => ex1_stall_out,
 239             e_in => decode2_to_execute1,
 240             f_out => execute1_to_fetch1,
 241             e_out => execute1_to_writeback,
 242             icache_inval => ex1_icache_inval,
 243             terminate_out => terminate
 244             );
 245
 246     loadstore1_0: entity work.loadstore1
 247         port map (
 248             clk => clk,
 249             l_in => decode2_to_loadstore1,
 250             l_out => loadstore1_to_dcache
 251             );
 252
 253     dcache_0: entity work.dcache
 254         generic map(
 255             LINE_SIZE => 64,
 256             NUM_LINES => 32,
 257             NUM_WAYS => 2
 258             )
 259         port map (
 260             clk => clk,
 261             rst => core_rst,
 262             d_in => loadstore1_to_dcache,
 263             d_out => dcache_to_writeback,
 264             wishbone_in => wishbone_data_in,
 265             wishbone_out => wishbone_data_out
 266             );
 267
 268     multiply_0: entity work.multiply
 269         port map (
 270             clk => clk,
 271             m_in => decode2_to_multiply,
 272             m_out => multiply_to_writeback
 273             );
 274
 275     divider_0: entity work.divider
 276         port map (
 277             clk => clk,
 278             rst => core_rst,
 279             d_in => decode2_to_divider,
 280             d_out => divider_to_writeback
 281             );
 282
 283     writeback_0: entity work.writeback
 284         port map (
 285             clk => clk,
 286             e_in => execute1_to_writeback,
 287             l_in => dcache_to_writeback,
 288             m_in => multiply_to_writeback,
 289             d_in => divider_to_writeback,
 290             w_out => writeback_to_register_file,
 291             c_out => writeback_to_cr_file,
 292             complete_out => complete
 293             );
 294
 295     debug_0: entity work.core_debug
 296         port map (
 297             clk => clk,
 298             rst => rst,
 299             dmi_addr => dmi_addr,
 300             dmi_din => dmi_din,
 301             dmi_dout => dmi_dout,
 302             dmi_req => dmi_req,
 303             dmi_wr => dmi_wr,
 304             dmi_ack => dmi_ack,
 305             core_stop => dbg_core_stop,
 306             core_rst => dbg_core_rst,
 307             icache_rst => dbg_icache_rst,
 308             terminate => terminate,
 309             core_stopped => dbg_core_is_stopped,
 310             nia => fetch1_to_icache.nia,
 311             terminated_out => terminated_out
 312             );
 313
 314 end behave;