2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
10 entity core_dram_tb is
12 MEMORY_SIZE : natural := (384*1024);
13 MAIN_RAM_FILE : string := "main_ram.bin";
14 DRAM_INIT_FILE : string := "";
15 DRAM_INIT_SIZE : natural := 16#c000#
19 architecture behave of core_dram_tb is
20 signal clk, rst: std_logic;
21 signal system_clk, soc_rst : std_ulogic;
24 constant clk_period : time := 10 ns;
27 signal wb_dram_in : wishbone_master_out;
28 signal wb_dram_out : wishbone_slave_out;
29 signal wb_ext_io_in : wb_io_master_out;
30 signal wb_ext_io_out : wb_io_slave_out;
31 signal wb_ext_is_dram_csr : std_ulogic;
32 signal wb_ext_is_dram_init : std_ulogic;
33 signal core_alt_reset : std_ulogic;
36 signal spi_sck : std_ulogic;
37 signal spi_cs_n : std_ulogic := '1';
38 signal spi_sdat_o : std_ulogic_vector(3 downto 0);
39 signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
40 signal spi_sdat_i : std_ulogic_vector(3 downto 0);
41 signal fl_hold_n : std_logic;
42 signal fl_wp_n : std_logic;
43 signal fl_mosi : std_logic;
44 signal fl_miso : std_logic;
47 function get_rom_size return natural is
49 if MEMORY_SIZE = 0 then
50 return DRAM_INIT_SIZE;
56 constant ROM_SIZE : natural := get_rom_size;
62 MEMORY_SIZE => MEMORY_SIZE,
63 RAM_INIT_FILE => MAIN_RAM_FILE,
65 DRAM_SIZE => 256 * 1024 * 1024,
66 DRAM_INIT_SIZE => ROM_SIZE,
67 CLK_FREQ => 100000000,
68 HAS_SPI_FLASH => true,
69 SPI_FLASH_DLINES => 4,
74 system_clk => system_clk,
75 wb_dram_in => wb_dram_in,
76 wb_dram_out => wb_dram_out,
77 wb_ext_io_in => wb_ext_io_in,
78 wb_ext_io_out => wb_ext_io_out,
79 wb_ext_is_dram_csr => wb_ext_is_dram_csr,
80 wb_ext_is_dram_init => wb_ext_is_dram_init,
81 spi_flash_sck => spi_sck,
82 spi_flash_cs_n => spi_cs_n,
83 spi_flash_sdat_o => spi_sdat_o,
84 spi_flash_sdat_oe => spi_sdat_oe,
85 spi_flash_sdat_i => spi_sdat_i,
86 alt_reset => core_alt_reset
89 flash: entity work.s25fl128s
91 TimingModel => "S25FL128SAGNFI000_R_30pF",
94 tdevice_PP256 => 100 ns,
95 tdevice_PP512 => 100 ns,
96 tdevice_WRR => 100 ns,
103 HOLDNeg => fl_hold_n,
109 fl_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
110 fl_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
111 fl_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
112 fl_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else '1' when spi_sdat_oe(0) = '1' else 'Z';
114 spi_sdat_i(0) <= fl_mosi;
115 spi_sdat_i(1) <= fl_miso;
116 spi_sdat_i(2) <= fl_wp_n;
117 spi_sdat_i(3) <= fl_hold_n;
119 dram: entity work.litedram_wrapper
125 DRAM_PORT_WIDTH => 128,
126 PAYLOAD_FILE => DRAM_INIT_FILE,
127 PAYLOAD_SIZE => ROM_SIZE
132 system_clk => system_clk,
133 system_reset => soc_rst,
134 core_alt_reset => core_alt_reset,
137 wb_out => wb_dram_out,
138 wb_ctrl_in => wb_ext_io_in,
139 wb_ctrl_out => wb_ext_io_out,
140 wb_ctrl_is_csr => wb_ext_is_dram_csr,
141 wb_ctrl_is_init => wb_ext_is_dram_init
147 wait for clk_period/2;
149 wait for clk_period/2;
155 wait for 10*clk_period;
160 jtag: entity work.sim_jtag;