core_dram_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core_dram_tb is
  10     generic (
  11         MEMORY_SIZE    : natural := (384*1024);
  12         MAIN_RAM_FILE  : string  := "main_ram.bin";
  13         DRAM_INIT_FILE : string  := "";
  14         DRAM_INIT_SIZE : natural := 16#c000#
  15         );
  16 end core_dram_tb;
  17
  18 architecture behave of core_dram_tb is
  19     signal clk, rst: std_logic;
  20     signal system_clk, soc_rst : std_ulogic;
  21
  22     -- testbench signals
  23     constant clk_period : time := 10 ns;
  24
  25     -- Sim DRAM
  26     signal wb_dram_in : wishbone_master_out;
  27     signal wb_dram_out : wishbone_slave_out;
  28     signal wb_dram_ctrl_in : wb_io_master_out;
  29     signal wb_dram_ctrl_out : wb_io_slave_out;
  30     signal wb_dram_is_csr   : std_ulogic;
  31     signal wb_dram_is_init  : std_ulogic;
  32     signal core_alt_reset : std_ulogic;
  33
  34     -- ROM size
  35     function get_rom_size return natural is
  36     begin
  37         if MEMORY_SIZE = 0 then
  38             return DRAM_INIT_SIZE;
  39         else
  40             return 0;
  41         end if;
  42     end function;
  43
  44     constant ROM_SIZE : natural := get_rom_size;
  45 begin
  46
  47     soc0: entity work.soc
  48         generic map(
  49             SIM => true,
  50             MEMORY_SIZE => MEMORY_SIZE,
  51             RAM_INIT_FILE => MAIN_RAM_FILE,
  52             RESET_LOW => false,
  53             HAS_DRAM => true,
  54             DRAM_SIZE => 256 * 1024 * 1024,
  55             DRAM_INIT_SIZE => ROM_SIZE,
  56             CLK_FREQ => 100000000
  57             )
  58         port map(
  59             rst => soc_rst,
  60             system_clk => system_clk,
  61             uart0_rxd => '0',
  62             uart0_txd => open,
  63             wb_dram_in => wb_dram_in,
  64             wb_dram_out => wb_dram_out,
  65             wb_dram_ctrl_in => wb_dram_ctrl_in,
  66             wb_dram_ctrl_out => wb_dram_ctrl_out,
  67             wb_dram_is_csr => wb_dram_is_csr,
  68             wb_dram_is_init => wb_dram_is_init,
  69             alt_reset => core_alt_reset
  70             );
  71
  72     dram: entity work.litedram_wrapper
  73         generic map(
  74             DRAM_ABITS => 24,
  75             DRAM_ALINES => 1,
  76             PAYLOAD_FILE => DRAM_INIT_FILE,
  77             PAYLOAD_SIZE => ROM_SIZE
  78             )
  79         port map(
  80             clk_in              => clk,
  81             rst             => rst,
  82             system_clk  => system_clk,
  83             system_reset        => soc_rst,
  84             core_alt_reset      => core_alt_reset,
  85             pll_locked  => open,
  86
  87             wb_in               => wb_dram_in,
  88             wb_out              => wb_dram_out,
  89             wb_ctrl_in  => wb_dram_ctrl_in,
  90             wb_ctrl_out => wb_dram_ctrl_out,
  91             wb_ctrl_is_csr  => wb_dram_is_csr,
  92             wb_ctrl_is_init => wb_dram_is_init,
  93
  94             init_done   => open,
  95             init_error  => open,
  96
  97             ddram_a             => open,
  98             ddram_ba    => open,
  99             ddram_ras_n => open,
 100             ddram_cas_n => open,
 101             ddram_we_n  => open,
 102             ddram_cs_n  => open,
 103             ddram_dm    => open,
 104             ddram_dq    => open,
 105             ddram_dqs_p => open,
 106             ddram_dqs_n => open,
 107             ddram_clk_p => open,
 108             ddram_clk_n => open,
 109             ddram_cke   => open,
 110             ddram_odt   => open,
 111             ddram_reset_n       => open
 112             );
 113
 114     clk_process: process
 115     begin
 116         clk <= '0';
 117         wait for clk_period/2;
 118         clk <= '1';
 119         wait for clk_period/2;
 120     end process;
 121
 122     rst_process: process
 123     begin
 124         rst <= '1';
 125         wait for 10*clk_period;
 126         rst <= '0';
 127         wait;
 128     end process;
 129
 130     jtag: entity work.sim_jtag;
 131
 132 end;