core_dram_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8 use work.utils.all;
   9
  10 entity core_dram_tb is
  11     generic (
  12         MEMORY_SIZE    : natural := (384*1024);
  13         MAIN_RAM_FILE  : string  := "main_ram.bin";
  14         DRAM_INIT_FILE : string  := "";
  15         DRAM_INIT_SIZE : natural := 16#c000#
  16         );
  17 end core_dram_tb;
  18
  19 architecture behave of core_dram_tb is
  20     signal clk, rst: std_logic;
  21     signal system_clk, soc_rst : std_ulogic;
  22
  23     -- testbench signals
  24     constant clk_period : time := 10 ns;
  25
  26     -- Sim DRAM
  27     signal wb_dram_in : wishbone_master_out;
  28     signal wb_dram_out : wishbone_slave_out;
  29     signal wb_dram_ctrl_in : wb_io_master_out;
  30     signal wb_dram_ctrl_out : wb_io_slave_out;
  31     signal wb_dram_is_csr   : std_ulogic;
  32     signal wb_dram_is_init  : std_ulogic;
  33     signal core_alt_reset : std_ulogic;
  34
  35     -- SPI
  36     signal spi_sck     : std_ulogic;
  37     signal spi_cs_n    : std_ulogic := '1';
  38     signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
  39     signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
  40     signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
  41     signal fl_hold_n   : std_logic;
  42     signal fl_wp_n     : std_logic;
  43     signal fl_mosi     : std_logic;
  44     signal fl_miso     : std_logic;
  45
  46     -- ROM size
  47     function get_rom_size return natural is
  48     begin
  49         if MEMORY_SIZE = 0 then
  50             return DRAM_INIT_SIZE;
  51         else
  52             return 0;
  53         end if;
  54     end function;
  55
  56     constant ROM_SIZE : natural := get_rom_size;
  57 begin
  58
  59     soc0: entity work.soc
  60         generic map(
  61             SIM => true,
  62             MEMORY_SIZE => MEMORY_SIZE,
  63             RAM_INIT_FILE => MAIN_RAM_FILE,
  64             RESET_LOW => false,
  65             HAS_DRAM => true,
  66             DRAM_SIZE => 256 * 1024 * 1024,
  67             DRAM_INIT_SIZE => ROM_SIZE,
  68             CLK_FREQ => 100000000,
  69             HAS_SPI_FLASH    => true,
  70             SPI_FLASH_DLINES => 4,
  71             SPI_FLASH_OFFSET => 0
  72             )
  73         port map(
  74             rst => soc_rst,
  75             system_clk => system_clk,
  76             uart0_rxd => '0',
  77             uart0_txd => open,
  78             wb_dram_in => wb_dram_in,
  79             wb_dram_out => wb_dram_out,
  80             wb_dram_ctrl_in => wb_dram_ctrl_in,
  81             wb_dram_ctrl_out => wb_dram_ctrl_out,
  82             wb_dram_is_csr => wb_dram_is_csr,
  83             wb_dram_is_init => wb_dram_is_init,
  84             spi_flash_sck     => spi_sck,
  85             spi_flash_cs_n    => spi_cs_n,
  86             spi_flash_sdat_o  => spi_sdat_o,
  87             spi_flash_sdat_oe => spi_sdat_oe,
  88             spi_flash_sdat_i  => spi_sdat_i,
  89             alt_reset => core_alt_reset
  90             );
  91
  92         flash: entity work.s25fl128s
  93         generic map (
  94             TimingModel => "S25FL128SAGNFI000_R_30pF",
  95             LongTimming => false,
  96             tdevice_PU => 10 ns,
  97             tdevice_PP256 => 100 ns,
  98             tdevice_PP512 => 100 ns,
  99             tdevice_WRR   => 100 ns,
 100             UserPreload => TRUE
 101             )
 102         port map(
 103             SCK => spi_sck,
 104             SI => fl_mosi,
 105             CSNeg => spi_cs_n,
 106             HOLDNeg => fl_hold_n,
 107             WPNeg => fl_wp_n,
 108             RSTNeg => '1',
 109             SO => fl_miso
 110             );
 111
 112     fl_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
 113     fl_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
 114     fl_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
 115     fl_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else '1' when spi_sdat_oe(0) = '1' else 'Z';
 116
 117     spi_sdat_i(0) <= fl_mosi;
 118     spi_sdat_i(1) <= fl_miso;
 119     spi_sdat_i(2) <= fl_wp_n;
 120     spi_sdat_i(3) <= fl_hold_n;
 121
 122     dram: entity work.litedram_wrapper
 123         generic map(
 124             DRAM_ABITS => 24,
 125             DRAM_ALINES => 1,
 126             PAYLOAD_FILE => DRAM_INIT_FILE,
 127             PAYLOAD_SIZE => ROM_SIZE
 128             )
 129         port map(
 130             clk_in              => clk,
 131             rst             => rst,
 132             system_clk  => system_clk,
 133             system_reset        => soc_rst,
 134             core_alt_reset      => core_alt_reset,
 135             pll_locked  => open,
 136
 137             wb_in               => wb_dram_in,
 138             wb_out              => wb_dram_out,
 139             wb_ctrl_in  => wb_dram_ctrl_in,
 140             wb_ctrl_out => wb_dram_ctrl_out,
 141             wb_ctrl_is_csr  => wb_dram_is_csr,
 142             wb_ctrl_is_init => wb_dram_is_init,
 143
 144             init_done   => open,
 145             init_error  => open,
 146
 147             ddram_a             => open,
 148             ddram_ba    => open,
 149             ddram_ras_n => open,
 150             ddram_cas_n => open,
 151             ddram_we_n  => open,
 152             ddram_cs_n  => open,
 153             ddram_dm    => open,
 154             ddram_dq    => open,
 155             ddram_dqs_p => open,
 156             ddram_dqs_n => open,
 157             ddram_clk_p => open,
 158             ddram_clk_n => open,
 159             ddram_cke   => open,
 160             ddram_odt   => open,
 161             ddram_reset_n       => open
 162             );
 163
 164     clk_process: process
 165     begin
 166         clk <= '0';
 167         wait for clk_period/2;
 168         clk <= '1';
 169         wait for clk_period/2;
 170     end process;
 171
 172     rst_process: process
 173     begin
 174         rst <= '1';
 175         wait for 10*clk_period;
 176         rst <= '0';
 177         wait;
 178     end process;
 179
 180     jtag: entity work.sim_jtag;
 181
 182 end;