2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
9 entity core_flash_tb is
12 architecture behave of core_flash_tb is
13 signal clk, rst: std_logic;
16 constant clk_period : time := 10 ns;
19 signal spi_sck : std_ulogic;
20 signal spi_cs_n : std_ulogic := '1';
21 signal spi_sdat_o : std_ulogic_vector(3 downto 0);
22 signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
23 signal spi_sdat_i : std_ulogic_vector(3 downto 0);
24 signal fl_hold_n : std_logic;
25 signal fl_wp_n : std_logic;
26 signal fl_mosi : std_logic;
27 signal fl_miso : std_logic;
33 MEMORY_SIZE => (384*1024),
34 RAM_INIT_FILE => "main_ram.bin",
35 CLK_FREQ => 100000000,
36 HAS_SPI_FLASH => true,
37 SPI_FLASH_DLINES => 4,
43 spi_flash_sck => spi_sck,
44 spi_flash_cs_n => spi_cs_n,
45 spi_flash_sdat_o => spi_sdat_o,
46 spi_flash_sdat_oe => spi_sdat_oe,
47 spi_flash_sdat_i => spi_sdat_i
50 flash: entity work.s25fl128s
52 TimingModel => "S25FL128SAGNFI000_R_30pF",
55 tdevice_PP256 => 100 ns,
56 tdevice_PP512 => 100 ns,
69 fl_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
70 fl_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
71 fl_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
72 fl_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else '1' when spi_sdat_oe(0) = '1' else 'Z';
74 spi_sdat_i(0) <= fl_mosi;
75 spi_sdat_i(1) <= fl_miso;
76 spi_sdat_i(2) <= fl_wp_n;
77 spi_sdat_i(3) <= fl_hold_n;
82 wait for clk_period/2;
84 wait for clk_period/2;
90 wait for 10*clk_period;
95 jtag: entity work.sim_jtag;