core_flash_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core_flash_tb is
  10 end core_flash_tb;
  11
  12 architecture behave of core_flash_tb is
  13         signal clk, rst: std_logic;
  14
  15         -- testbench signals
  16         constant clk_period : time := 10 ns;
  17
  18         -- Dummy DRAM
  19         signal wb_dram_in : wishbone_master_out;
  20         signal wb_dram_out : wishbone_slave_out;
  21         signal wb_dram_ctrl_in : wb_io_master_out;
  22         signal wb_dram_ctrl_out : wb_io_slave_out;
  23
  24         -- SPI
  25         signal spi_sck     : std_ulogic;
  26         signal spi_cs_n    : std_ulogic := '1';
  27         signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
  28         signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
  29         signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
  30         signal fl_hold_n   : std_logic;
  31         signal fl_wp_n     : std_logic;
  32         signal fl_mosi     : std_logic;
  33         signal fl_miso     : std_logic;
  34 begin
  35
  36     soc0: entity work.soc
  37         generic map(
  38             SIM => true,
  39             MEMORY_SIZE => (384*1024),
  40             RAM_INIT_FILE => "main_ram.bin",
  41             RESET_LOW => false,
  42             CLK_FREQ => 100000000,
  43             HAS_SPI_FLASH    => true,
  44             SPI_FLASH_DLINES => 4,
  45             SPI_FLASH_OFFSET => 0
  46             )
  47         port map(
  48             rst => rst,
  49             system_clk => clk,
  50             uart0_rxd => '0',
  51             uart0_txd => open,
  52             wb_dram_in => wb_dram_in,
  53             wb_dram_out => wb_dram_out,
  54             wb_dram_ctrl_in => wb_dram_ctrl_in,
  55             wb_dram_ctrl_out => wb_dram_ctrl_out,
  56             spi_flash_sck     => spi_sck,
  57             spi_flash_cs_n    => spi_cs_n,
  58             spi_flash_sdat_o  => spi_sdat_o,
  59             spi_flash_sdat_oe => spi_sdat_oe,
  60             spi_flash_sdat_i  => spi_sdat_i,
  61             alt_reset => '0'
  62             );
  63
  64     flash: entity work.s25fl128s
  65         generic map (
  66             TimingModel => "S25FL128SAGNFI000_R_30pF",
  67             LongTimming => false,
  68             tdevice_PU => 10 ns,
  69             tdevice_PP256 => 100 ns,
  70             tdevice_PP512 => 100 ns,
  71             tdevice_WRR   => 100 ns
  72             )
  73         port map(
  74             SCK => spi_sck,
  75             SI => fl_mosi,
  76             CSNeg => spi_cs_n,
  77             HOLDNeg => fl_hold_n,
  78             WPNeg => fl_wp_n,
  79             RSTNeg => '1',
  80             SO => fl_miso
  81             );
  82
  83     fl_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
  84     fl_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
  85     fl_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
  86     fl_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else '1' when spi_sdat_oe(0) = '1' else 'Z';
  87
  88     spi_sdat_i(0) <= fl_mosi;
  89     spi_sdat_i(1) <= fl_miso;
  90     spi_sdat_i(2) <= fl_wp_n;
  91     spi_sdat_i(3) <= fl_hold_n;
  92
  93     clk_process: process
  94     begin
  95         clk <= '0';
  96         wait for clk_period/2;
  97         clk <= '1';
  98         wait for clk_period/2;
  99     end process;
 100
 101     rst_process: process
 102     begin
 103         rst <= '1';
 104         wait for 10*clk_period;
 105         rst <= '0';
 106         wait;
 107     end process;
 108
 109     jtag: entity work.sim_jtag;
 110
 111     -- Dummy DRAM
 112     wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
 113     wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
 114     wb_dram_out.stall <= '0';
 115     wb_dram_ctrl_out.ack <= wb_dram_ctrl_in.cyc and wb_dram_ctrl_in.stb;
 116     wb_dram_ctrl_out.dat <= x"FFFFFFFF";
 117     wb_dram_ctrl_out.stall <= '0';
 118
 119 end;