core_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core_tb is
  10 end core_tb;
  11
  12 architecture behave of core_tb is
  13         signal clk, rst: std_logic;
  14
  15         -- testbench signals
  16         constant clk_period : time := 10 ns;
  17
  18         -- Dummy DRAM
  19         signal wb_dram_in : wishbone_master_out;
  20         signal wb_dram_out : wishbone_slave_out;
  21         signal wb_dram_ctrl_in : wb_io_master_out;
  22         signal wb_dram_ctrl_out : wb_io_slave_out;
  23
  24         -- Dummy SPI
  25         signal spi_sdat_i : std_ulogic_vector(0 downto 0);
  26 begin
  27
  28     soc0: entity work.soc
  29         generic map(
  30             SIM => true,
  31             MEMORY_SIZE => (384*1024),
  32             RAM_INIT_FILE => "main_ram.bin",
  33             RESET_LOW => false,
  34             CLK_FREQ => 100000000,
  35             HAS_SPI_FLASH => false
  36             )
  37         port map(
  38             rst => rst,
  39             system_clk => clk,
  40             uart0_rxd => '0',
  41             uart0_txd => open,
  42             spi_flash_sck => open,
  43             spi_flash_cs_n => open,
  44             spi_flash_sdat_o => open,
  45             spi_flash_sdat_oe => open,
  46             spi_flash_sdat_i => spi_sdat_i,
  47             wb_dram_in => wb_dram_in,
  48             wb_dram_out => wb_dram_out,
  49             wb_dram_ctrl_in => wb_dram_ctrl_in,
  50             wb_dram_ctrl_out => wb_dram_ctrl_out,
  51             alt_reset => '0'
  52             );
  53     spi_sdat_i(0) <= '1';
  54
  55     clk_process: process
  56     begin
  57         clk <= '0';
  58         wait for clk_period/2;
  59         clk <= '1';
  60         wait for clk_period/2;
  61     end process;
  62
  63     rst_process: process
  64     begin
  65         rst <= '1';
  66         wait for 10*clk_period;
  67         rst <= '0';
  68         wait;
  69     end process;
  70
  71     jtag: entity work.sim_jtag;
  72
  73     -- Dummy DRAM
  74     wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
  75     wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
  76     wb_dram_out.stall <= '0';
  77     wb_dram_ctrl_out.ack <= wb_dram_ctrl_in.cyc and wb_dram_ctrl_in.stb;
  78     wb_dram_ctrl_out.dat <= x"FFFFFFFF";
  79     wb_dram_ctrl_out.stall <= '0';
  80
  81 end;