core_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core_tb is
  10 end core_tb;
  11
  12 architecture behave of core_tb is
  13         signal clk, rst: std_logic;
  14
  15         -- testbench signals
  16         constant clk_period : time := 10 ns;
  17
  18         -- Dummy DRAM
  19         signal wb_dram_in : wishbone_master_out;
  20         signal wb_dram_out : wishbone_slave_out;
  21 begin
  22
  23     soc0: entity work.soc
  24         generic map(
  25             SIM => true,
  26             MEMORY_SIZE => (384*1024),
  27             RAM_INIT_FILE => "main_ram.bin",
  28             RESET_LOW => false,
  29             CLK_FREQ => 100000000
  30             )
  31         port map(
  32             rst => rst,
  33             system_clk => clk,
  34             uart0_rxd => '0',
  35             uart0_txd => open,
  36             wb_dram_in => wb_dram_in,
  37             wb_dram_out => wb_dram_out,
  38             alt_reset => '0'
  39             );
  40
  41     clk_process: process
  42     begin
  43         clk <= '0';
  44         wait for clk_period/2;
  45         clk <= '1';
  46         wait for clk_period/2;
  47     end process;
  48
  49     rst_process: process
  50     begin
  51         rst <= '1';
  52         wait for 10*clk_period;
  53         rst <= '0';
  54         wait;
  55     end process;
  56
  57     jtag: entity work.sim_jtag;
  58
  59     -- Dummy DRAM
  60     wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
  61     wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
  62     wb_dram_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack;
  63
  64 end;