core_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use std.textio.all;
   5
   6 library work;
   7 use work.common.all;
   8 use work.wishbone_types.all;
   9
  10 entity core_tb is
  11 end core_tb;
  12
  13 architecture behave of core_tb is
  14         signal clk, rst: std_logic;
  15
  16         signal wishbone_dcore_in : wishbone_slave_out;
  17         signal wishbone_dcore_out : wishbone_master_out;
  18
  19         signal wishbone_icore_in : wishbone_slave_out;
  20         signal wishbone_icore_out : wishbone_master_out;
  21
  22         signal wishbone_core_in : wishbone_slave_out;
  23         signal wishbone_core_out : wishbone_master_out;
  24
  25         signal wishbone_ram_in : wishbone_slave_out;
  26         signal wishbone_ram_out : wishbone_master_out;
  27
  28         signal wishbone_uart_in : wishbone_slave_out;
  29         signal wishbone_uart_out : wishbone_master_out;
  30
  31         signal registers : regfile;
  32         signal terminate : std_ulogic;
  33
  34         -- testbench signals
  35         constant clk_period : time := 10 ns;
  36 begin
  37         core_0: entity work.core
  38                 generic map (SIM => true)
  39             port map (clk => clk, rst => rst,
  40                       wishbone_insn_in => wishbone_icore_in,
  41                       wishbone_insn_out => wishbone_icore_out,
  42                       wishbone_data_in => wishbone_dcore_in,
  43                       wishbone_data_out => wishbone_dcore_out,
  44                       registers => registers, terminate_out => terminate);
  45
  46         simple_ram_0: entity work.simple_ram_behavioural
  47                 generic map ( filename => "simple_ram_behavioural.bin", size => 524288)
  48                 port map (clk => clk, rst => rst, wishbone_in => wishbone_ram_out, wishbone_out => wishbone_ram_in);
  49
  50         simple_uart_0: entity work.sim_uart
  51                 port map ( clk => clk, reset => rst, wishbone_in => wishbone_uart_out, wishbone_out => wishbone_uart_in);
  52
  53
  54         wishbone_arbiter_0: entity work.wishbone_arbiter
  55                 port map (clk => clk, rst => rst,
  56                           wb1_in => wishbone_dcore_out, wb1_out => wishbone_dcore_in,
  57                           wb2_in => wishbone_icore_out, wb2_out => wishbone_icore_in,
  58                           wb_out => wishbone_core_out, wb_in => wishbone_core_in);
  59
  60         bus_process: process(wishbone_core_out, wishbone_ram_in, wishbone_uart_in)
  61           -- Selected slave
  62           type slave_type is (SLAVE_UART, SLAVE_MEMORY, SLAVE_NONE);
  63           variable slave : slave_type;
  64         begin
  65                 -- Simple address decoder
  66                 slave := SLAVE_NONE;
  67                 if wishbone_core_out.adr(31 downto 24) = x"00" then
  68                         slave := SLAVE_MEMORY;
  69                 elsif wishbone_core_out.adr(31 downto 24) = x"c0" then
  70                         if wishbone_core_out.adr(15 downto 12) = x"2" then
  71                                 slave := SLAVE_UART;
  72                         end if;
  73                 end if;
  74
  75                 -- Wishbone muxing:
  76                 -- Start with all master signals to all slaves, then override
  77                 -- cyc and stb accordingly
  78                 wishbone_ram_out <= wishbone_core_out;
  79                 wishbone_uart_out <= wishbone_core_out;
  80                 if slave = SLAVE_MEMORY then
  81                         wishbone_core_in <= wishbone_ram_in;
  82                 else
  83                         wishbone_ram_out.cyc <= '0';
  84                         wishbone_ram_out.stb <= '0';
  85                 end if;
  86                 if slave = SLAVE_UART then
  87                         wishbone_core_in <= wishbone_uart_in;
  88                 else
  89                         wishbone_uart_out.cyc <= '0';
  90                         wishbone_uart_out.stb <= '0';
  91                 end if;
  92                 if slave = SLAVE_NONE then
  93                         wishbone_core_in.dat <= (others => '1');
  94                         wishbone_core_in.ack <= wishbone_core_out.cyc and
  95                                                 wishbone_core_out.stb;
  96                 end if;
  97         end process;
  98
  99         clk_process: process
 100         begin
 101                 clk <= '0';
 102                 wait for clk_period/2;
 103                 clk <= '1';
 104                 wait for clk_period/2;
 105         end process;
 106
 107         rst_process: process
 108         begin
 109                 rst <= '1';
 110                 wait for 10*clk_period;
 111                 rst <= '0';
 112                 wait;
 113         end process;
 114
 115         dump_registers: process(all)
 116         begin
 117                 if terminate = '1' then
 118                         loop_0: for i in 0 to 31 loop
 119                                 report "REG " & to_hstring(registers(i));
 120                         end loop loop_0;
 121                         assert false report "end of test" severity failure;
 122                 end if;
 123         end process;
 124 end;