countzero.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6
   7 entity zero_counter is
   8     port (
   9         rs          : in std_ulogic_vector(63 downto 0);
  10         count_right : in std_ulogic;
  11         is_32bit    : in std_ulogic;
  12         result      : out std_ulogic_vector(63 downto 0)
  13         );
  14 end entity zero_counter;
  15
  16 architecture behaviour of zero_counter is
  17 begin
  18     zerocounter0: process(all)
  19         variable l32, r32 : std_ulogic;
  20         variable v32      : std_ulogic_vector(31 downto 0);
  21         variable v16      : std_ulogic_vector(15 downto 0);
  22         variable v8       : std_ulogic_vector(7 downto 0);
  23         variable v4       : std_ulogic_vector(3 downto 0);
  24         variable sel      : std_ulogic_vector(5 downto 0);
  25     begin
  26         l32 := '0';
  27         r32 := '0';
  28         v32 := (others => '0');
  29         v16 := (others => '0');
  30         v8  := (others => '0');
  31         v4  := (others => '0');
  32         sel := (others => '0');
  33
  34         l32 := or (rs(63 downto 32));
  35         r32 := or (rs(31 downto 0));
  36         if (l32 = '0' or is_32bit = '1') and r32 = '0' then
  37             -- operand is zero, return 32 for 32-bit, else 64
  38             result <= x"00000000000000" & '0' & not is_32bit & is_32bit & "00000";
  39         else
  40
  41             if count_right = '0' then
  42                 sel(5) := l32 and (not is_32bit);
  43             else
  44                 sel(5) := (not r32) and (not is_32bit);
  45             end if;
  46             if sel(5) = '1' then
  47                 v32 := rs(63 downto 32);
  48             else
  49                 v32 := rs(31 downto 0);
  50             end if;
  51
  52             if count_right = '0' then
  53                 sel(4) := or (v32(31 downto 16));
  54             else
  55                 sel(4) := not (or (v32(15 downto 0)));
  56             end if;
  57             if sel(4) = '1' then
  58                 v16 := v32(31 downto 16);
  59             else
  60                 v16 := v32(15 downto 0);
  61             end if;
  62
  63             if count_right = '0' then
  64                 sel(3) := or (v16(15 downto 8));
  65             else
  66                 sel(3) := not (or (v16(7 downto 0)));
  67             end if;
  68             if sel(3) = '1' then
  69                 v8 := v16(15 downto 8);
  70             else
  71                 v8 := v16(7 downto 0);
  72             end if;
  73
  74             if count_right = '0' then
  75                 sel(2) := or (v8(7 downto 4));
  76             else
  77                 sel(2) := not (or (v8(3 downto 0)));
  78             end if;
  79             if sel(2) = '1' then
  80                 v4 := v8(7 downto 4);
  81             else
  82                 v4 := v8(3 downto 0);
  83             end if;
  84
  85             if count_right = '0' then
  86                 if v4(3) = '1' then
  87                     sel(1 downto 0) := "11";
  88                 elsif v4(2) = '1' then
  89                     sel(1 downto 0) := "10";
  90                 elsif v4(1) = '1' then
  91                     sel(1 downto 0) := "01";
  92                 else
  93                     sel(1 downto 0) := "00";
  94                 end if;
  95                 result <= x"00000000000000" & "00" & (not sel(5) and not is_32bit) & not sel(4 downto 0);
  96             else
  97                 if v4(0) = '1' then
  98                     sel(1 downto 0) := "00";
  99                 elsif v4(1) = '1' then
 100                     sel(1 downto 0) := "01";
 101                 elsif v4(2) = '1' then
 102                     sel(1 downto 0) := "10";
 103                 else
 104                     sel(1 downto 0) := "11";
 105                 end if;
 106                 result <= x"00000000000000" & "00" & sel;
 107             end if;
 108         end if;
 109
 110     end process;
 111 end behaviour;