countzero_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.glibc_random.all;
   8
   9 entity countzero_tb is
  10 end countzero_tb;
  11
  12 architecture behave of countzero_tb is
  13     constant clk_period: time := 10 ns;
  14     signal rs: std_ulogic_vector(63 downto 0);
  15     signal is_32bit, count_right: std_ulogic := '0';
  16     signal result: std_ulogic_vector(63 downto 0);
  17     signal randno: std_ulogic_vector(63 downto 0);
  18
  19 begin
  20     zerocounter_0: entity work.zero_counter
  21         port map (
  22             rs => rs,
  23             result => result,
  24             count_right => count_right,
  25             is_32bit => is_32bit
  26         );
  27
  28     stim_process: process
  29         variable r: std_ulogic_vector(63 downto 0);
  30     begin
  31         -- test with input = 0
  32         report "test zero input";
  33         rs <= (others => '0');
  34         is_32bit <= '0';
  35         count_right <= '0';
  36         wait for clk_period;
  37         assert result = x"0000000000000040"
  38             report "bad cntlzd 0 = " & to_hstring(result);
  39         count_right <= '1';
  40         wait for clk_period;
  41         assert result = x"0000000000000040"
  42             report "bad cnttzd 0 = " & to_hstring(result);
  43         is_32bit <= '1';
  44         count_right <= '0';
  45         wait for clk_period;
  46         assert result = x"0000000000000020"
  47             report "bad cntlzw 0 = " & to_hstring(result);
  48         count_right <= '1';
  49         wait for clk_period;
  50         assert result = x"0000000000000020"
  51             report "bad cnttzw 0 = " & to_hstring(result);
  52
  53         report "test cntlzd/w";
  54         count_right <= '0';
  55         for j in 0 to 100 loop
  56             r := pseudorand(64);
  57             r(63) := '1';
  58             for i in 0 to 63 loop
  59                 rs <= r;
  60                 is_32bit <= '0';
  61                 wait for clk_period;
  62                 assert to_integer(unsigned(result)) = i
  63                     report "bad cntlzd " & to_hstring(rs) & " -> " & to_hstring(result);
  64                 rs <= r(31 downto 0) & r(63 downto 32);
  65                 is_32bit <= '1';
  66                 wait for clk_period;
  67                 if i < 32 then
  68                     assert to_integer(unsigned(result)) = i
  69                         report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result);
  70                 else
  71                     assert to_integer(unsigned(result)) = 32
  72                         report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result);
  73                 end if;
  74                 r := '0' & r(63 downto 1);
  75             end loop;
  76         end loop;
  77
  78         report "test cnttzd/w";
  79         count_right <= '1';
  80         for j in 0 to 100 loop
  81             r := pseudorand(64);
  82             r(0) := '1';
  83             for i in 0 to 63 loop
  84                 rs <= r;
  85                 is_32bit <= '0';
  86                 wait for clk_period;
  87                 assert to_integer(unsigned(result)) = i
  88                     report "bad cnttzd " & to_hstring(rs) & " -> " & to_hstring(result);
  89                 is_32bit <= '1';
  90                 wait for clk_period;
  91                 if i < 32 then
  92                     assert to_integer(unsigned(result)) = i
  93                         report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result);
  94                 else
  95                     assert to_integer(unsigned(result)) = 32
  96                         report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result);
  97                 end if;
  98                 r := r(62 downto 0) & '0';
  99             end loop;
 100         end loop;
 101
 102         assert false report "end of test" severity failure;
 103         wait;
 104     end process;
 105 end behave;