cr_file.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity cr_file is
   9     generic (
  10         SIM : boolean := false
  11         );
  12     port(
  13         clk   : in std_logic;
  14
  15         d_in  : in Decode2ToCrFileType;
  16         d_out : out CrFileToDecode2Type;
  17
  18         w_in  : in WritebackToCrFileType;
  19
  20         -- debug
  21         sim_dump : in std_ulogic
  22         );
  23 end entity cr_file;
  24
  25 architecture behaviour of cr_file is
  26     signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
  27     signal crs_updated : std_ulogic_vector(31 downto 0);
  28     signal xerc : xer_common_t := xerc_init;
  29     signal xerc_updated : xer_common_t;
  30 begin
  31     cr_create_0: process(all)
  32         variable hi, lo : integer := 0;
  33         variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0');
  34     begin
  35         cr_tmp := crs;
  36
  37         for i in 0 to 7 loop
  38             if w_in.write_cr_mask(i) = '1' then
  39                 lo := i*4;
  40                 hi := lo + 3;
  41                 cr_tmp(hi downto lo) := w_in.write_cr_data(hi downto lo);
  42             end if;
  43         end loop;
  44
  45         crs_updated <= cr_tmp;
  46
  47         if w_in.write_xerc_enable = '1' then
  48             xerc_updated <= w_in.write_xerc_data;
  49         else
  50             xerc_updated <= xerc;
  51         end if;
  52
  53     end process;
  54
  55     -- synchronous writes
  56     cr_write_0: process(clk)
  57     begin
  58         if rising_edge(clk) then
  59             if w_in.write_cr_enable = '1' then
  60                 report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
  61                 crs <= crs_updated;
  62             end if;
  63             if w_in.write_xerc_enable = '1' then
  64                 report "Writing XERC";
  65                 xerc <= xerc_updated;
  66             end if;
  67         end if;
  68     end process;
  69
  70     -- asynchronous reads
  71     cr_read_0: process(all)
  72     begin
  73         -- just return the entire CR to make mfcrf easier for now
  74         if d_in.read = '1' then
  75             report "Reading CR " & to_hstring(crs_updated);
  76         end if;
  77         d_out.read_cr_data <= crs_updated;
  78         d_out.read_xerc_data <= xerc_updated;
  79     end process;
  80
  81     sim_dump_test: if SIM generate
  82         dump_cr: process(all)
  83         begin
  84             if sim_dump = '1' then
  85                 report "CR 00000000" & to_hstring(crs);
  86                 assert false report "end of test" severity failure;
  87             end if;
  88         end process;
  89     end generate;
  90
  91 end architecture behaviour;