Initial import of microwatt
[microwatt.git] / cr_file.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 library work;
6 use work.common.all;
7
8 entity cr_file is
9 port(
10 clk : in std_logic;
11
12 d_in : in Decode2ToCrFileType;
13 d_out : out CrFileToDecode2Type;
14
15 w_in : in WritebackToCrFileType
16 );
17 end entity cr_file;
18
19 architecture behaviour of cr_file is
20 signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
21 begin
22 -- synchronous writes
23 cr_write_0: process(clk)
24 variable hi, lo : integer := 0;
25 begin
26 if rising_edge(clk) then
27 if w_in.write_cr_enable = '1' then
28 report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
29
30 for i in 0 to 7 loop
31 if w_in.write_cr_mask(i) = '1' then
32 lo := i*4;
33 hi := lo + 3;
34 crs(hi downto lo) <= w_in.write_cr_data(hi downto lo);
35 end if;
36 end loop;
37 end if;
38 end if;
39 end process cr_write_0;
40
41 -- asynchronous reads
42 cr_read_0: process(all)
43 variable hi, lo : integer := 0;
44 begin
45 --lo := (7-d_in.read_cr_nr_1)*4;
46 --hi := lo + 3;
47
48 --report "read " & integer'image(d_in.read_cr_nr_1) & " from CR " & to_hstring(crs(hi downto lo));
49 --d_out.read_cr_data_1 <= crs(hi downto lo);
50
51 -- Also return the entire CR to make mfcrf easier for now
52 report "read CR " & to_hstring(crs);
53 d_out.read_cr_data <= crs;
54
55 -- -- Forward any written data
56 -- if w_in.write_cr_enable = '1' then
57 -- if d_in.read_cr_nr_1 = w_in.write_cr_nr then
58 -- d_out.read_cr_data_1 <= w_in.write_cr_data;
59 -- end if;
60 -- if d_in.read_cr_nr_2 = w_in.write_cr_nr then
61 -- d_out.read_cr_data_2 <= w_in.write_cr_data;
62 -- end if;
63 -- end if;
64 end process cr_read_0;
65 end architecture behaviour;