cr_file.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity cr_file is
   9         port(
  10                 clk   : in std_logic;
  11
  12                 d_in  : in Decode2ToCrFileType;
  13                 d_out : out CrFileToDecode2Type;
  14
  15                 w_in  : in WritebackToCrFileType
  16         );
  17 end entity cr_file;
  18
  19 architecture behaviour of cr_file is
  20         signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
  21         signal crs_updated : std_ulogic_vector(31 downto 0) := (others => '0');
  22 begin
  23         cr_create_0: process(all)
  24                 variable hi, lo : integer := 0;
  25         begin
  26                 for i in 0 to 7 loop
  27                         if w_in.write_cr_mask(i) = '1' then
  28                                 lo := i*4;
  29                                 hi := lo + 3;
  30                                 crs_updated(hi downto lo) <= w_in.write_cr_data(hi downto lo);
  31                         end if;
  32                 end loop;
  33         end process;
  34
  35         -- synchronous writes
  36         cr_write_0: process(clk)
  37         begin
  38                 if rising_edge(clk) then
  39                         if w_in.write_cr_enable = '1' then
  40                                 report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
  41                                 crs <= crs_updated;
  42                         end if;
  43                 end if;
  44         end process;
  45
  46         -- asynchronous reads
  47         cr_read_0: process(all)
  48                 variable hi, lo : integer := 0;
  49         begin
  50                 -- just return the entire CR to make mfcrf easier for now
  51                 if d_in.read = '1' then
  52                         report "Reading CR " & to_hstring(crs_updated);
  53                 end if;
  54                 if w_in.write_cr_enable then
  55                         d_out.read_cr_data <= crs_updated;
  56                 else
  57                         d_out.read_cr_data <= crs;
  58                 end if;
  59         end process;
  60 end architecture behaviour;