2 -- Set associative dcache write-through
4 -- TODO (in no specific order):
6 -- * See list in icache.vhdl
7 -- * Complete load misses on the cycle when WB data comes instead of
8 -- at the end of line (this requires dealing with requests coming in
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
19 use work.wishbone_types.all;
24 LINE_SIZE : positive := 64;
25 -- Number of lines in a set
26 NUM_LINES : positive := 32;
28 NUM_WAYS : positive := 4;
29 -- L1 DTLB entries per set
30 TLB_SET_SIZE : positive := 64;
31 -- L1 DTLB number of sets
32 TLB_NUM_WAYS : positive := 2;
33 -- L1 DTLB log_2(page_size)
34 TLB_LG_PGSZ : positive := 12
40 d_in : in Loadstore1ToDcacheType;
41 d_out : out DcacheToLoadstore1Type;
43 m_in : in MmuToDcacheType;
44 m_out : out DcacheToMmuType;
46 stall_out : out std_ulogic;
48 wishbone_out : out wishbone_master_out;
49 wishbone_in : in wishbone_slave_out
53 architecture rtl of dcache is
54 -- BRAM organisation: We never access more than wishbone_data_bits at
55 -- a time so to save resources we make the array only that wide, and
56 -- use consecutive indices for to make a cache "line"
58 -- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
59 constant ROW_SIZE : natural := wishbone_data_bits / 8;
60 -- ROW_PER_LINE is the number of row (wishbone transactions) in a line
61 constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
62 -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
64 constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
66 -- Bit fields counts in the address
68 -- REAL_ADDR_BITS is the number of real address bits that we store
69 constant REAL_ADDR_BITS : positive := 56;
70 -- ROW_BITS is the number of bits to select a row
71 constant ROW_BITS : natural := log2(BRAM_ROWS);
72 -- ROW_LINEBITS is the number of bits to select a row within a line
73 constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
74 -- LINE_OFF_BITS is the number of bits for the offset in a cache line
75 constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
76 -- ROW_OFF_BITS is the number of bits for the offset in a row
77 constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
78 -- INDEX_BITS is the number if bits to select a cache line
79 constant INDEX_BITS : natural := log2(NUM_LINES);
80 -- SET_SIZE_BITS is the log base 2 of the set size
81 constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
82 -- TAG_BITS is the number of bits of the tag part of the address
83 constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
84 -- WAY_BITS is the number of bits to select a way
85 constant WAY_BITS : natural := log2(NUM_WAYS);
87 -- Example of layout for 32 lines of 64 bytes:
89 -- .. tag |index| line |
91 -- .. | |---| | ROW_LINEBITS (3)
92 -- .. | |--- - --| LINE_OFF_BITS (6)
93 -- .. | |- --| ROW_OFF_BITS (3)
94 -- .. |----- ---| | ROW_BITS (8)
95 -- .. |-----| | INDEX_BITS (5)
96 -- .. --------| | TAG_BITS (45)
98 subtype row_t is integer range 0 to BRAM_ROWS-1;
99 subtype index_t is integer range 0 to NUM_LINES-1;
100 subtype way_t is integer range 0 to NUM_WAYS-1;
102 -- The cache data BRAM organized as described above for each way
103 subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
105 -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
106 -- not handle a clean (commented) definition of the cache tags as a 3d
107 -- memory. For now, work around it by putting all the tags
108 subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
109 -- type cache_tags_set_t is array(way_t) of cache_tag_t;
110 -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
111 constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
112 subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
113 type cache_tags_array_t is array(index_t) of cache_tags_set_t;
115 -- The cache valid bits
116 subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
117 type cache_valids_t is array(index_t) of cache_way_valids_t;
119 -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
120 signal cache_tags : cache_tags_array_t;
121 signal cache_valids : cache_valids_t;
123 attribute ram_style : string;
124 attribute ram_style of cache_tags : signal is "distributed";
127 constant TLB_SET_BITS : natural := log2(TLB_SET_SIZE);
128 constant TLB_WAY_BITS : natural := log2(TLB_NUM_WAYS);
129 constant TLB_EA_TAG_BITS : natural := 64 - (TLB_LG_PGSZ + TLB_SET_BITS);
130 constant TLB_TAG_WAY_BITS : natural := TLB_NUM_WAYS * TLB_EA_TAG_BITS;
131 constant TLB_PTE_BITS : natural := 64;
132 constant TLB_PTE_WAY_BITS : natural := TLB_NUM_WAYS * TLB_PTE_BITS;
134 subtype tlb_way_t is integer range 0 to TLB_NUM_WAYS - 1;
135 subtype tlb_index_t is integer range 0 to TLB_SET_SIZE - 1;
136 subtype tlb_way_valids_t is std_ulogic_vector(TLB_NUM_WAYS-1 downto 0);
137 type tlb_valids_t is array(tlb_index_t) of tlb_way_valids_t;
138 subtype tlb_tag_t is std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
139 subtype tlb_way_tags_t is std_ulogic_vector(TLB_TAG_WAY_BITS-1 downto 0);
140 type tlb_tags_t is array(tlb_index_t) of tlb_way_tags_t;
141 subtype tlb_pte_t is std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
142 subtype tlb_way_ptes_t is std_ulogic_vector(TLB_PTE_WAY_BITS-1 downto 0);
143 type tlb_ptes_t is array(tlb_index_t) of tlb_way_ptes_t;
144 type hit_way_set_t is array(tlb_way_t) of way_t;
146 signal dtlb_valids : tlb_valids_t;
147 signal dtlb_tags : tlb_tags_t;
148 signal dtlb_ptes : tlb_ptes_t;
149 attribute ram_style of dtlb_tags : signal is "distributed";
150 attribute ram_style of dtlb_ptes : signal is "distributed";
152 -- Record for storing permission, attribute, etc. bits from a PTE
153 type perm_attr_t is record
154 reference : std_ulogic;
155 changed : std_ulogic;
156 nocache : std_ulogic;
158 rd_perm : std_ulogic;
159 wr_perm : std_ulogic;
162 function extract_perm_attr(pte : std_ulogic_vector(TLB_PTE_BITS - 1 downto 0)) return perm_attr_t is
163 variable pa : perm_attr_t;
165 pa.reference := pte(8);
166 pa.changed := pte(7);
167 pa.nocache := pte(5);
169 pa.rd_perm := pte(2);
170 pa.wr_perm := pte(1);
174 constant real_mode_perm_attr : perm_attr_t := (nocache => '0', others => '1');
176 -- Type of operation on a "valid" input
177 type op_t is (OP_NONE,
178 OP_LOAD_HIT, -- Cache hit on load
179 OP_LOAD_MISS, -- Load missing cache
180 OP_LOAD_NC, -- Non-cachable load
181 OP_BAD, -- BAD: Cache hit on NC load/store
182 OP_TLB_ERR, -- TLB miss or protection/RC failure
183 OP_STORE_HIT, -- Store hitting cache
184 OP_STORE_MISS); -- Store missing cache
186 -- Cache state machine
187 type state_t is (IDLE, -- Normal load hit processing
188 RELOAD_WAIT_ACK, -- Cache reload wait ack
189 FINISH_LD_MISS, -- Extra cycle after load miss
190 STORE_WAIT_ACK, -- Store wait ack
191 NC_LOAD_WAIT_ACK);-- Non-cachable load wait ack
195 -- Dcache operations:
197 -- In order to make timing, we use the BRAMs with an output buffer,
198 -- which means that the BRAM output is delayed by an extra cycle.
200 -- Thus, the dcache has a 2-stage internal pipeline for cache hits
203 -- All other operations are handled via stalling in the first stage.
205 -- The second stage can thus complete a hit at the same time as the
206 -- first stage emits a stall for a complex op.
209 -- Stage 0 register, basically contains just the latched request
210 type reg_stage_0_t is record
211 req : Loadstore1ToDcacheType;
215 mmu_req : std_ulogic; -- indicates source of request
218 signal r0 : reg_stage_0_t;
219 signal r0_valid : std_ulogic;
221 -- First stage register, contains state for stage 1 of load hits
222 -- and for the state machine used by all other operations
224 type reg_stage_1_t is record
225 -- Latch the complete request from ls1
226 req : Loadstore1ToDcacheType;
227 mmu_req : std_ulogic;
231 hit_load_valid : std_ulogic;
233 -- Data buffer for "slow" read ops (load miss and NC loads).
234 slow_data : std_ulogic_vector(63 downto 0);
235 slow_valid : std_ulogic;
237 -- Signal to complete a failed stcx.
238 stcx_fail : std_ulogic;
240 -- Cache miss state (reload state machine)
242 wb : wishbone_master_out;
245 store_index : index_t;
247 -- Signals to complete with error
248 error_done : std_ulogic;
249 cache_paradox : std_ulogic;
251 -- completion signal for tlbie
252 tlbie_done : std_ulogic;
255 signal r1 : reg_stage_1_t;
257 -- Reservation information
259 type reservation_t is record
261 addr : std_ulogic_vector(63 downto LINE_OFF_BITS);
264 signal reservation : reservation_t;
266 -- Async signals on incoming request
267 signal req_index : index_t;
268 signal req_row : row_t;
269 signal req_hit_way : way_t;
270 signal req_tag : cache_tag_t;
271 signal req_op : op_t;
272 signal req_data : std_ulogic_vector(63 downto 0);
273 signal req_laddr : std_ulogic_vector(63 downto 0);
275 signal early_req_row : row_t;
277 signal cancel_store : std_ulogic;
278 signal set_rsrv : std_ulogic;
279 signal clear_rsrv : std_ulogic;
281 -- Cache RAM interface
282 type cache_ram_out_t is array(way_t) of cache_row_t;
283 signal cache_out : cache_ram_out_t;
285 -- PLRU output interface
286 type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
287 signal plru_victim : plru_out_t;
288 signal replace_way : way_t;
290 -- Wishbone read/write/cache write formatting signals
291 signal bus_sel : std_ulogic_vector(7 downto 0);
294 signal tlb_tag_way : tlb_way_tags_t;
295 signal tlb_pte_way : tlb_way_ptes_t;
296 signal tlb_valid_way : tlb_way_valids_t;
297 signal tlb_req_index : tlb_index_t;
298 signal tlb_hit : std_ulogic;
299 signal tlb_hit_way : tlb_way_t;
300 signal pte : tlb_pte_t;
301 signal ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
302 signal valid_ra : std_ulogic;
303 signal perm_attr : perm_attr_t;
304 signal rc_ok : std_ulogic;
305 signal perm_ok : std_ulogic;
307 -- TLB PLRU output interface
308 type tlb_plru_out_t is array(tlb_index_t) of std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
309 signal tlb_plru_victim : tlb_plru_out_t;
312 -- Helper functions to decode incoming requests
315 -- Return the cache line index (tag index) for an address
316 function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is
318 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)));
321 -- Return the cache row index (data memory) for an address
322 function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is
324 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)));
327 -- Returns whether this is the last row of a line
328 function is_last_row_addr(addr: wishbone_addr_type) return boolean is
329 constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
331 return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
334 -- Returns whether this is the last row of a line
335 function is_last_row(row: row_t) return boolean is
336 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
337 constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
339 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
340 return row_v(ROW_LINEBITS-1 downto 0) = ones;
343 -- Return the address of the next row in the current cache line
344 function next_row_addr(addr: wishbone_addr_type) return std_ulogic_vector is
345 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
346 variable result : wishbone_addr_type;
348 -- Is there no simpler way in VHDL to generate that 3 bits adder ?
349 row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
350 row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
352 result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
356 -- Return the next row in the current cache line. We use a dedicated
357 -- function in order to limit the size of the generated adder to be
358 -- only the bits within a cache line (3 bits with default settings)
360 function next_row(row: row_t) return row_t is
361 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
362 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
363 variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
365 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
366 row_idx := row_v(ROW_LINEBITS-1 downto 0);
367 row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
368 return to_integer(unsigned(row_v));
371 -- Get the tag value from the address
372 function get_tag(addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0)) return cache_tag_t is
374 return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
377 -- Read a tag from a tag memory row
378 function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
380 return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
383 -- Write a tag to tag memory row
384 procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
387 tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
390 -- Read a TLB tag from a TLB tag memory row
391 function read_tlb_tag(way: tlb_way_t; tags: tlb_way_tags_t) return tlb_tag_t is
392 variable j : integer;
394 j := way * TLB_EA_TAG_BITS;
395 return tags(j + TLB_EA_TAG_BITS - 1 downto j);
398 -- Write a TLB tag to a TLB tag memory row
399 procedure write_tlb_tag(way: tlb_way_t; tags: inout tlb_way_tags_t;
401 variable j : integer;
403 j := way * TLB_EA_TAG_BITS;
404 tags(j + TLB_EA_TAG_BITS - 1 downto j) := tag;
407 -- Read a PTE from a TLB PTE memory row
408 function read_tlb_pte(way: tlb_way_t; ptes: tlb_way_ptes_t) return tlb_pte_t is
409 variable j : integer;
411 j := way * TLB_PTE_BITS;
412 return ptes(j + TLB_PTE_BITS - 1 downto j);
415 procedure write_tlb_pte(way: tlb_way_t; ptes: inout tlb_way_ptes_t; newpte: tlb_pte_t) is
416 variable j : integer;
418 j := way * TLB_PTE_BITS;
419 ptes(j + TLB_PTE_BITS - 1 downto j) := newpte;
424 assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
425 assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
426 assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
427 assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
428 assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
429 report "geometry bits don't add up" severity FAILURE;
430 assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
431 report "geometry bits don't add up" severity FAILURE;
432 assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
433 report "geometry bits don't add up" severity FAILURE;
434 assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
435 report "geometry bits don't add up" severity FAILURE;
436 assert (64 = wishbone_data_bits)
437 report "Can't yet handle a wishbone width that isn't 64-bits" severity FAILURE;
439 -- Latch the request in r0.req as long as we're not stalling
440 stage_0 : process(clk)
442 if rising_edge(clk) then
445 elsif stall_out = '0' then
446 assert (d_in.valid and m_in.valid) = '0' report
447 "request collision loadstore vs MMU";
448 if m_in.valid = '1' then
450 r0.req.load <= not (m_in.tlbie or m_in.tlbld);
453 r0.req.reserve <= '0';
454 r0.req.virt_mode <= '0';
455 r0.req.priv_mode <= '1';
456 r0.req.addr <= m_in.addr;
457 r0.req.data <= m_in.pte;
458 r0.req.byte_sel <= (others => '1');
459 r0.tlbie <= m_in.tlbie;
460 r0.doall <= m_in.doall;
461 r0.tlbld <= m_in.tlbld;
474 -- we don't yet handle collisions between loadstore1 requests and MMU requests
477 -- Hold off the request in r0 when stalling,
478 -- and cancel it if we get an error in a previous request.
479 r0_valid <= r0.req.valid and not stall_out and not r1.error_done;
482 -- Operates in the second cycle on the request latched in r0.req.
483 -- TLB updates write the entry at the end of the second cycle.
484 tlb_read : process(clk)
485 variable index : tlb_index_t;
486 variable addrbits : std_ulogic_vector(TLB_SET_BITS - 1 downto 0);
488 if rising_edge(clk) then
489 if stall_out = '1' then
490 -- keep reading the same thing while stalled
491 index := tlb_req_index;
493 if m_in.valid = '1' then
494 addrbits := m_in.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1 downto TLB_LG_PGSZ);
496 addrbits := d_in.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1 downto TLB_LG_PGSZ);
498 index := to_integer(unsigned(addrbits));
500 tlb_valid_way <= dtlb_valids(index);
501 tlb_tag_way <= dtlb_tags(index);
502 tlb_pte_way <= dtlb_ptes(index);
506 -- Generate TLB PLRUs
507 maybe_tlb_plrus: if TLB_NUM_WAYS > 1 generate
509 tlb_plrus: for i in 0 to TLB_SET_SIZE - 1 generate
510 -- TLB PLRU interface
511 signal tlb_plru_acc : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
512 signal tlb_plru_acc_en : std_ulogic;
513 signal tlb_plru_out : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
515 tlb_plru : entity work.plru
523 acc_en => tlb_plru_acc_en,
527 process(tlb_req_index, tlb_hit, tlb_hit_way, tlb_plru_out)
530 if tlb_hit = '1' and tlb_req_index = i then
531 tlb_plru_acc_en <= '1';
533 tlb_plru_acc_en <= '0';
535 tlb_plru_acc <= std_ulogic_vector(to_unsigned(tlb_hit_way, TLB_WAY_BITS));
536 tlb_plru_victim(i) <= tlb_plru_out;
541 tlb_search : process(all)
542 variable hitway : tlb_way_t;
543 variable hit : std_ulogic;
544 variable eatag : tlb_tag_t;
546 tlb_req_index <= to_integer(unsigned(r0.req.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1
547 downto TLB_LG_PGSZ)));
550 eatag := r0.req.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
551 for i in tlb_way_t loop
552 if tlb_valid_way(i) = '1' and
553 read_tlb_tag(i, tlb_tag_way) = eatag then
558 tlb_hit <= hit and r0_valid;
559 tlb_hit_way <= hitway;
560 if tlb_hit = '1' then
561 pte <= read_tlb_pte(hitway, tlb_pte_way);
563 pte <= (others => '0');
565 valid_ra <= tlb_hit or not r0.req.virt_mode;
566 if r0.req.virt_mode = '1' then
567 ra <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
568 r0.req.addr(TLB_LG_PGSZ - 1 downto 0);
569 perm_attr <= extract_perm_attr(pte);
571 ra <= r0.req.addr(REAL_ADDR_BITS - 1 downto 0);
572 perm_attr <= real_mode_perm_attr;
576 tlb_update : process(clk)
577 variable tlbie : std_ulogic;
578 variable tlbwe : std_ulogic;
579 variable repl_way : tlb_way_t;
580 variable eatag : tlb_tag_t;
581 variable tagset : tlb_way_tags_t;
582 variable pteset : tlb_way_ptes_t;
584 if rising_edge(clk) then
585 tlbie := r0_valid and r0.tlbie;
586 tlbwe := r0_valid and r0.tlbld;
587 if rst = '1' or (tlbie = '1' and r0.doall = '1') then
588 -- clear all valid bits at once
589 for i in tlb_index_t loop
590 dtlb_valids(i) <= (others => '0');
592 elsif tlbie = '1' then
593 if tlb_hit = '1' then
594 dtlb_valids(tlb_req_index)(tlb_hit_way) <= '0';
596 elsif tlbwe = '1' then
597 if tlb_hit = '1' then
598 repl_way := tlb_hit_way;
600 repl_way := to_integer(unsigned(tlb_plru_victim(tlb_req_index)));
602 eatag := r0.req.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
603 tagset := tlb_tag_way;
604 write_tlb_tag(repl_way, tagset, eatag);
605 dtlb_tags(tlb_req_index) <= tagset;
606 pteset := tlb_pte_way;
607 write_tlb_pte(repl_way, pteset, r0.req.data);
608 dtlb_ptes(tlb_req_index) <= pteset;
609 dtlb_valids(tlb_req_index)(repl_way) <= '1';
615 maybe_plrus: if NUM_WAYS > 1 generate
617 plrus: for i in 0 to NUM_LINES-1 generate
619 signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
620 signal plru_acc_en : std_ulogic;
621 signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
624 plru : entity work.plru
632 acc_en => plru_acc_en,
636 process(req_index, req_op, req_hit_way, plru_out)
639 if (req_op = OP_LOAD_HIT or
640 req_op = OP_STORE_HIT) and req_index = i then
645 plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
646 plru_victim(i) <= plru_out;
651 -- Cache request parsing and hit detection
652 dcache_request : process(all)
653 variable is_hit : std_ulogic;
654 variable hit_way : way_t;
656 variable opsel : std_ulogic_vector(2 downto 0);
657 variable go : std_ulogic;
658 variable nc : std_ulogic;
659 variable s_hit : std_ulogic;
660 variable s_tag : cache_tag_t;
661 variable s_pte : tlb_pte_t;
662 variable s_ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
663 variable hit_set : std_ulogic_vector(TLB_NUM_WAYS - 1 downto 0);
664 variable hit_way_set : hit_way_set_t;
666 -- Extract line, row and tag from request
667 req_index <= get_index(r0.req.addr);
668 req_row <= get_row(r0.req.addr);
669 req_tag <= get_tag(ra);
671 -- Only do anything if not being stalled by stage 1
672 go := r0_valid and not (r0.tlbie or r0.tlbld);
674 -- Calculate address of beginning of cache line, will be
675 -- used for cache miss processing if needed
677 req_laddr <= (63 downto REAL_ADDR_BITS => '0') &
678 ra(REAL_ADDR_BITS - 1 downto LINE_OFF_BITS) &
679 (LINE_OFF_BITS-1 downto 0 => '0');
681 -- Test if pending request is a hit on any way
682 -- In order to make timing in virtual mode, when we are using the TLB,
683 -- we compare each way with each of the real addresses from each way of
684 -- the TLB, and then decide later which match to use.
687 if r0.req.virt_mode = '1' then
688 for j in tlb_way_t loop
691 s_pte := read_tlb_pte(j, tlb_pte_way);
692 s_ra := s_pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
693 r0.req.addr(TLB_LG_PGSZ - 1 downto 0);
694 s_tag := get_tag(s_ra);
696 if go = '1' and cache_valids(req_index)(i) = '1' and
697 read_tag(i, cache_tags(req_index)) = s_tag and
698 tlb_valid_way(j) = '1' then
705 if tlb_hit = '1' then
706 is_hit := hit_set(tlb_hit_way);
707 hit_way := hit_way_set(tlb_hit_way);
710 s_tag := get_tag(r0.req.addr(REAL_ADDR_BITS - 1 downto 0));
712 if go = '1' and cache_valids(req_index)(i) = '1' and
713 read_tag(i, cache_tags(req_index)) = s_tag then
720 -- The way that matched on a hit
721 req_hit_way <= hit_way;
723 -- The way to replace on a miss
724 replace_way <= to_integer(unsigned(plru_victim(req_index)));
726 -- work out whether we have permission for this access
727 -- NB we don't yet implement AMR, thus no KUAP
728 rc_ok <= perm_attr.reference and (r0.req.load or perm_attr.changed);
729 perm_ok <= (r0.req.priv_mode or not perm_attr.priv) and
730 (perm_attr.wr_perm or (r0.req.load and perm_attr.rd_perm));
732 -- Combine the request and cache hit status to decide what
733 -- operation needs to be done
735 nc := r0.req.nc or perm_attr.nocache;
738 if valid_ra = '1' and rc_ok = '1' and perm_ok = '1' then
739 opsel := r0.req.load & nc & is_hit;
741 when "101" => op := OP_LOAD_HIT;
742 when "100" => op := OP_LOAD_MISS;
743 when "110" => op := OP_LOAD_NC;
744 when "001" => op := OP_STORE_HIT;
745 when "000" => op := OP_STORE_MISS;
746 when "010" => op := OP_STORE_MISS;
747 when "011" => op := OP_BAD;
748 when "111" => op := OP_BAD;
749 when others => op := OP_NONE;
757 -- Version of the row number that is valid one cycle earlier
758 -- in the cases where we need to read the cache data BRAM.
759 -- If we're stalling then we need to keep reading the last
761 if stall_out = '0' then
762 if m_in.valid = '1' then
763 early_req_row <= get_row(m_in.addr);
765 early_req_row <= get_row(d_in.addr);
768 early_req_row <= req_row;
772 -- Wire up wishbone request latch out of stage 1
773 wishbone_out <= r1.wb;
775 -- Generate stalls from stage 1 state machine
776 stall_out <= '1' when r1.state /= IDLE else '0';
778 -- Handle load-with-reservation and store-conditional instructions
779 reservation_comb: process(all)
784 if r0_valid = '1' and r0.req.reserve = '1' then
785 -- XXX generate alignment interrupt if address is not aligned
786 -- XXX or if r0.req.nc = '1'
787 if r0.req.load = '1' then
788 -- load with reservation
793 if reservation.valid = '0' or
794 r0.req.addr(63 downto LINE_OFF_BITS) /= reservation.addr then
801 reservation_reg: process(clk)
803 if rising_edge(clk) then
804 if rst = '1' or clear_rsrv = '1' then
805 reservation.valid <= '0';
806 elsif set_rsrv = '1' then
807 reservation.valid <= '1';
808 reservation.addr <= r0.req.addr(63 downto LINE_OFF_BITS);
813 -- Return data for loads & completion control logic
815 writeback_control: process(all)
818 -- The mux on d_out.data defaults to the normal load hit case.
820 d_out.data <= cache_out(r1.hit_way);
821 d_out.store_done <= '0';
823 d_out.cache_paradox <= '0';
826 m_out.done <= r1.tlbie_done;
828 m_out.data <= cache_out(r1.hit_way);
830 -- We have a valid load or store hit or we just completed a slow
831 -- op such as a load miss, a NC load or a store
833 -- Note: the load hit is delayed by one cycle. However it can still
834 -- not collide with r.slow_valid (well unless I miscalculated) because
835 -- slow_valid can only be set on a subsequent request and not on its
836 -- first cycle (the state machine must have advanced), which makes
837 -- slow_valid at least 2 cycles from the previous hit_load_valid.
840 -- Sanity: Only one of these must be set in any given cycle
841 assert (r1.slow_valid and r1.stcx_fail) /= '1' report
842 "unexpected slow_valid collision with stcx_fail"
844 assert ((r1.slow_valid or r1.stcx_fail) and r1.hit_load_valid) /= '1' report
845 "unexpected hit_load_delayed collision with slow_valid"
848 if r1.mmu_req = '0' then
849 -- Request came from loadstore1...
850 -- Load hit case is the standard path
851 if r1.hit_load_valid = '1' then
852 report "completing load hit";
856 -- error cases complete without stalling
857 if r1.error_done = '1' then
858 report "completing ld/st with error";
860 d_out.cache_paradox <= r1.cache_paradox;
864 -- Slow ops (load miss, NC, stores)
865 if r1.slow_valid = '1' then
866 -- If it's a load, enable register writeback and switch
870 -- Read data comes from the slow data latch
871 d_out.data <= r1.slow_data;
873 d_out.store_done <= '1';
875 report "completing store or load miss";
879 if r1.stcx_fail = '1' then
880 d_out.store_done <= '0';
885 -- Request came from MMU
886 if r1.hit_load_valid = '1' then
887 report "completing load hit to MMU, data=" & to_hstring(m_out.data);
891 -- error cases complete without stalling
892 if r1.error_done = '1' then
893 report "completing MMU ld with error";
898 -- Slow ops (i.e. load miss)
899 if r1.slow_valid = '1' then
900 -- Read data comes from the slow data latch
901 m_out.data <= r1.slow_data;
902 report "completing MMU load miss, data=" & to_hstring(m_out.data);
910 -- Generate a cache RAM for each way. This handles the normal
911 -- reads, writes from reloads and the special store-hit update
914 -- Note: the BRAMs have an extra read buffer, meaning the output
915 -- is pipelined an extra cycle. This differs from the
916 -- icache. The writeback logic needs to take that into
917 -- account by using 1-cycle delayed signals for load hits.
919 rams: for i in 0 to NUM_WAYS-1 generate
920 signal do_read : std_ulogic;
921 signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
922 signal do_write : std_ulogic;
923 signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
924 signal wr_data : std_ulogic_vector(wishbone_data_bits-1 downto 0);
925 signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
926 signal dout : cache_row_t;
928 way: entity work.cache_ram
930 ROW_BITS => ROW_BITS,
931 WIDTH => wishbone_data_bits,
945 variable tmp_adr : std_ulogic_vector(63 downto 0);
946 variable reloading : boolean;
950 rd_addr <= std_ulogic_vector(to_unsigned(early_req_row, ROW_BITS));
951 cache_out(i) <= dout;
955 -- Defaults to wishbone read responses (cache refill),
957 -- For timing, the mux on wr_data/sel/addr is not dependent on anything
958 -- other than the current state. Only the do_write signal is.
960 if r1.state = IDLE then
961 -- In IDLE state, the only write path is the store-hit update case
962 wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
963 wr_data <= r0.req.data;
964 wr_sel <= r0.req.byte_sel;
966 -- Otherwise, we might be doing a reload or a DCBZ
967 if r1.req.dcbz = '1' then
968 wr_data <= (others => '0');
970 wr_data <= wishbone_in.dat;
972 wr_sel <= (others => '1');
973 wr_addr <= std_ulogic_vector(to_unsigned(r1.store_row, ROW_BITS));
976 -- The two actual write cases here
978 reloading := r1.state = RELOAD_WAIT_ACK;
979 if reloading and wishbone_in.ack = '1' and r1.store_way = i then
982 if req_op = OP_STORE_HIT and req_hit_way = i and cancel_store = '0' and
983 r0.req.dcbz = '0' then
984 assert not reloading report "Store hit while in state:" &
985 state_t'image(r1.state)
993 -- Cache hit synchronous machine for the easy case. This handles load hits.
994 -- It also handles error cases (TLB miss, cache paradox)
996 dcache_fast_hit : process(clk)
998 if rising_edge(clk) then
999 -- If we have a request incoming, we have to latch it as r0.req.valid
1000 -- is only set for a single cycle. It's up to the control logic to
1001 -- ensure we don't override an uncompleted request (for now we are
1002 -- single issue on load/stores so we are fine, later, we can generate
1003 -- a stall output if necessary).
1005 if req_op /= OP_NONE and stall_out = '0' then
1007 r1.mmu_req <= r0.mmu_req;
1008 report "op:" & op_t'image(req_op) &
1009 " addr:" & to_hstring(r0.req.addr) &
1010 " nc:" & std_ulogic'image(r0.req.nc) &
1011 " idx:" & integer'image(req_index) &
1012 " tag:" & to_hstring(req_tag) &
1013 " way: " & integer'image(req_hit_way);
1016 -- Fast path for load/store hits. Set signals for the writeback controls.
1017 if req_op = OP_LOAD_HIT then
1018 r1.hit_way <= req_hit_way;
1019 r1.hit_load_valid <= '1';
1021 r1.hit_load_valid <= '0';
1024 if req_op = OP_TLB_ERR then
1025 report "Signalling ld/st error valid_ra=" & std_ulogic'image(valid_ra) &
1026 " rc_ok=" & std_ulogic'image(rc_ok) & " perm_ok=" & std_ulogic'image(perm_ok);
1027 r1.error_done <= '1';
1028 r1.cache_paradox <= '0';
1029 elsif req_op = OP_BAD then
1030 report "Signalling cache paradox";
1031 r1.error_done <= '1';
1032 r1.cache_paradox <= '1';
1034 r1.error_done <= '0';
1035 r1.cache_paradox <= '0';
1038 -- complete tlbies and TLB loads in the third cycle
1039 r1.tlbie_done <= r0_valid and (r0.tlbie or r0.tlbld);
1044 -- Every other case is handled by this state machine:
1046 -- * Cache load miss/reload (in conjunction with "rams")
1047 -- * Load hits for non-cachable forms
1048 -- * Stores (the collision case is handled in "rams")
1050 -- All wishbone requests generation is done here. This machine
1051 -- operates at stage 1.
1053 dcache_slow : process(clk)
1054 variable tagset : cache_tags_set_t;
1055 variable stbs_done : boolean;
1057 if rising_edge(clk) then
1058 -- On reset, clear all valid bits to force misses
1060 for i in index_t loop
1061 cache_valids(i) <= (others => '0');
1064 r1.slow_valid <= '0';
1068 -- Not useful normally but helps avoiding tons of sim warnings
1069 r1.wb.adr <= (others => '0');
1071 -- One cycle pulses reset
1072 r1.slow_valid <= '0';
1073 r1.stcx_fail <= '0';
1075 -- Main state machine
1080 -- stay in IDLE state
1082 when OP_LOAD_MISS =>
1083 -- Normal load cache miss, start the reload machine
1085 report "cache miss addr:" & to_hstring(r0.req.addr) &
1086 " idx:" & integer'image(req_index) &
1087 " way:" & integer'image(replace_way) &
1088 " tag:" & to_hstring(req_tag);
1090 -- Force misses on that way while reloading that line
1091 cache_valids(req_index)(replace_way) <= '0';
1093 -- Store new tag in selected way
1094 for i in 0 to NUM_WAYS-1 loop
1095 if i = replace_way then
1096 tagset := cache_tags(req_index);
1097 write_tag(i, tagset, req_tag);
1098 cache_tags(req_index) <= tagset;
1102 -- Keep track of our index and way for subsequent stores.
1103 r1.store_index <= req_index;
1104 r1.store_way <= replace_way;
1105 r1.store_row <= get_row(req_laddr);
1107 -- Prep for first wishbone read. We calculate the address of
1108 -- the start of the cache line and start the WB cycle
1110 r1.wb.adr <= req_laddr(r1.wb.adr'left downto 0);
1111 r1.wb.sel <= (others => '1');
1116 -- Track that we had one request sent
1117 r1.state <= RELOAD_WAIT_ACK;
1120 r1.wb.sel <= r0.req.byte_sel;
1121 r1.wb.adr <= ra(r1.wb.adr'left downto 3) & "000";
1125 r1.state <= NC_LOAD_WAIT_ACK;
1127 when OP_STORE_HIT | OP_STORE_MISS =>
1128 if r0.req.dcbz = '0' then
1129 r1.wb.sel <= r0.req.byte_sel;
1130 r1.wb.adr <= ra(r1.wb.adr'left downto 3) & "000";
1131 r1.wb.dat <= r0.req.data;
1132 if cancel_store = '0' then
1136 r1.state <= STORE_WAIT_ACK;
1138 r1.stcx_fail <= '1';
1142 -- dcbz is handled much like a load miss except
1143 -- that we are writing to memory instead of reading
1144 r1.store_index <= req_index;
1145 r1.store_row <= get_row(req_laddr);
1147 if req_op = OP_STORE_HIT then
1148 r1.store_way <= req_hit_way;
1150 r1.store_way <= replace_way;
1152 -- Force misses on the victim way while zeroing
1153 cache_valids(req_index)(replace_way) <= '0';
1155 -- Store new tag in selected way
1156 for i in 0 to NUM_WAYS-1 loop
1157 if i = replace_way then
1158 tagset := cache_tags(req_index);
1159 write_tag(i, tagset, req_tag);
1160 cache_tags(req_index) <= tagset;
1165 -- Set up for wishbone writes
1166 r1.wb.adr <= req_laddr(r1.wb.adr'left downto 0);
1167 r1.wb.sel <= (others => '1');
1169 r1.wb.dat <= (others => '0');
1173 -- Handle the rest like a load miss
1174 r1.state <= RELOAD_WAIT_ACK;
1177 -- OP_NONE and OP_BAD do nothing
1178 -- OP_BAD was handled above already
1184 when RELOAD_WAIT_ACK =>
1185 -- Requests are all sent if stb is 0
1186 stbs_done := r1.wb.stb = '0';
1188 -- If we are still sending requests, was one accepted ?
1189 if wishbone_in.stall = '0' and not stbs_done then
1190 -- That was the last word ? We are done sending. Clear
1191 -- stb and set stbs_done so we can handle an eventual last
1192 -- ack on the same cycle.
1194 if is_last_row_addr(r1.wb.adr) then
1199 -- Calculate the next row address
1200 r1.wb.adr <= next_row_addr(r1.wb.adr);
1203 -- Incoming acks processing
1204 if wishbone_in.ack = '1' then
1205 -- Is this the data we were looking for ? Latch it so
1206 -- we can respond later. We don't currently complete the
1207 -- pending miss request immediately, we wait for the
1208 -- whole line to be loaded. The reason is that if we
1209 -- did, we would potentially get new requests in while
1210 -- not idle, which we don't currently know how to deal
1213 if r1.store_row = get_row(r1.req.addr) and r1.req.dcbz = '0' then
1214 r1.slow_data <= wishbone_in.dat;
1217 -- Check for completion
1218 if stbs_done and is_last_row(r1.store_row) then
1219 -- Complete wishbone cycle
1222 -- Cache line is now valid
1223 cache_valids(r1.store_index)(r1.store_way) <= '1';
1225 -- Don't complete and go idle until next cycle, in
1226 -- case the next request is for the last dword of
1227 -- the cache line we just loaded.
1228 r1.state <= FINISH_LD_MISS;
1231 -- Increment store row counter
1232 r1.store_row <= next_row(r1.store_row);
1235 when FINISH_LD_MISS =>
1236 -- Write back the load data that we got
1237 r1.slow_valid <= '1';
1239 report "completing miss !";
1241 when STORE_WAIT_ACK | NC_LOAD_WAIT_ACK =>
1242 -- Clear stb when slave accepted request
1243 if wishbone_in.stall = '0' then
1247 -- Got ack ? complete.
1248 if wishbone_in.ack = '1' then
1249 if r1.state = NC_LOAD_WAIT_ACK then
1250 r1.slow_data <= wishbone_in.dat;
1253 r1.slow_valid <= '1';