dcache_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.common.all;
   6 use work.wishbone_types.all;
   7
   8 entity dcache_tb is
   9 end dcache_tb;
  10
  11 architecture behave of dcache_tb is
  12     signal clk          : std_ulogic;
  13     signal rst          : std_ulogic;
  14
  15     signal d_in         : Loadstore1ToDcacheType;
  16     signal d_out        : DcacheToWritebackType;
  17
  18     signal wb_bram_in   : wishbone_master_out;
  19     signal wb_bram_out  : wishbone_slave_out;
  20
  21     constant clk_period : time := 10 ns;
  22 begin
  23     dcache0: entity work.dcache
  24         generic map(
  25             LINE_SIZE => 64,
  26             NUM_LINES => 4
  27             )
  28         port map(
  29             clk => clk,
  30             rst => rst,
  31             d_in => d_in,
  32             d_out => d_out,
  33             wishbone_out => wb_bram_in,
  34             wishbone_in => wb_bram_out
  35             );
  36
  37     -- BRAM Memory slave
  38     bram0: entity work.mw_soc_memory
  39         generic map(
  40             MEMORY_SIZE   => 128,
  41             RAM_INIT_FILE => "icache_test.bin"
  42             )
  43         port map(
  44             clk => clk,
  45             rst => rst,
  46             wishbone_in => wb_bram_in,
  47             wishbone_out => wb_bram_out
  48             );
  49
  50     clk_process: process
  51     begin
  52         clk <= '0';
  53         wait for clk_period/2;
  54         clk <= '1';
  55         wait for clk_period/2;
  56     end process;
  57
  58     rst_process: process
  59     begin
  60         rst <= '1';
  61         wait for 2*clk_period;
  62         rst <= '0';
  63         wait;
  64     end process;
  65
  66     stim: process
  67     begin
  68         -- Clear stuff
  69         d_in.valid <= '0';
  70         d_in.load <= '0';
  71         d_in.nc <= '0';
  72         d_in.addr <= (others => '0');
  73         d_in.data <= (others => '0');
  74         d_in.write_reg <= (others => '0');
  75         d_in.length <= (others => '0');
  76         d_in.byte_reverse <= '0';
  77         d_in.sign_extend <= '0';
  78         d_in.update <= '0';
  79         d_in.update_reg <= (others => '0');
  80
  81         wait for 4*clk_period;
  82         wait until rising_edge(clk);
  83
  84         -- Cacheable read of address 4
  85         d_in.load <= '1';
  86         d_in.nc <= '0';
  87         d_in.addr <= x"0000000000000004";
  88         d_in.valid <= '1';
  89         wait until rising_edge(clk);
  90         d_in.valid <= '0';
  91
  92         wait until rising_edge(clk) and d_out.write_enable = '1';
  93         assert d_out.valid = '1';
  94         assert d_out.write_data = x"0000000100000000"
  95             report "data @" & to_hstring(d_in.addr) &
  96             "=" & to_hstring(d_out.write_data) &
  97             " expected 0000000100000000"
  98             severity failure;
  99 --      wait for clk_period;
 100
 101         -- Cacheable read of address 30
 102         d_in.load <= '1';
 103         d_in.nc <= '0';
 104         d_in.addr <= x"0000000000000030";
 105         d_in.valid <= '1';
 106         wait until rising_edge(clk);
 107         d_in.valid <= '0';
 108
 109         wait until rising_edge(clk) and d_out.write_enable = '1';
 110         assert d_out.valid = '1';
 111         assert d_out.write_data = x"0000000D0000000C"
 112             report "data @" & to_hstring(d_in.addr) &
 113             "=" & to_hstring(d_out.write_data) &
 114             " expected 0000000D0000000C"
 115             severity failure;
 116
 117         -- Non-cacheable read of address 100
 118         d_in.load <= '1';
 119         d_in.nc <= '1';
 120         d_in.addr <= x"0000000000000100";
 121         d_in.valid <= '1';
 122         wait until rising_edge(clk);
 123         d_in.valid <= '0';
 124
 125         wait until rising_edge(clk) and d_out.write_enable = '1';
 126         assert d_out.valid = '1';
 127         assert d_out.write_data = x"0000004100000040"
 128             report "data @" & to_hstring(d_in.addr) &
 129             "=" & to_hstring(d_out.write_data) &
 130             " expected 0000004100000040"
 131             severity failure;
 132
 133         wait for clk_period*4;
 134
 135         assert false report "end of test" severity failure;
 136         wait;
 137
 138     end process;
 139 end;