decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12     generic (
  13         EX1_BYPASS : boolean := true;
  14         -- Non-zero to enable log data collection
  15         LOG_LENGTH : natural := 0
  16         );
  17     port (
  18         clk   : in std_ulogic;
  19         rst   : in std_ulogic;
  20
  21         complete_in : in std_ulogic;
  22         busy_in   : in std_ulogic;
  23         stall_out : out std_ulogic;
  24
  25         stopped_out : out std_ulogic;
  26
  27         flush_in: in std_ulogic;
  28
  29         d_in  : in Decode1ToDecode2Type;
  30
  31         e_out : out Decode2ToExecute1Type;
  32
  33         r_in  : in RegisterFileToDecode2Type;
  34         r_out : out Decode2ToRegisterFileType;
  35
  36         c_in  : in CrFileToDecode2Type;
  37         c_out : out Decode2ToCrFileType;
  38
  39         log_out : out std_ulogic_vector(9 downto 0)
  40         );
  41 end entity decode2;
  42
  43 architecture behaviour of decode2 is
  44     type reg_type is record
  45         e : Decode2ToExecute1Type;
  46     end record;
  47
  48     signal r, rin : reg_type;
  49
  50     signal deferred : std_ulogic;
  51
  52     type decode_input_reg_t is record
  53         reg_valid : std_ulogic;
  54         reg       : gspr_index_t;
  55         data      : std_ulogic_vector(63 downto 0);
  56     end record;
  57
  58     type decode_output_reg_t is record
  59         reg_valid : std_ulogic;
  60         reg       : gspr_index_t;
  61     end record;
  62
  63     function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  64                                  reg_data : std_ulogic_vector(63 downto 0);
  65                                  ispr : gspr_index_t;
  66                                  instr_addr : std_ulogic_vector(63 downto 0))
  67         return decode_input_reg_t is
  68     begin
  69         if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  70             return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  71         elsif t = SPR then
  72             -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  73             -- If it's all 0, we don't treat it as a dependency as slow SPRs
  74             -- operations are single issue.
  75             --
  76             assert is_fast_spr(ispr) =  '1' or ispr = "000000"
  77                 report "Decode A says SPR but ISPR is invalid:" &
  78                 to_hstring(ispr) severity failure;
  79             return (is_fast_spr(ispr), ispr, reg_data);
  80         elsif t = CIA then
  81             return ('0', (others => '0'), instr_addr);
  82         else
  83             return ('0', (others => '0'), (others => '0'));
  84         end if;
  85     end;
  86
  87     function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  88                                  reg_data : std_ulogic_vector(63 downto 0);
  89                                  ispr : gspr_index_t) return decode_input_reg_t is
  90         variable ret : decode_input_reg_t;
  91     begin
  92         case t is
  93             when RB =>
  94                 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
  95             when CONST_UI =>
  96                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  97             when CONST_SI =>
  98                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  99             when CONST_SI_HI =>
 100                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
 101             when CONST_UI_HI =>
 102                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
 103             when CONST_LI =>
 104                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
 105             when CONST_BD =>
 106                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 107             when CONST_DS =>
 108                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 109             when CONST_DXHI4 =>
 110                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
 111             when CONST_M1 =>
 112                 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 113             when CONST_SH =>
 114                 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 115             when CONST_SH32 =>
 116                 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 117             when SPR =>
 118                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 119                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 120                 -- operations are single issue.
 121                 assert is_fast_spr(ispr) = '1' or ispr = "000000"
 122                     report "Decode B says SPR but ISPR is invalid:" &
 123                     to_hstring(ispr) severity failure;
 124                 ret := (is_fast_spr(ispr), ispr, reg_data);
 125             when NONE =>
 126                 ret := ('0', (others => '0'), (others => '0'));
 127         end case;
 128
 129         return ret;
 130     end;
 131
 132     function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 133                                  reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 134     begin
 135         case t is
 136             when RS =>
 137                 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 138             when RCR =>
 139                 return ('1', gpr_to_gspr(insn_rcreg(insn_in)), reg_data);
 140             when NONE =>
 141                 return ('0', (others => '0'), (others => '0'));
 142         end case;
 143     end;
 144
 145     function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 146                                 ispr : gspr_index_t) return decode_output_reg_t is
 147     begin
 148         case t is
 149             when RT =>
 150                 return ('1', gpr_to_gspr(insn_rt(insn_in)));
 151             when RA =>
 152                 return ('1', gpr_to_gspr(insn_ra(insn_in)));
 153             when SPR =>
 154                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 155                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 156                 -- operations are single issue.
 157                 assert is_fast_spr(ispr) = '1' or ispr = "000000"
 158                     report "Decode B says SPR but ISPR is invalid:" &
 159                     to_hstring(ispr) severity failure;
 160                 return (is_fast_spr(ispr), ispr);
 161             when NONE =>
 162                 return ('0', "000000");
 163         end case;
 164     end;
 165
 166     function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 167     begin
 168         case t is
 169             when RC =>
 170                 return insn_rc(insn_in);
 171             when ONE =>
 172                 return '1';
 173             when NONE =>
 174                 return '0';
 175         end case;
 176     end;
 177
 178     -- For now, use "rc" in the decode table to decide whether oe exists.
 179     -- This is not entirely correct architecturally: For mulhd and
 180     -- mulhdu, the OE field is reserved. It remains to be seen what an
 181     -- actual POWER9 does if we set it on those instructions, for now we
 182     -- test that further down when assigning to the multiplier oe input.
 183     --
 184     function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 185     begin
 186         case t is
 187             when RC =>
 188                 return insn_oe(insn_in);
 189             when OTHERS =>
 190                 return '0';
 191         end case;
 192     end;
 193
 194     -- issue control signals
 195     signal control_valid_in : std_ulogic;
 196     signal control_valid_out : std_ulogic;
 197     signal control_sgl_pipe : std_logic;
 198
 199     signal gpr_write_valid : std_ulogic;
 200     signal gpr_write : gspr_index_t;
 201     signal gpr_bypassable  : std_ulogic;
 202
 203     signal update_gpr_write_valid : std_ulogic;
 204     signal update_gpr_write_reg : gspr_index_t;
 205
 206     signal gpr_a_read_valid : std_ulogic;
 207     signal gpr_a_read :gspr_index_t;
 208     signal gpr_a_bypass : std_ulogic;
 209
 210     signal gpr_b_read_valid : std_ulogic;
 211     signal gpr_b_read : gspr_index_t;
 212     signal gpr_b_bypass : std_ulogic;
 213
 214     signal gpr_c_read_valid : std_ulogic;
 215     signal gpr_c_read : gpr_index_t;
 216     signal gpr_c_bypass : std_ulogic;
 217
 218     signal cr_write_valid  : std_ulogic;
 219     signal cr_bypass       : std_ulogic;
 220     signal cr_bypass_avail : std_ulogic;
 221
 222 begin
 223     control_0: entity work.control
 224         generic map (
 225             PIPELINE_DEPTH => 1
 226             )
 227         port map (
 228             clk         => clk,
 229             rst         => rst,
 230
 231             complete_in => complete_in,
 232             valid_in    => control_valid_in,
 233             busy_in     => busy_in,
 234             deferred    => deferred,
 235             flush_in    => flush_in,
 236             sgl_pipe_in => control_sgl_pipe,
 237             stop_mark_in => d_in.stop_mark,
 238
 239             gpr_write_valid_in => gpr_write_valid,
 240             gpr_write_in       => gpr_write,
 241             gpr_bypassable     => gpr_bypassable,
 242
 243             update_gpr_write_valid => update_gpr_write_valid,
 244             update_gpr_write_reg => update_gpr_write_reg,
 245
 246             gpr_a_read_valid_in  => gpr_a_read_valid,
 247             gpr_a_read_in        => gpr_a_read,
 248
 249             gpr_b_read_valid_in  => gpr_b_read_valid,
 250             gpr_b_read_in        => gpr_b_read,
 251
 252             gpr_c_read_valid_in  => gpr_c_read_valid,
 253             gpr_c_read_in        => gpr_c_read,
 254
 255             cr_read_in           => d_in.decode.input_cr,
 256             cr_write_in          => cr_write_valid,
 257             cr_bypass            => cr_bypass,
 258             cr_bypassable        => cr_bypass_avail,
 259
 260             valid_out   => control_valid_out,
 261             stall_out   => stall_out,
 262             stopped_out => stopped_out,
 263
 264             gpr_bypass_a => gpr_a_bypass,
 265             gpr_bypass_b => gpr_b_bypass,
 266             gpr_bypass_c => gpr_c_bypass
 267             );
 268
 269     deferred <= r.e.valid and busy_in;
 270
 271     decode2_0: process(clk)
 272     begin
 273         if rising_edge(clk) then
 274             if rst = '1' or flush_in = '1' or deferred = '0' then
 275                 if rin.e.valid = '1' then
 276                     report "execute " & to_hstring(rin.e.nia);
 277                 end if;
 278                 r <= rin;
 279             end if;
 280         end if;
 281     end process;
 282
 283     r_out.read1_reg <= d_in.ispr1 when d_in.decode.input_reg_a = SPR
 284                        else gpr_to_gspr(insn_ra(d_in.insn));
 285     r_out.read2_reg <= d_in.ispr2 when d_in.decode.input_reg_b = SPR
 286                        else gpr_to_gspr(insn_rb(d_in.insn));
 287     r_out.read3_reg <= insn_rcreg(d_in.insn) when d_in.decode.input_reg_c = RCR
 288                        else insn_rs(d_in.insn);
 289
 290     c_out.read <= d_in.decode.input_cr;
 291
 292     decode2_1: process(all)
 293         variable v : reg_type;
 294         variable mul_a : std_ulogic_vector(63 downto 0);
 295         variable mul_b : std_ulogic_vector(63 downto 0);
 296         variable decoded_reg_a : decode_input_reg_t;
 297         variable decoded_reg_b : decode_input_reg_t;
 298         variable decoded_reg_c : decode_input_reg_t;
 299         variable decoded_reg_o : decode_output_reg_t;
 300         variable length : std_ulogic_vector(3 downto 0);
 301     begin
 302         v := r;
 303
 304         v.e := Decode2ToExecute1Init;
 305
 306         mul_a := (others => '0');
 307         mul_b := (others => '0');
 308
 309         --v.e.input_cr := d_in.decode.input_cr;
 310         --v.e.output_cr := d_in.decode.output_cr;
 311
 312         decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
 313                                              d_in.nia);
 314         decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 315         decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 316         decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
 317
 318         r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
 319         r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
 320         r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
 321
 322         case d_in.decode.length is
 323             when is1B =>
 324                 length := "0001";
 325             when is2B =>
 326                 length := "0010";
 327             when is4B =>
 328                 length := "0100";
 329             when is8B =>
 330                 length := "1000";
 331             when NONE =>
 332                 length := "0000";
 333         end case;
 334
 335         -- execute unit
 336         v.e.nia := d_in.nia;
 337         v.e.unit := d_in.decode.unit;
 338         v.e.insn_type := d_in.decode.insn_type;
 339         v.e.read_reg1 := decoded_reg_a.reg;
 340         v.e.read_data1 := decoded_reg_a.data;
 341         v.e.bypass_data1 := gpr_a_bypass;
 342         v.e.read_reg2 := decoded_reg_b.reg;
 343         v.e.read_data2 := decoded_reg_b.data;
 344         v.e.bypass_data2 := gpr_b_bypass;
 345         v.e.read_data3 := decoded_reg_c.data;
 346         v.e.bypass_data3 := gpr_c_bypass;
 347         v.e.write_reg := decoded_reg_o.reg;
 348         v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 349         if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
 350             v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 351         end if;
 352         v.e.cr := c_in.read_cr_data;
 353         v.e.bypass_cr := cr_bypass;
 354         v.e.xerc := c_in.read_xerc_data;
 355         v.e.invert_a := d_in.decode.invert_a;
 356         v.e.invert_out := d_in.decode.invert_out;
 357         v.e.input_carry := d_in.decode.input_carry;
 358         v.e.output_carry := d_in.decode.output_carry;
 359         v.e.is_32bit := d_in.decode.is_32bit;
 360         v.e.is_signed := d_in.decode.is_signed;
 361         if d_in.decode.lr = '1' then
 362             v.e.lr := insn_lk(d_in.insn);
 363         end if;
 364         v.e.insn := d_in.insn;
 365         v.e.data_len := length;
 366         v.e.byte_reverse := d_in.decode.byte_reverse;
 367         v.e.sign_extend := d_in.decode.sign_extend;
 368         v.e.update := d_in.decode.update;
 369         v.e.reserve := d_in.decode.reserve;
 370         v.e.br_pred := d_in.br_pred;
 371
 372         -- issue control
 373         control_valid_in <= d_in.valid;
 374         control_sgl_pipe <= d_in.decode.sgl_pipe;
 375
 376         gpr_write_valid <= decoded_reg_o.reg_valid;
 377         gpr_write <= decoded_reg_o.reg;
 378         gpr_bypassable <= '0';
 379         if EX1_BYPASS and d_in.decode.unit = ALU then
 380             gpr_bypassable <= '1';
 381         end if;
 382         update_gpr_write_valid <= d_in.decode.update;
 383         update_gpr_write_reg <= decoded_reg_a.reg;
 384         if v.e.lr = '1' then
 385             -- there are no instructions that have both update=1 and lr=1
 386             update_gpr_write_valid <= '1';
 387             update_gpr_write_reg <= fast_spr_num(SPR_LR);
 388         end if;
 389
 390         gpr_a_read_valid <= decoded_reg_a.reg_valid;
 391         gpr_a_read <= decoded_reg_a.reg;
 392
 393         gpr_b_read_valid <= decoded_reg_b.reg_valid;
 394         gpr_b_read <= decoded_reg_b.reg;
 395
 396         gpr_c_read_valid <= decoded_reg_c.reg_valid;
 397         gpr_c_read <= gspr_to_gpr(decoded_reg_c.reg);
 398
 399         cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 400         cr_bypass_avail <= '0';
 401         if EX1_BYPASS then
 402             cr_bypass_avail <= d_in.decode.output_cr;
 403         end if;
 404
 405         v.e.valid := control_valid_out;
 406
 407         if rst = '1' or flush_in = '1' then
 408             v.e := Decode2ToExecute1Init;
 409         end if;
 410
 411         -- Update registers
 412         rin <= v;
 413
 414         -- Update outputs
 415         e_out <= r.e;
 416     end process;
 417
 418     d2_log: if LOG_LENGTH > 0 generate
 419         signal log_data : std_ulogic_vector(9 downto 0);
 420     begin
 421         dec2_log : process(clk)
 422         begin
 423             if rising_edge(clk) then
 424                 log_data <= r.e.nia(5 downto 2) &
 425                             r.e.valid &
 426                             stopped_out &
 427                             stall_out &
 428                             r.e.bypass_data3 &
 429                             r.e.bypass_data2 &
 430                             r.e.bypass_data1;
 431             end if;
 432         end process;
 433         log_out <= log_data;
 434     end generate;
 435
 436 end architecture behaviour;