decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12         port (
  13                 clk   : in std_ulogic;
  14                 rst   : in std_ulogic;
  15
  16                 complete_in : in std_ulogic;
  17                 stall_in : in std_ulogic;
  18                 stall_out : out std_ulogic;
  19
  20                 stopped_out : out std_ulogic;
  21
  22                 flush_in: in std_ulogic;
  23
  24                 d_in  : in Decode1ToDecode2Type;
  25
  26                 e_out : out Decode2ToExecute1Type;
  27                 m_out : out Decode2ToMultiplyType;
  28                 d_out : out Decode2ToDividerType;
  29                 l_out : out Decode2ToLoadstore1Type;
  30
  31                 r_in  : in RegisterFileToDecode2Type;
  32                 r_out : out Decode2ToRegisterFileType;
  33
  34                 c_in  : in CrFileToDecode2Type;
  35                 c_out : out Decode2ToCrFileType
  36         );
  37 end entity decode2;
  38
  39 architecture behaviour of decode2 is
  40         type reg_type is record
  41                 e : Decode2ToExecute1Type;
  42                 m : Decode2ToMultiplyType;
  43                 d : Decode2ToDividerType;
  44                 l : Decode2ToLoadstore1Type;
  45         end record;
  46
  47         signal r, rin : reg_type;
  48
  49         type decode_input_reg_t is record
  50                 reg_valid : std_ulogic;
  51                 reg       : gspr_index_t;
  52                 data      : std_ulogic_vector(63 downto 0);
  53         end record;
  54
  55         type decode_output_reg_t is record
  56                 reg_valid : std_ulogic;
  57                 reg       : gspr_index_t;
  58         end record;
  59
  60         function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  61                                      reg_data : std_ulogic_vector(63 downto 0);
  62                                      ispr : gspr_index_t) return decode_input_reg_t is
  63         begin
  64                 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  65                     assert is_fast_spr(ispr) = '0' report "Decode A says GPR but ISPR says SPR:" &
  66                         to_hstring(ispr) severity failure;
  67                     return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  68                 elsif t = SPR then
  69                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  70                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
  71                     -- operations are single issue.
  72                     --
  73                     assert is_fast_spr(ispr) =  '1' or ispr = "000000"
  74                         report "Decode A says SPR but ISPR is invalid:" &
  75                         to_hstring(ispr) severity failure;
  76                     return (is_fast_spr(ispr), ispr, reg_data);
  77                 else
  78                         return ('0', (others => '0'), (others => '0'));
  79                 end if;
  80         end;
  81
  82         function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  83                                      reg_data : std_ulogic_vector(63 downto 0);
  84                                      ispr : gspr_index_t) return decode_input_reg_t is
  85         begin
  86                 case t is
  87                 when RB =>
  88                     assert is_fast_spr(ispr) = '0' report "Decode B says GPR but ISPR says SPR:" &
  89                         to_hstring(ispr) severity failure;
  90                     return ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
  91                 when CONST_UI =>
  92                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  93                 when CONST_SI =>
  94                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  95                 when CONST_SI_HI =>
  96                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
  97                 when CONST_UI_HI =>
  98                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
  99                 when CONST_LI =>
 100                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
 101                 when CONST_BD =>
 102                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 103                 when CONST_DS =>
 104                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 105                 when CONST_M1 =>
 106                         return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 107                 when CONST_SH =>
 108                         return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 109                 when CONST_SH32 =>
 110                         return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 111                 when SPR =>
 112                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 113                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
 114                     -- operations are single issue.
 115                     assert is_fast_spr(ispr) = '1' or ispr = "000000"
 116                         report "Decode B says SPR but ISPR is invalid:" &
 117                         to_hstring(ispr) severity failure;
 118                     return (is_fast_spr(ispr), ispr, reg_data);
 119                 when NONE =>
 120                         return ('0', (others => '0'), (others => '0'));
 121                 end case;
 122         end;
 123
 124         function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 125                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 126         begin
 127                 case t is
 128                 when RS =>
 129                         return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 130                 when NONE =>
 131                         return ('0', (others => '0'), (others => '0'));
 132                 end case;
 133         end;
 134
 135         function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 136                                     ispr : gspr_index_t) return decode_output_reg_t is
 137         begin
 138                 case t is
 139                 when RT =>
 140                     return ('1', gpr_to_gspr(insn_rt(insn_in)));
 141                 when RA =>
 142                     return ('1', gpr_to_gspr(insn_ra(insn_in)));
 143                 when SPR =>
 144                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 145                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
 146                     -- operations are single issue.
 147                     assert is_fast_spr(ispr) = '1' or ispr = "000000"
 148                         report "Decode B says SPR but ISPR is invalid:" &
 149                         to_hstring(ispr) severity failure;
 150                     return (is_fast_spr(ispr), ispr);
 151                 when NONE =>
 152                     return ('0', "000000");
 153                 end case;
 154         end;
 155
 156         function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 157         begin
 158                 case t is
 159                 when RC =>
 160                         return insn_rc(insn_in);
 161                 when ONE =>
 162                         return '1';
 163                 when NONE =>
 164                         return '0';
 165                 end case;
 166         end;
 167
 168         -- For now, use "rc" in the decode table to decide whether oe exists.
 169         -- This is not entirely correct architecturally: For mulhd and
 170         -- mulhdu, the OE field is reserved. It remains to be seen what an
 171         -- actual POWER9 does if we set it on those instructions, for now we
 172         -- test that further down when assigning to the multiplier oe input.
 173         --
 174         function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 175         begin
 176                 case t is
 177                 when RC =>
 178                         return insn_oe(insn_in);
 179                 when OTHERS =>
 180                         return '0';
 181                 end case;
 182         end;
 183
 184         -- issue control signals
 185         signal control_valid_in : std_ulogic;
 186         signal control_valid_out : std_ulogic;
 187         signal control_sgl_pipe : std_logic;
 188
 189         signal gpr_write_valid : std_ulogic;
 190         signal gpr_write : gspr_index_t;
 191
 192         signal gpr_a_read_valid : std_ulogic;
 193         signal gpr_a_read :gspr_index_t;
 194
 195         signal gpr_b_read_valid : std_ulogic;
 196         signal gpr_b_read : gspr_index_t;
 197
 198         signal gpr_c_read_valid : std_ulogic;
 199         signal gpr_c_read : gpr_index_t;
 200
 201         signal cr_write_valid : std_ulogic;
 202 begin
 203         control_0: entity work.control
 204         generic map (
 205                 PIPELINE_DEPTH => 1
 206         )
 207         port map (
 208                 clk         => clk,
 209                 rst         => rst,
 210
 211                 complete_in => complete_in,
 212                 valid_in    => control_valid_in,
 213                 stall_in    => stall_in,
 214                 flush_in    => flush_in,
 215                 sgl_pipe_in => control_sgl_pipe,
 216                 stop_mark_in => d_in.stop_mark,
 217
 218                 gpr_write_valid_in => gpr_write_valid,
 219                 gpr_write_in       => gpr_write,
 220
 221                 gpr_a_read_valid_in  => gpr_a_read_valid,
 222                 gpr_a_read_in        => gpr_a_read,
 223
 224                 gpr_b_read_valid_in  => gpr_b_read_valid,
 225                 gpr_b_read_in        => gpr_b_read,
 226
 227                 gpr_c_read_valid_in  => gpr_c_read_valid,
 228                 gpr_c_read_in        => gpr_c_read,
 229
 230                 cr_read_in           => d_in.decode.input_cr,
 231                 cr_write_in           => cr_write_valid,
 232
 233                 valid_out   => control_valid_out,
 234                 stall_out   => stall_out,
 235                 stopped_out => stopped_out
 236         );
 237
 238         decode2_0: process(clk)
 239         begin
 240                 if rising_edge(clk) then
 241                         if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' or rin.d.valid = '1' then
 242                                 report "execute " & to_hstring(rin.e.nia);
 243                         end if;
 244                         r <= rin;
 245                 end if;
 246         end process;
 247
 248         r_out.read1_reg <= gpr_or_spr_to_gspr(insn_ra(d_in.insn), d_in.ispr1);
 249         r_out.read2_reg <= gpr_or_spr_to_gspr(insn_rb(d_in.insn), d_in.ispr2);
 250         r_out.read3_reg <= insn_rs(d_in.insn);
 251
 252         c_out.read <= d_in.decode.input_cr;
 253
 254         decode2_1: process(all)
 255                 variable v : reg_type;
 256                 variable mul_a : std_ulogic_vector(63 downto 0);
 257                 variable mul_b : std_ulogic_vector(63 downto 0);
 258                 variable decoded_reg_a : decode_input_reg_t;
 259                 variable decoded_reg_b : decode_input_reg_t;
 260                 variable decoded_reg_c : decode_input_reg_t;
 261                 variable decoded_reg_o : decode_output_reg_t;
 262                 variable signed_division: std_ulogic;
 263                 variable length : std_ulogic_vector(3 downto 0);
 264         begin
 265                 v := r;
 266
 267                 v.e := Decode2ToExecute1Init;
 268                 v.l := Decode2ToLoadStore1Init;
 269                 v.m := Decode2ToMultiplyInit;
 270                 v.d := Decode2ToDividerInit;
 271
 272                 mul_a := (others => '0');
 273                 mul_b := (others => '0');
 274
 275                 --v.e.input_cr := d_in.decode.input_cr;
 276                 --v.m.input_cr := d_in.decode.input_cr;
 277                 --v.e.output_cr := d_in.decode.output_cr;
 278
 279                 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1);
 280                 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 281                 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 282                 decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
 283
 284                 r_out.read1_enable <= decoded_reg_a.reg_valid;
 285                 r_out.read2_enable <= decoded_reg_b.reg_valid;
 286                 r_out.read3_enable <= decoded_reg_c.reg_valid;
 287
 288                 case d_in.decode.length is
 289                 when is1B =>
 290                         length := "0001";
 291                 when is2B =>
 292                         length := "0010";
 293                 when is4B =>
 294                         length := "0100";
 295                 when is8B =>
 296                         length := "1000";
 297                 when NONE =>
 298                         length := "0000";
 299                 end case;
 300
 301                 -- execute unit
 302                 v.e.nia := d_in.nia;
 303                 v.e.insn_type := d_in.decode.insn_type;
 304                 v.e.read_reg1 := decoded_reg_a.reg;
 305                 v.e.read_data1 := decoded_reg_a.data;
 306                 v.e.read_reg2 := decoded_reg_b.reg;
 307                 v.e.read_data2 := decoded_reg_b.data;
 308                 v.e.read_data3 := decoded_reg_c.data;
 309                 v.e.write_reg := decoded_reg_o.reg;
 310                 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 311                 v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 312                 v.e.cr := c_in.read_cr_data;
 313                 v.e.xerc := c_in.read_xerc_data;
 314                 v.e.invert_a := d_in.decode.invert_a;
 315                 v.e.invert_out := d_in.decode.invert_out;
 316                 v.e.input_carry := d_in.decode.input_carry;
 317                 v.e.output_carry := d_in.decode.output_carry;
 318                 v.e.is_32bit := d_in.decode.is_32bit;
 319                 v.e.is_signed := d_in.decode.is_signed;
 320                 if d_in.decode.lr = '1' then
 321                         v.e.lr := insn_lk(d_in.insn);
 322                 end if;
 323                 v.e.insn := d_in.insn;
 324                 v.e.data_len := length;
 325
 326                 -- multiply unit
 327                 v.m.insn_type := d_in.decode.insn_type;
 328                 mul_a := decoded_reg_a.data;
 329                 mul_b := decoded_reg_b.data;
 330                 v.m.write_reg := gspr_to_gpr(decoded_reg_o.reg);
 331                 v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
 332                 v.m.xerc := c_in.read_xerc_data;
 333                 if v.m.insn_type = OP_MUL_L64 then
 334                   v.m.oe := decode_oe(d_in.decode.rc, d_in.insn);
 335                 end if;
 336                 v.m.is_32bit := d_in.decode.is_32bit;
 337
 338                 if d_in.decode.is_32bit = '1' then
 339                         if d_in.decode.is_signed = '1' then
 340                                 v.m.data1 := (others => mul_a(31));
 341                                 v.m.data1(31 downto 0) := mul_a(31 downto 0);
 342                                 v.m.data2 := (others => mul_b(31));
 343                                 v.m.data2(31 downto 0) := mul_b(31 downto 0);
 344                         else
 345                                 v.m.data1 := '0' & x"00000000" & mul_a(31 downto 0);
 346                                 v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
 347                         end if;
 348                 else
 349                         if d_in.decode.is_signed = '1' then
 350                                 v.m.data1 := mul_a(63) & mul_a;
 351                                 v.m.data2 := mul_b(63) & mul_b;
 352                         else
 353                                 v.m.data1 := '0' & mul_a;
 354                                 v.m.data2 := '0' & mul_b;
 355                         end if;
 356                 end if;
 357
 358                 -- divide unit
 359                 -- PPC divide and modulus instruction words have these bits in
 360                 -- the bottom 11 bits: o1dns 010t1 r
 361                 -- where o = OE for div instrs, signedness for mod instrs
 362                 --       d = 1 for div*, 0 for mod*
 363                 --       n = 1 for normal, 0 for extended (dividend << 32/64)
 364                 --       s = 1 for signed, 0 for unsigned (for div*)
 365                 --       t = 1 for 32-bit, 0 for 64-bit
 366                 --       r = RC bit (record condition code)
 367                 v.d.write_reg := gspr_to_gpr(decoded_reg_o.reg);
 368                 v.d.is_modulus := not d_in.insn(8);
 369                 v.d.is_32bit := d_in.insn(2);
 370                 if d_in.insn(8) = '1' then
 371                         signed_division := d_in.insn(6);
 372                 else
 373                         signed_division := d_in.insn(10);
 374                 end if;
 375                 v.d.is_signed := signed_division;
 376                 if d_in.insn(2) = '0' then
 377                         -- 64-bit forms
 378                         if d_in.insn(8) = '1' and d_in.insn(7) = '0' then
 379                                 v.d.is_extended := '1';
 380                         end if;
 381                         v.d.dividend := decoded_reg_a.data;
 382                         v.d.divisor := decoded_reg_b.data;
 383                 else
 384                         -- 32-bit forms
 385                         if d_in.insn(8) = '1' and d_in.insn(7) = '0' then   -- extended forms
 386                                 v.d.dividend := decoded_reg_a.data(31 downto 0) & x"00000000";
 387                         elsif signed_division = '1' and decoded_reg_a.data(31) = '1' then
 388                                 -- sign extend to 64 bits
 389                                 v.d.dividend := x"ffffffff" & decoded_reg_a.data(31 downto 0);
 390                         else
 391                                 v.d.dividend := x"00000000" & decoded_reg_a.data(31 downto 0);
 392                         end if;
 393                         if signed_division = '1' and decoded_reg_b.data(31) = '1' then
 394                                 v.d.divisor := x"ffffffff" & decoded_reg_b.data(31 downto 0);
 395                         else
 396                                 v.d.divisor := x"00000000" & decoded_reg_b.data(31 downto 0);
 397                         end if;
 398                 end if;
 399                 v.d.rc := decode_rc(d_in.decode.rc, d_in.insn);
 400                 v.d.xerc := c_in.read_xerc_data;
 401                 v.d.oe := decode_oe(d_in.decode.rc, d_in.insn);
 402
 403                 -- load/store unit
 404                 v.l.update_reg := gspr_to_gpr(decoded_reg_a.reg);
 405                 v.l.addr1 := decoded_reg_a.data;
 406                 v.l.addr2 := decoded_reg_b.data;
 407                 v.l.data := decoded_reg_c.data;
 408                 v.l.write_reg := gspr_to_gpr(decoded_reg_o.reg);
 409
 410                 if d_in.decode.insn_type = OP_LOAD then
 411                         v.l.load := '1';
 412                 else
 413                         v.l.load := '0';
 414                 end if;
 415
 416                 v.l.length := length;
 417                 v.l.byte_reverse := d_in.decode.byte_reverse;
 418                 v.l.sign_extend := d_in.decode.sign_extend;
 419                 v.l.update := d_in.decode.update;
 420                 v.l.xerc := c_in.read_xerc_data;
 421
 422                 -- issue control
 423                 control_valid_in <= d_in.valid;
 424                 control_sgl_pipe <= d_in.decode.sgl_pipe;
 425
 426                 gpr_write_valid <= decoded_reg_o.reg_valid;
 427                 gpr_write <= decoded_reg_o.reg;
 428
 429                 gpr_a_read_valid <= decoded_reg_a.reg_valid;
 430                 gpr_a_read <= decoded_reg_a.reg;
 431
 432                 gpr_b_read_valid <= decoded_reg_b.reg_valid;
 433                 gpr_b_read <= decoded_reg_b.reg;
 434
 435                 gpr_c_read_valid <= decoded_reg_c.reg_valid;
 436                 gpr_c_read <= gspr_to_gpr(decoded_reg_c.reg);
 437
 438                 cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 439
 440                 v.e.valid := '0';
 441                 v.m.valid := '0';
 442                 v.d.valid := '0';
 443                 v.l.valid := '0';
 444                 case d_in.decode.unit is
 445                 when ALU =>
 446                         v.e.valid := control_valid_out;
 447                 when LDST =>
 448                         v.l.valid := control_valid_out;
 449                 when MUL =>
 450                         v.m.valid := control_valid_out;
 451                 when DIV =>
 452                         v.d.valid := control_valid_out;
 453                 when NONE =>
 454                         v.e.valid := control_valid_out;
 455                         v.e.insn_type := OP_ILLEGAL;
 456                 end case;
 457
 458                 if rst = '1' then
 459                         v.e := Decode2ToExecute1Init;
 460                         v.l := Decode2ToLoadStore1Init;
 461                         v.m := Decode2ToMultiplyInit;
 462                         v.d := Decode2ToDividerInit;
 463                 end if;
 464
 465                 -- Update registers
 466                 rin <= v;
 467
 468                 -- Update outputs
 469                 e_out <= r.e;
 470                 l_out <= r.l;
 471                 m_out <= r.m;
 472                 d_out <= r.d;
 473         end process;
 474 end architecture behaviour;