decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12         generic (
  13                 EX1_BYPASS : boolean := true
  14         );
  15         port (
  16                 clk   : in std_ulogic;
  17                 rst   : in std_ulogic;
  18
  19                 complete_in : in std_ulogic;
  20                 stall_in : in std_ulogic;
  21                 stall_out : out std_ulogic;
  22
  23                 stopped_out : out std_ulogic;
  24
  25                 flush_in: in std_ulogic;
  26
  27                 d_in  : in Decode1ToDecode2Type;
  28
  29                 e_out : out Decode2ToExecute1Type;
  30
  31                 r_in  : in RegisterFileToDecode2Type;
  32                 r_out : out Decode2ToRegisterFileType;
  33
  34                 c_in  : in CrFileToDecode2Type;
  35                 c_out : out Decode2ToCrFileType
  36         );
  37 end entity decode2;
  38
  39 architecture behaviour of decode2 is
  40         type reg_type is record
  41                 e : Decode2ToExecute1Type;
  42         end record;
  43
  44         signal r, rin : reg_type;
  45
  46         type decode_input_reg_t is record
  47                 reg_valid : std_ulogic;
  48                 reg       : gspr_index_t;
  49                 data      : std_ulogic_vector(63 downto 0);
  50         end record;
  51
  52         type decode_output_reg_t is record
  53                 reg_valid : std_ulogic;
  54                 reg       : gspr_index_t;
  55         end record;
  56
  57         function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  58                                      reg_data : std_ulogic_vector(63 downto 0);
  59                                      ispr : gspr_index_t) return decode_input_reg_t is
  60         begin
  61                 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  62                     assert is_fast_spr(ispr) = '0' report "Decode A says GPR but ISPR says SPR:" &
  63                         to_hstring(ispr) severity failure;
  64                     return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  65                 elsif t = SPR then
  66                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  67                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
  68                     -- operations are single issue.
  69                     --
  70                     assert is_fast_spr(ispr) =  '1' or ispr = "000000"
  71                         report "Decode A says SPR but ISPR is invalid:" &
  72                         to_hstring(ispr) severity failure;
  73                     return (is_fast_spr(ispr), ispr, reg_data);
  74                 else
  75                         return ('0', (others => '0'), (others => '0'));
  76                 end if;
  77         end;
  78
  79         function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  80                                      reg_data : std_ulogic_vector(63 downto 0);
  81                                      ispr : gspr_index_t) return decode_input_reg_t is
  82         begin
  83                 case t is
  84                 when RB =>
  85                     assert is_fast_spr(ispr) = '0' report "Decode B says GPR but ISPR says SPR:" &
  86                         to_hstring(ispr) severity failure;
  87                     return ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
  88                 when CONST_UI =>
  89                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  90                 when CONST_SI =>
  91                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  92                 when CONST_SI_HI =>
  93                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
  94                 when CONST_UI_HI =>
  95                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
  96                 when CONST_LI =>
  97                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
  98                 when CONST_BD =>
  99                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 100                 when CONST_DS =>
 101                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 102                 when CONST_M1 =>
 103                         return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 104                 when CONST_SH =>
 105                         return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 106                 when CONST_SH32 =>
 107                         return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 108                 when SPR =>
 109                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 110                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
 111                     -- operations are single issue.
 112                     assert is_fast_spr(ispr) = '1' or ispr = "000000"
 113                         report "Decode B says SPR but ISPR is invalid:" &
 114                         to_hstring(ispr) severity failure;
 115                     return (is_fast_spr(ispr), ispr, reg_data);
 116                 when NONE =>
 117                         return ('0', (others => '0'), (others => '0'));
 118                 end case;
 119         end;
 120
 121         function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 122                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 123         begin
 124                 case t is
 125                 when RS =>
 126                         return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 127                 when NONE =>
 128                         return ('0', (others => '0'), (others => '0'));
 129                 end case;
 130         end;
 131
 132         function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 133                                     ispr : gspr_index_t) return decode_output_reg_t is
 134         begin
 135                 case t is
 136                 when RT =>
 137                     return ('1', gpr_to_gspr(insn_rt(insn_in)));
 138                 when RA =>
 139                     return ('1', gpr_to_gspr(insn_ra(insn_in)));
 140                 when SPR =>
 141                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 142                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
 143                     -- operations are single issue.
 144                     assert is_fast_spr(ispr) = '1' or ispr = "000000"
 145                         report "Decode B says SPR but ISPR is invalid:" &
 146                         to_hstring(ispr) severity failure;
 147                     return (is_fast_spr(ispr), ispr);
 148                 when NONE =>
 149                     return ('0', "000000");
 150                 end case;
 151         end;
 152
 153         function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 154         begin
 155                 case t is
 156                 when RC =>
 157                         return insn_rc(insn_in);
 158                 when ONE =>
 159                         return '1';
 160                 when NONE =>
 161                         return '0';
 162                 end case;
 163         end;
 164
 165         -- For now, use "rc" in the decode table to decide whether oe exists.
 166         -- This is not entirely correct architecturally: For mulhd and
 167         -- mulhdu, the OE field is reserved. It remains to be seen what an
 168         -- actual POWER9 does if we set it on those instructions, for now we
 169         -- test that further down when assigning to the multiplier oe input.
 170         --
 171         function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 172         begin
 173                 case t is
 174                 when RC =>
 175                         return insn_oe(insn_in);
 176                 when OTHERS =>
 177                         return '0';
 178                 end case;
 179         end;
 180
 181         -- issue control signals
 182         signal control_valid_in : std_ulogic;
 183         signal control_valid_out : std_ulogic;
 184         signal control_sgl_pipe : std_logic;
 185
 186         signal gpr_write_valid : std_ulogic;
 187         signal gpr_write : gspr_index_t;
 188         signal gpr_bypassable  : std_ulogic;
 189
 190         signal gpr_a_read_valid : std_ulogic;
 191         signal gpr_a_read :gspr_index_t;
 192         signal gpr_a_bypass : std_ulogic;
 193
 194         signal gpr_b_read_valid : std_ulogic;
 195         signal gpr_b_read : gspr_index_t;
 196         signal gpr_b_bypass : std_ulogic;
 197
 198         signal gpr_c_read_valid : std_ulogic;
 199         signal gpr_c_read : gpr_index_t;
 200         signal gpr_c_bypass : std_ulogic;
 201
 202         signal cr_write_valid : std_ulogic;
 203 begin
 204         control_0: entity work.control
 205         generic map (
 206                 PIPELINE_DEPTH => 1
 207         )
 208         port map (
 209                 clk         => clk,
 210                 rst         => rst,
 211
 212                 complete_in => complete_in,
 213                 valid_in    => control_valid_in,
 214                 stall_in    => stall_in,
 215                 flush_in    => flush_in,
 216                 sgl_pipe_in => control_sgl_pipe,
 217                 stop_mark_in => d_in.stop_mark,
 218
 219                 gpr_write_valid_in => gpr_write_valid,
 220                 gpr_write_in       => gpr_write,
 221                 gpr_bypassable     => gpr_bypassable,
 222
 223                 gpr_a_read_valid_in  => gpr_a_read_valid,
 224                 gpr_a_read_in        => gpr_a_read,
 225
 226                 gpr_b_read_valid_in  => gpr_b_read_valid,
 227                 gpr_b_read_in        => gpr_b_read,
 228
 229                 gpr_c_read_valid_in  => gpr_c_read_valid,
 230                 gpr_c_read_in        => gpr_c_read,
 231
 232                 cr_read_in           => d_in.decode.input_cr,
 233                 cr_write_in           => cr_write_valid,
 234
 235                 valid_out   => control_valid_out,
 236                 stall_out   => stall_out,
 237                 stopped_out => stopped_out,
 238
 239                 gpr_bypass_a => gpr_a_bypass,
 240                 gpr_bypass_b => gpr_b_bypass,
 241                 gpr_bypass_c => gpr_c_bypass
 242         );
 243
 244         decode2_0: process(clk)
 245         begin
 246                 if rising_edge(clk) then
 247                         if rin.e.valid = '1' then
 248                                 report "execute " & to_hstring(rin.e.nia);
 249                         end if;
 250                         r <= rin;
 251                 end if;
 252         end process;
 253
 254         r_out.read1_reg <= gpr_or_spr_to_gspr(insn_ra(d_in.insn), d_in.ispr1);
 255         r_out.read2_reg <= gpr_or_spr_to_gspr(insn_rb(d_in.insn), d_in.ispr2);
 256         r_out.read3_reg <= insn_rs(d_in.insn);
 257
 258         c_out.read <= d_in.decode.input_cr;
 259
 260         decode2_1: process(all)
 261                 variable v : reg_type;
 262                 variable mul_a : std_ulogic_vector(63 downto 0);
 263                 variable mul_b : std_ulogic_vector(63 downto 0);
 264                 variable decoded_reg_a : decode_input_reg_t;
 265                 variable decoded_reg_b : decode_input_reg_t;
 266                 variable decoded_reg_c : decode_input_reg_t;
 267                 variable decoded_reg_o : decode_output_reg_t;
 268                 variable length : std_ulogic_vector(3 downto 0);
 269         begin
 270                 v := r;
 271
 272                 v.e := Decode2ToExecute1Init;
 273
 274                 mul_a := (others => '0');
 275                 mul_b := (others => '0');
 276
 277                 --v.e.input_cr := d_in.decode.input_cr;
 278                 --v.e.output_cr := d_in.decode.output_cr;
 279
 280                 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1);
 281                 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 282                 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 283                 decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
 284
 285                 r_out.read1_enable <= decoded_reg_a.reg_valid;
 286                 r_out.read2_enable <= decoded_reg_b.reg_valid;
 287                 r_out.read3_enable <= decoded_reg_c.reg_valid;
 288
 289                 case d_in.decode.length is
 290                 when is1B =>
 291                         length := "0001";
 292                 when is2B =>
 293                         length := "0010";
 294                 when is4B =>
 295                         length := "0100";
 296                 when is8B =>
 297                         length := "1000";
 298                 when NONE =>
 299                         length := "0000";
 300                 end case;
 301
 302                 -- execute unit
 303                 v.e.nia := d_in.nia;
 304                 v.e.insn_type := d_in.decode.insn_type;
 305                 v.e.read_reg1 := decoded_reg_a.reg;
 306                 v.e.read_data1 := decoded_reg_a.data;
 307                 v.e.bypass_data1 := gpr_a_bypass;
 308                 v.e.read_reg2 := decoded_reg_b.reg;
 309                 v.e.read_data2 := decoded_reg_b.data;
 310                 v.e.bypass_data2 := gpr_b_bypass;
 311                 v.e.read_data3 := decoded_reg_c.data;
 312                 v.e.bypass_data3 := gpr_c_bypass;
 313                 v.e.write_reg := decoded_reg_o.reg;
 314                 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 315                 if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
 316                         v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 317                 end if;
 318                 v.e.cr := c_in.read_cr_data;
 319                 v.e.xerc := c_in.read_xerc_data;
 320                 v.e.invert_a := d_in.decode.invert_a;
 321                 v.e.invert_out := d_in.decode.invert_out;
 322                 v.e.input_carry := d_in.decode.input_carry;
 323                 v.e.output_carry := d_in.decode.output_carry;
 324                 v.e.is_32bit := d_in.decode.is_32bit;
 325                 v.e.is_signed := d_in.decode.is_signed;
 326                 if d_in.decode.lr = '1' then
 327                         v.e.lr := insn_lk(d_in.insn);
 328                 end if;
 329                 v.e.insn := d_in.insn;
 330                 v.e.data_len := length;
 331                 v.e.byte_reverse := d_in.decode.byte_reverse;
 332                 v.e.sign_extend := d_in.decode.sign_extend;
 333                 v.e.update := d_in.decode.update;
 334
 335                 -- issue control
 336                 control_valid_in <= d_in.valid;
 337                 control_sgl_pipe <= d_in.decode.sgl_pipe;
 338
 339                 gpr_write_valid <= decoded_reg_o.reg_valid;
 340                 gpr_write <= decoded_reg_o.reg;
 341                 gpr_bypassable <= '0';
 342                 if EX1_BYPASS and d_in.decode.unit = ALU then
 343                         gpr_bypassable <= '1';
 344                 end if;
 345
 346                 gpr_a_read_valid <= decoded_reg_a.reg_valid;
 347                 gpr_a_read <= decoded_reg_a.reg;
 348
 349                 gpr_b_read_valid <= decoded_reg_b.reg_valid;
 350                 gpr_b_read <= decoded_reg_b.reg;
 351
 352                 gpr_c_read_valid <= decoded_reg_c.reg_valid;
 353                 gpr_c_read <= gspr_to_gpr(decoded_reg_c.reg);
 354
 355                 cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 356
 357                 v.e.valid := control_valid_out;
 358                 if d_in.decode.unit = NONE then
 359                         v.e.insn_type := OP_ILLEGAL;
 360                 end if;
 361
 362                 if rst = '1' then
 363                         v.e := Decode2ToExecute1Init;
 364                 end if;
 365
 366                 -- Update registers
 367                 rin <= v;
 368
 369                 -- Update outputs
 370                 e_out <= r.e;
 371         end process;
 372 end architecture behaviour;