decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12         port (
  13                 clk   : in std_ulogic;
  14                 rst   : in std_ulogic;
  15
  16                 complete_in : in std_ulogic;
  17                 stall_out : out std_ulogic;
  18
  19                 stopped_out : out std_ulogic;
  20
  21                 flush_in: in std_ulogic;
  22
  23                 d_in  : in Decode1ToDecode2Type;
  24
  25                 e_out : out Decode2ToExecute1Type;
  26                 m_out : out Decode2ToMultiplyType;
  27                 d_out : out Decode2ToDividerType;
  28                 l_out : out Decode2ToLoadstore1Type;
  29
  30                 r_in  : in RegisterFileToDecode2Type;
  31                 r_out : out Decode2ToRegisterFileType;
  32
  33                 c_in  : in CrFileToDecode2Type;
  34                 c_out : out Decode2ToCrFileType
  35         );
  36 end entity decode2;
  37
  38 architecture behaviour of decode2 is
  39         type state_type is (IDLE, WAIT_FOR_PREV_TO_COMPLETE, WAIT_FOR_CURR_TO_COMPLETE);
  40
  41         type reg_internal_type is record
  42                 state : state_type;
  43                 outstanding : integer range -1 to 2;
  44         end record;
  45
  46         type reg_type is record
  47                 e : Decode2ToExecute1Type;
  48                 m : Decode2ToMultiplyType;
  49                 d : Decode2ToDividerType;
  50                 l : Decode2ToLoadstore1Type;
  51         end record;
  52
  53         signal r_int, rin_int : reg_internal_type;
  54         signal r, rin : reg_type;
  55
  56         type decode_input_reg_t is record
  57                 reg_valid : std_ulogic;
  58                 reg       : std_ulogic_vector(4 downto 0);
  59                 data      : std_ulogic_vector(63 downto 0);
  60         end record;
  61
  62         function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  63                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  64         begin
  65                 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  66                         return ('1', insn_ra(insn_in), reg_data);
  67                 else
  68                         return ('0', (others => '0'), (others => '0'));
  69                 end if;
  70         end;
  71
  72         function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  73                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  74         begin
  75                 case t is
  76                 when RB =>
  77                         return ('1', insn_rb(insn_in), reg_data);
  78                 when CONST_UI =>
  79                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  80                 when CONST_SI =>
  81                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  82                 when CONST_SI_HI =>
  83                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
  84                 when CONST_UI_HI =>
  85                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
  86                 when CONST_LI =>
  87                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
  88                 when CONST_BD =>
  89                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
  90                 when CONST_DS =>
  91                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
  92                 when CONST_M1 =>
  93                         return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
  94                 when CONST_SH =>
  95                         return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
  96                 when CONST_SH32 =>
  97                         return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
  98                 when NONE =>
  99                         return ('0', (others => '0'), (others => '0'));
 100                 end case;
 101         end;
 102
 103         function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 104                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 105         begin
 106                 case t is
 107                 when RS =>
 108                         return ('1', insn_rs(insn_in), reg_data);
 109                 when NONE =>
 110                         return ('0', (others => '0'), (others => '0'));
 111                 end case;
 112         end;
 113
 114         function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 115         begin
 116                 case t is
 117                 when RT =>
 118                         return insn_rt(insn_in);
 119                 when RA =>
 120                         return insn_ra(insn_in);
 121                 when NONE =>
 122                         return "00000";
 123                 end case;
 124         end;
 125
 126         function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 127         begin
 128                 case t is
 129                 when RC =>
 130                         return insn_rc(insn_in);
 131                 when ONE =>
 132                         return '1';
 133                 when NONE =>
 134                         return '0';
 135                 end case;
 136         end;
 137 begin
 138
 139         decode2_0: process(clk)
 140         begin
 141                 if rising_edge(clk) then
 142                         assert r_int.outstanding <= 1 report "Outstanding bad " & integer'image(r_int.outstanding) severity failure;
 143
 144                         if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' or rin.d.valid = '1' then
 145                                 report "execute " & to_hstring(rin.e.nia);
 146                         end if;
 147                         r <= rin;
 148                         r_int <= rin_int;
 149                 end if;
 150         end process;
 151
 152         r_out.read1_reg <= insn_ra(d_in.insn);
 153         r_out.read2_reg <= insn_rb(d_in.insn);
 154         r_out.read3_reg <= insn_rs(d_in.insn);
 155
 156         c_out.read <= d_in.decode.input_cr;
 157
 158         decode2_1: process(all)
 159                 variable v : reg_type;
 160                 variable v_int : reg_internal_type;
 161                 variable mul_a : std_ulogic_vector(63 downto 0);
 162                 variable mul_b : std_ulogic_vector(63 downto 0);
 163                 variable decoded_reg_a : decode_input_reg_t;
 164                 variable decoded_reg_b : decode_input_reg_t;
 165                 variable decoded_reg_c : decode_input_reg_t;
 166                 variable signed_division: std_ulogic;
 167                 variable is_valid : std_ulogic;
 168         begin
 169                 v := r;
 170                 v_int := r_int;
 171
 172                 v.e := Decode2ToExecute1Init;
 173                 v.l := Decode2ToLoadStore1Init;
 174                 v.m := Decode2ToMultiplyInit;
 175                 v.d := Decode2ToDividerInit;
 176
 177                 mul_a := (others => '0');
 178                 mul_b := (others => '0');
 179
 180                 --v.e.input_cr := d_in.decode.input_cr;
 181                 --v.m.input_cr := d_in.decode.input_cr;
 182                 --v.e.output_cr := d_in.decode.output_cr;
 183
 184                 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data);
 185                 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data);
 186                 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 187
 188                 r_out.read1_enable <= decoded_reg_a.reg_valid;
 189                 r_out.read2_enable <= decoded_reg_b.reg_valid;
 190                 r_out.read3_enable <= decoded_reg_c.reg_valid;
 191
 192                 -- execute unit
 193                 v.e.nia := d_in.nia;
 194                 v.e.insn_type := d_in.decode.insn_type;
 195                 v.e.read_reg1 := decoded_reg_a.reg;
 196                 v.e.read_data1 := decoded_reg_a.data;
 197                 v.e.read_reg2 := decoded_reg_b.reg;
 198                 v.e.read_data2 := decoded_reg_b.data;
 199                 v.e.read_data3 := decoded_reg_c.data;
 200                 v.e.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 201                 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 202                 v.e.cr := c_in.read_cr_data;
 203                 v.e.invert_a := d_in.decode.invert_a;
 204                 v.e.invert_out := d_in.decode.invert_out;
 205                 v.e.input_carry := d_in.decode.input_carry;
 206                 v.e.output_carry := d_in.decode.output_carry;
 207                 v.e.is_32bit := d_in.decode.is_32bit;
 208                 v.e.is_signed := d_in.decode.is_signed;
 209                 if d_in.decode.lr = '1' then
 210                         v.e.lr := insn_lk(d_in.insn);
 211                 end if;
 212                 v.e.insn := d_in.insn;
 213
 214                 -- multiply unit
 215                 v.m.insn_type := d_in.decode.insn_type;
 216                 mul_a := decoded_reg_a.data;
 217                 mul_b := decoded_reg_b.data;
 218                 v.m.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 219                 v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
 220
 221                 if d_in.decode.is_32bit = '1' then
 222                         if d_in.decode.is_signed = '1' then
 223                                 v.m.data1 := (others => mul_a(31));
 224                                 v.m.data1(31 downto 0) := mul_a(31 downto 0);
 225                                 v.m.data2 := (others => mul_b(31));
 226                                 v.m.data2(31 downto 0) := mul_b(31 downto 0);
 227                         else
 228                                 v.m.data1 := '0' & x"00000000" & mul_a(31 downto 0);
 229                                 v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
 230                         end if;
 231                 else
 232                         if d_in.decode.is_signed = '1' then
 233                                 v.m.data1 := mul_a(63) & mul_a;
 234                                 v.m.data2 := mul_b(63) & mul_b;
 235                         else
 236                                 v.m.data1 := '0' & mul_a;
 237                                 v.m.data2 := '0' & mul_b;
 238                         end if;
 239                 end if;
 240
 241                 -- divide unit
 242                 -- PPC divide and modulus instruction words have these bits in
 243                 -- the bottom 11 bits: o1dns 010t1 r
 244                 -- where o = OE for div instrs, signedness for mod instrs
 245                 --       d = 1 for div*, 0 for mod*
 246                 --       n = 1 for normal, 0 for extended (dividend << 32/64)
 247                 --       s = 1 for signed, 0 for unsigned (for div*)
 248                 --       t = 1 for 32-bit, 0 for 64-bit
 249                 --       r = RC bit (record condition code)
 250                 v.d.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 251                 v.d.is_modulus := not d_in.insn(8);
 252                 v.d.is_32bit := d_in.insn(2);
 253                 if d_in.insn(8) = '1' then
 254                         signed_division := d_in.insn(6);
 255                 else
 256                         signed_division := d_in.insn(10);
 257                 end if;
 258                 v.d.is_signed := signed_division;
 259                 if d_in.insn(2) = '0' then
 260                         -- 64-bit forms
 261                         if d_in.insn(8) = '1' and d_in.insn(7) = '0' then
 262                                 v.d.is_extended := '1';
 263                         end if;
 264                         v.d.dividend := decoded_reg_a.data;
 265                         v.d.divisor := decoded_reg_b.data;
 266                 else
 267                         -- 32-bit forms
 268                         if d_in.insn(8) = '1' and d_in.insn(7) = '0' then   -- extended forms
 269                                 v.d.dividend := decoded_reg_a.data(31 downto 0) & x"00000000";
 270                         elsif signed_division = '1' and decoded_reg_a.data(31) = '1' then
 271                                 -- sign extend to 64 bits
 272                                 v.d.dividend := x"ffffffff" & decoded_reg_a.data(31 downto 0);
 273                         else
 274                                 v.d.dividend := x"00000000" & decoded_reg_a.data(31 downto 0);
 275                         end if;
 276                         if signed_division = '1' and decoded_reg_b.data(31) = '1' then
 277                                 v.d.divisor := x"ffffffff" & decoded_reg_b.data(31 downto 0);
 278                         else
 279                                 v.d.divisor := x"00000000" & decoded_reg_b.data(31 downto 0);
 280                         end if;
 281                 end if;
 282                 v.d.rc := decode_rc(d_in.decode.rc, d_in.insn);
 283
 284                 -- load/store unit
 285                 v.l.update_reg := decoded_reg_a.reg;
 286                 v.l.addr1 := decoded_reg_a.data;
 287                 v.l.addr2 := decoded_reg_b.data;
 288                 v.l.data := decoded_reg_c.data;
 289                 v.l.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 290
 291                 if d_in.decode.insn_type = OP_LOAD then
 292                         v.l.load := '1';
 293                 else
 294                         v.l.load := '0';
 295                 end if;
 296
 297                 case d_in.decode.length is
 298                 when is1B =>
 299                         v.l.length := "0001";
 300                 when is2B =>
 301                         v.l.length := "0010";
 302                 when is4B =>
 303                         v.l.length := "0100";
 304                 when is8B =>
 305                         v.l.length := "1000";
 306                 when NONE =>
 307                         v.l.length := "0000";
 308                 end case;
 309
 310                 v.l.byte_reverse := d_in.decode.byte_reverse;
 311                 v.l.sign_extend := d_in.decode.sign_extend;
 312                 v.l.update := d_in.decode.update;
 313
 314                 -- single issue
 315
 316                 if complete_in = '1' then
 317                         v_int.outstanding := v_int.outstanding - 1;
 318                 end if;
 319
 320                 -- state machine to handle instructions that must be single
 321                 -- through the pipeline.
 322                 stall_out <= '0';
 323                 is_valid := d_in.valid;
 324
 325                 -- Handle debugger stop
 326                 stopped_out <= '0';
 327                 if d_in.stop_mark = '1' and v_int.outstanding = 0 then
 328                     stopped_out <= '1';
 329                 end if;
 330
 331                 case v_int.state is
 332                 when IDLE =>
 333                         if (flush_in = '0') and (is_valid = '1') and (d_in.decode.sgl_pipe = '1') then
 334                                 if v_int.outstanding /= 0 then
 335                                         v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
 336                                         stall_out <= '1';
 337                                         is_valid := '0';
 338                                 else
 339                                         -- send insn out and wait on it to complete
 340                                         v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
 341                                 end if;
 342                         end if;
 343
 344                 when WAIT_FOR_PREV_TO_COMPLETE =>
 345                         if v_int.outstanding = 0 then
 346                                 -- send insn out and wait on it to complete
 347                                 v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
 348                         else
 349                                 stall_out <= '1';
 350                                 is_valid := '0';
 351                         end if;
 352
 353                 when WAIT_FOR_CURR_TO_COMPLETE =>
 354                         if v_int.outstanding = 0 then
 355                                 v_int.state := IDLE;
 356                         else
 357                                 stall_out <= '1';
 358                                 is_valid := '0';
 359                         end if;
 360                 end case;
 361
 362                 v.e.valid := '0';
 363                 v.m.valid := '0';
 364                 v.d.valid := '0';
 365                 v.l.valid := '0';
 366                 case d_in.decode.unit is
 367                 when ALU =>
 368                         v.e.valid := is_valid;
 369                 when LDST =>
 370                         v.l.valid := is_valid;
 371                 when MUL =>
 372                         v.m.valid := is_valid;
 373                 when DIV =>
 374                         v.d.valid := is_valid;
 375                 when NONE =>
 376                         v.e.valid := is_valid;
 377                         v.e.insn_type := OP_ILLEGAL;
 378                 end case;
 379
 380                 if flush_in = '1' then
 381                         v.e.valid := '0';
 382                         v.m.valid := '0';
 383                         v.d.valid := '0';
 384                         v.l.valid := '0';
 385                 end if;
 386
 387                 -- track outstanding instructions
 388                 if v.e.valid = '1' or v.l.valid = '1' or v.m.valid = '1' or v.d.valid = '1' then
 389                         v_int.outstanding := v_int.outstanding + 1;
 390                 end if;
 391
 392                 if rst = '1' then
 393                         v_int.state := IDLE;
 394                         v_int.outstanding := 0;
 395                         v.e := Decode2ToExecute1Init;
 396                         v.l := Decode2ToLoadStore1Init;
 397                         v.m := Decode2ToMultiplyInit;
 398                         v.d := Decode2ToDividerInit;
 399                 end if;
 400
 401                 -- Update registers
 402                 rin <= v;
 403                 rin_int <= v_int;
 404
 405                 -- Update outputs
 406                 e_out <= r.e;
 407                 l_out <= r.l;
 408                 m_out <= r.m;
 409                 d_out <= r.d;
 410         end process;
 411 end architecture behaviour;