decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12     generic (
  13         EX1_BYPASS : boolean := true
  14         );
  15     port (
  16         clk   : in std_ulogic;
  17         rst   : in std_ulogic;
  18
  19         complete_in : in std_ulogic;
  20         busy_in   : in std_ulogic;
  21         stall_out : out std_ulogic;
  22
  23         stopped_out : out std_ulogic;
  24
  25         flush_in: in std_ulogic;
  26
  27         d_in  : in Decode1ToDecode2Type;
  28
  29         e_out : out Decode2ToExecute1Type;
  30
  31         r_in  : in RegisterFileToDecode2Type;
  32         r_out : out Decode2ToRegisterFileType;
  33
  34         c_in  : in CrFileToDecode2Type;
  35         c_out : out Decode2ToCrFileType;
  36
  37         log_out : out std_ulogic_vector(9 downto 0)
  38         );
  39 end entity decode2;
  40
  41 architecture behaviour of decode2 is
  42     type reg_type is record
  43         e : Decode2ToExecute1Type;
  44     end record;
  45
  46     signal r, rin : reg_type;
  47
  48     signal deferred : std_ulogic;
  49
  50     signal log_data : std_ulogic_vector(9 downto 0);
  51
  52     type decode_input_reg_t is record
  53         reg_valid : std_ulogic;
  54         reg       : gspr_index_t;
  55         data      : std_ulogic_vector(63 downto 0);
  56     end record;
  57
  58     type decode_output_reg_t is record
  59         reg_valid : std_ulogic;
  60         reg       : gspr_index_t;
  61     end record;
  62
  63     function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  64                                  reg_data : std_ulogic_vector(63 downto 0);
  65                                  ispr : gspr_index_t;
  66                                  instr_addr : std_ulogic_vector(63 downto 0))
  67         return decode_input_reg_t is
  68     begin
  69         if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  70             return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  71         elsif t = SPR then
  72             -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  73             -- If it's all 0, we don't treat it as a dependency as slow SPRs
  74             -- operations are single issue.
  75             --
  76             assert is_fast_spr(ispr) =  '1' or ispr = "000000"
  77                 report "Decode A says SPR but ISPR is invalid:" &
  78                 to_hstring(ispr) severity failure;
  79             return (is_fast_spr(ispr), ispr, reg_data);
  80         elsif t = CIA then
  81             return ('0', (others => '0'), instr_addr);
  82         else
  83             return ('0', (others => '0'), (others => '0'));
  84         end if;
  85     end;
  86
  87     function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  88                                  reg_data : std_ulogic_vector(63 downto 0);
  89                                  ispr : gspr_index_t) return decode_input_reg_t is
  90         variable ret : decode_input_reg_t;
  91     begin
  92         case t is
  93             when RB =>
  94                 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
  95             when CONST_UI =>
  96                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  97             when CONST_SI =>
  98                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  99             when CONST_SI_HI =>
 100                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
 101             when CONST_UI_HI =>
 102                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
 103             when CONST_LI =>
 104                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
 105             when CONST_BD =>
 106                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 107             when CONST_DS =>
 108                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 109             when CONST_DXHI4 =>
 110                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
 111             when CONST_M1 =>
 112                 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 113             when CONST_SH =>
 114                 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 115             when CONST_SH32 =>
 116                 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 117             when SPR =>
 118                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 119                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 120                 -- operations are single issue.
 121                 assert is_fast_spr(ispr) = '1' or ispr = "000000"
 122                     report "Decode B says SPR but ISPR is invalid:" &
 123                     to_hstring(ispr) severity failure;
 124                 ret := (is_fast_spr(ispr), ispr, reg_data);
 125             when NONE =>
 126                 ret := ('0', (others => '0'), (others => '0'));
 127         end case;
 128
 129         return ret;
 130     end;
 131
 132     function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 133                                  reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 134     begin
 135         case t is
 136             when RS =>
 137                 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 138             when NONE =>
 139                 return ('0', (others => '0'), (others => '0'));
 140         end case;
 141     end;
 142
 143     function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 144                                 ispr : gspr_index_t) return decode_output_reg_t is
 145     begin
 146         case t is
 147             when RT =>
 148                 return ('1', gpr_to_gspr(insn_rt(insn_in)));
 149             when RA =>
 150                 return ('1', gpr_to_gspr(insn_ra(insn_in)));
 151             when SPR =>
 152                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 153                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 154                 -- operations are single issue.
 155                 assert is_fast_spr(ispr) = '1' or ispr = "000000"
 156                     report "Decode B says SPR but ISPR is invalid:" &
 157                     to_hstring(ispr) severity failure;
 158                 return (is_fast_spr(ispr), ispr);
 159             when NONE =>
 160                 return ('0', "000000");
 161         end case;
 162     end;
 163
 164     function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 165     begin
 166         case t is
 167             when RC =>
 168                 return insn_rc(insn_in);
 169             when ONE =>
 170                 return '1';
 171             when NONE =>
 172                 return '0';
 173         end case;
 174     end;
 175
 176     -- For now, use "rc" in the decode table to decide whether oe exists.
 177     -- This is not entirely correct architecturally: For mulhd and
 178     -- mulhdu, the OE field is reserved. It remains to be seen what an
 179     -- actual POWER9 does if we set it on those instructions, for now we
 180     -- test that further down when assigning to the multiplier oe input.
 181     --
 182     function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 183     begin
 184         case t is
 185             when RC =>
 186                 return insn_oe(insn_in);
 187             when OTHERS =>
 188                 return '0';
 189         end case;
 190     end;
 191
 192     -- issue control signals
 193     signal control_valid_in : std_ulogic;
 194     signal control_valid_out : std_ulogic;
 195     signal control_sgl_pipe : std_logic;
 196
 197     signal gpr_write_valid : std_ulogic;
 198     signal gpr_write : gspr_index_t;
 199     signal gpr_bypassable  : std_ulogic;
 200
 201     signal update_gpr_write_valid : std_ulogic;
 202     signal update_gpr_write_reg : gspr_index_t;
 203
 204     signal gpr_a_read_valid : std_ulogic;
 205     signal gpr_a_read :gspr_index_t;
 206     signal gpr_a_bypass : std_ulogic;
 207
 208     signal gpr_b_read_valid : std_ulogic;
 209     signal gpr_b_read : gspr_index_t;
 210     signal gpr_b_bypass : std_ulogic;
 211
 212     signal gpr_c_read_valid : std_ulogic;
 213     signal gpr_c_read : gpr_index_t;
 214     signal gpr_c_bypass : std_ulogic;
 215
 216     signal cr_write_valid  : std_ulogic;
 217     signal cr_bypass       : std_ulogic;
 218     signal cr_bypass_avail : std_ulogic;
 219
 220 begin
 221     control_0: entity work.control
 222         generic map (
 223             PIPELINE_DEPTH => 1
 224             )
 225         port map (
 226             clk         => clk,
 227             rst         => rst,
 228
 229             complete_in => complete_in,
 230             valid_in    => control_valid_in,
 231             busy_in     => busy_in,
 232             deferred    => deferred,
 233             flush_in    => flush_in,
 234             sgl_pipe_in => control_sgl_pipe,
 235             stop_mark_in => d_in.stop_mark,
 236
 237             gpr_write_valid_in => gpr_write_valid,
 238             gpr_write_in       => gpr_write,
 239             gpr_bypassable     => gpr_bypassable,
 240
 241             update_gpr_write_valid => update_gpr_write_valid,
 242             update_gpr_write_reg => update_gpr_write_reg,
 243
 244             gpr_a_read_valid_in  => gpr_a_read_valid,
 245             gpr_a_read_in        => gpr_a_read,
 246
 247             gpr_b_read_valid_in  => gpr_b_read_valid,
 248             gpr_b_read_in        => gpr_b_read,
 249
 250             gpr_c_read_valid_in  => gpr_c_read_valid,
 251             gpr_c_read_in        => gpr_c_read,
 252
 253             cr_read_in           => d_in.decode.input_cr,
 254             cr_write_in          => cr_write_valid,
 255             cr_bypass            => cr_bypass,
 256             cr_bypassable        => cr_bypass_avail,
 257
 258             valid_out   => control_valid_out,
 259             stall_out   => stall_out,
 260             stopped_out => stopped_out,
 261
 262             gpr_bypass_a => gpr_a_bypass,
 263             gpr_bypass_b => gpr_b_bypass,
 264             gpr_bypass_c => gpr_c_bypass
 265             );
 266
 267     deferred <= r.e.valid and busy_in;
 268
 269     decode2_0: process(clk)
 270     begin
 271         if rising_edge(clk) then
 272             if rst = '1' or flush_in = '1' or deferred = '0' then
 273                 if rin.e.valid = '1' then
 274                     report "execute " & to_hstring(rin.e.nia);
 275                 end if;
 276                 r <= rin;
 277             end if;
 278         end if;
 279     end process;
 280
 281     r_out.read1_reg <= d_in.ispr1 when d_in.decode.input_reg_a = SPR
 282                        else gpr_to_gspr(insn_ra(d_in.insn));
 283     r_out.read2_reg <= d_in.ispr2 when d_in.decode.input_reg_b = SPR
 284                        else gpr_to_gspr(insn_rb(d_in.insn));
 285     r_out.read3_reg <= insn_rs(d_in.insn);
 286
 287     c_out.read <= d_in.decode.input_cr;
 288
 289     decode2_1: process(all)
 290         variable v : reg_type;
 291         variable mul_a : std_ulogic_vector(63 downto 0);
 292         variable mul_b : std_ulogic_vector(63 downto 0);
 293         variable decoded_reg_a : decode_input_reg_t;
 294         variable decoded_reg_b : decode_input_reg_t;
 295         variable decoded_reg_c : decode_input_reg_t;
 296         variable decoded_reg_o : decode_output_reg_t;
 297         variable length : std_ulogic_vector(3 downto 0);
 298     begin
 299         v := r;
 300
 301         v.e := Decode2ToExecute1Init;
 302
 303         mul_a := (others => '0');
 304         mul_b := (others => '0');
 305
 306         --v.e.input_cr := d_in.decode.input_cr;
 307         --v.e.output_cr := d_in.decode.output_cr;
 308
 309         decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
 310                                              d_in.nia);
 311         decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 312         decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 313         decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
 314
 315         r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
 316         r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
 317         r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
 318
 319         case d_in.decode.length is
 320             when is1B =>
 321                 length := "0001";
 322             when is2B =>
 323                 length := "0010";
 324             when is4B =>
 325                 length := "0100";
 326             when is8B =>
 327                 length := "1000";
 328             when NONE =>
 329                 length := "0000";
 330         end case;
 331
 332         -- execute unit
 333         v.e.nia := d_in.nia;
 334         v.e.unit := d_in.decode.unit;
 335         v.e.insn_type := d_in.decode.insn_type;
 336         v.e.read_reg1 := decoded_reg_a.reg;
 337         v.e.read_data1 := decoded_reg_a.data;
 338         v.e.bypass_data1 := gpr_a_bypass;
 339         v.e.read_reg2 := decoded_reg_b.reg;
 340         v.e.read_data2 := decoded_reg_b.data;
 341         v.e.bypass_data2 := gpr_b_bypass;
 342         v.e.read_data3 := decoded_reg_c.data;
 343         v.e.bypass_data3 := gpr_c_bypass;
 344         v.e.write_reg := decoded_reg_o.reg;
 345         v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 346         if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
 347             v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 348         end if;
 349         v.e.cr := c_in.read_cr_data;
 350         v.e.bypass_cr := cr_bypass;
 351         v.e.xerc := c_in.read_xerc_data;
 352         v.e.invert_a := d_in.decode.invert_a;
 353         v.e.invert_out := d_in.decode.invert_out;
 354         v.e.input_carry := d_in.decode.input_carry;
 355         v.e.output_carry := d_in.decode.output_carry;
 356         v.e.is_32bit := d_in.decode.is_32bit;
 357         v.e.is_signed := d_in.decode.is_signed;
 358         if d_in.decode.lr = '1' then
 359             v.e.lr := insn_lk(d_in.insn);
 360         end if;
 361         v.e.insn := d_in.insn;
 362         v.e.data_len := length;
 363         v.e.byte_reverse := d_in.decode.byte_reverse;
 364         v.e.sign_extend := d_in.decode.sign_extend;
 365         v.e.update := d_in.decode.update;
 366         v.e.reserve := d_in.decode.reserve;
 367         v.e.br_pred := d_in.br_pred;
 368
 369         -- issue control
 370         control_valid_in <= d_in.valid;
 371         control_sgl_pipe <= d_in.decode.sgl_pipe;
 372
 373         gpr_write_valid <= decoded_reg_o.reg_valid;
 374         gpr_write <= decoded_reg_o.reg;
 375         gpr_bypassable <= '0';
 376         if EX1_BYPASS and d_in.decode.unit = ALU then
 377             gpr_bypassable <= '1';
 378         end if;
 379         update_gpr_write_valid <= d_in.decode.update;
 380         update_gpr_write_reg <= decoded_reg_a.reg;
 381         if v.e.lr = '1' then
 382             -- there are no instructions that have both update=1 and lr=1
 383             update_gpr_write_valid <= '1';
 384             update_gpr_write_reg <= fast_spr_num(SPR_LR);
 385         end if;
 386
 387         gpr_a_read_valid <= decoded_reg_a.reg_valid;
 388         gpr_a_read <= decoded_reg_a.reg;
 389
 390         gpr_b_read_valid <= decoded_reg_b.reg_valid;
 391         gpr_b_read <= decoded_reg_b.reg;
 392
 393         gpr_c_read_valid <= decoded_reg_c.reg_valid;
 394         gpr_c_read <= gspr_to_gpr(decoded_reg_c.reg);
 395
 396         cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 397         cr_bypass_avail <= '0';
 398         if EX1_BYPASS then
 399             cr_bypass_avail <= d_in.decode.output_cr;
 400         end if;
 401
 402         v.e.valid := control_valid_out;
 403         if d_in.decode.unit = NONE then
 404             v.e.insn_type := OP_ILLEGAL;
 405         end if;
 406
 407         if rst = '1' or flush_in = '1' then
 408             v.e := Decode2ToExecute1Init;
 409         end if;
 410
 411         -- Update registers
 412         rin <= v;
 413
 414         -- Update outputs
 415         e_out <= r.e;
 416     end process;
 417
 418     dec2_log : process(clk)
 419     begin
 420         if rising_edge(clk) then
 421             log_data <= r.e.nia(5 downto 2) &
 422                         r.e.valid &
 423                         stopped_out &
 424                         stall_out &
 425                         r.e.bypass_data3 &
 426                         r.e.bypass_data2 &
 427                         r.e.bypass_data1;
 428         end if;
 429     end process;
 430     log_out <= log_data;
 431
 432 end architecture behaviour;