decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12     generic (
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         -- Non-zero to enable log data collection
  16         LOG_LENGTH : natural := 0
  17         );
  18     port (
  19         clk   : in std_ulogic;
  20         rst   : in std_ulogic;
  21
  22         complete_in : in std_ulogic;
  23         busy_in   : in std_ulogic;
  24         stall_out : out std_ulogic;
  25
  26         stopped_out : out std_ulogic;
  27
  28         flush_in: in std_ulogic;
  29
  30         d_in  : in Decode1ToDecode2Type;
  31
  32         e_out : out Decode2ToExecute1Type;
  33
  34         r_in  : in RegisterFileToDecode2Type;
  35         r_out : out Decode2ToRegisterFileType;
  36
  37         c_in  : in CrFileToDecode2Type;
  38         c_out : out Decode2ToCrFileType;
  39
  40         log_out : out std_ulogic_vector(9 downto 0)
  41         );
  42 end entity decode2;
  43
  44 architecture behaviour of decode2 is
  45     type reg_type is record
  46         e : Decode2ToExecute1Type;
  47     end record;
  48
  49     signal r, rin : reg_type;
  50
  51     signal deferred : std_ulogic;
  52
  53     type decode_input_reg_t is record
  54         reg_valid : std_ulogic;
  55         reg       : gspr_index_t;
  56         data      : std_ulogic_vector(63 downto 0);
  57     end record;
  58
  59     type decode_output_reg_t is record
  60         reg_valid : std_ulogic;
  61         reg       : gspr_index_t;
  62     end record;
  63
  64     function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  65                                  reg_data : std_ulogic_vector(63 downto 0);
  66                                  ispr : gspr_index_t;
  67                                  instr_addr : std_ulogic_vector(63 downto 0))
  68         return decode_input_reg_t is
  69     begin
  70         if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  71             return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  72         elsif t = SPR then
  73             -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  74             -- If it's all 0, we don't treat it as a dependency as slow SPRs
  75             -- operations are single issue.
  76             --
  77             assert is_fast_spr(ispr) =  '1' or ispr = "0000000"
  78                 report "Decode A says SPR but ISPR is invalid:" &
  79                 to_hstring(ispr) severity failure;
  80             return (is_fast_spr(ispr), ispr, reg_data);
  81         elsif t = CIA then
  82             return ('0', (others => '0'), instr_addr);
  83         else
  84             return ('0', (others => '0'), (others => '0'));
  85         end if;
  86     end;
  87
  88     function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  89                                  reg_data : std_ulogic_vector(63 downto 0);
  90                                  ispr : gspr_index_t) return decode_input_reg_t is
  91         variable ret : decode_input_reg_t;
  92     begin
  93         case t is
  94             when RB =>
  95                 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
  96             when FRB =>
  97                 if HAS_FPU then
  98                     ret := ('1', fpr_to_gspr(insn_frb(insn_in)), reg_data);
  99                 else
 100                     ret := ('0', (others => '0'), (others => '0'));
 101                 end if;
 102             when CONST_UI =>
 103                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
 104             when CONST_SI =>
 105                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
 106             when CONST_SI_HI =>
 107                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
 108             when CONST_UI_HI =>
 109                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
 110             when CONST_LI =>
 111                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
 112             when CONST_BD =>
 113                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 114             when CONST_DS =>
 115                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 116             when CONST_DXHI4 =>
 117                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
 118             when CONST_M1 =>
 119                 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 120             when CONST_SH =>
 121                 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 122             when CONST_SH32 =>
 123                 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 124             when SPR =>
 125                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 126                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 127                 -- operations are single issue.
 128                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 129                     report "Decode B says SPR but ISPR is invalid:" &
 130                     to_hstring(ispr) severity failure;
 131                 ret := (is_fast_spr(ispr), ispr, reg_data);
 132             when NONE =>
 133                 ret := ('0', (others => '0'), (others => '0'));
 134         end case;
 135
 136         return ret;
 137     end;
 138
 139     function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 140                                  reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 141     begin
 142         case t is
 143             when RS =>
 144                 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 145             when RCR =>
 146                 return ('1', gpr_to_gspr(insn_rcreg(insn_in)), reg_data);
 147             when FRS =>
 148                 if HAS_FPU then
 149                     return ('1', fpr_to_gspr(insn_frt(insn_in)), reg_data);
 150                 else
 151                     return ('0', (others => '0'), (others => '0'));
 152                 end if;
 153             when NONE =>
 154                 return ('0', (others => '0'), (others => '0'));
 155         end case;
 156     end;
 157
 158     function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 159                                 ispr : gspr_index_t) return decode_output_reg_t is
 160     begin
 161         case t is
 162             when RT =>
 163                 return ('1', gpr_to_gspr(insn_rt(insn_in)));
 164             when RA =>
 165                 return ('1', gpr_to_gspr(insn_ra(insn_in)));
 166             when FRT =>
 167                 if HAS_FPU then
 168                     return ('1', fpr_to_gspr(insn_frt(insn_in)));
 169                 else
 170                     return ('0', "0000000");
 171                 end if;
 172             when SPR =>
 173                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 174                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 175                 -- operations are single issue.
 176                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 177                     report "Decode B says SPR but ISPR is invalid:" &
 178                     to_hstring(ispr) severity failure;
 179                 return (is_fast_spr(ispr), ispr);
 180             when NONE =>
 181                 return ('0', "0000000");
 182         end case;
 183     end;
 184
 185     function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 186     begin
 187         case t is
 188             when RC =>
 189                 return insn_rc(insn_in);
 190             when ONE =>
 191                 return '1';
 192             when NONE =>
 193                 return '0';
 194         end case;
 195     end;
 196
 197     -- For now, use "rc" in the decode table to decide whether oe exists.
 198     -- This is not entirely correct architecturally: For mulhd and
 199     -- mulhdu, the OE field is reserved. It remains to be seen what an
 200     -- actual POWER9 does if we set it on those instructions, for now we
 201     -- test that further down when assigning to the multiplier oe input.
 202     --
 203     function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 204     begin
 205         case t is
 206             when RC =>
 207                 return insn_oe(insn_in);
 208             when OTHERS =>
 209                 return '0';
 210         end case;
 211     end;
 212
 213     -- issue control signals
 214     signal control_valid_in : std_ulogic;
 215     signal control_valid_out : std_ulogic;
 216     signal control_sgl_pipe : std_logic;
 217
 218     signal gpr_write_valid : std_ulogic;
 219     signal gpr_write : gspr_index_t;
 220     signal gpr_bypassable  : std_ulogic;
 221
 222     signal update_gpr_write_valid : std_ulogic;
 223     signal update_gpr_write_reg : gspr_index_t;
 224
 225     signal gpr_a_read_valid : std_ulogic;
 226     signal gpr_a_read :gspr_index_t;
 227     signal gpr_a_bypass : std_ulogic;
 228
 229     signal gpr_b_read_valid : std_ulogic;
 230     signal gpr_b_read : gspr_index_t;
 231     signal gpr_b_bypass : std_ulogic;
 232
 233     signal gpr_c_read_valid : std_ulogic;
 234     signal gpr_c_read : gspr_index_t;
 235     signal gpr_c_bypass : std_ulogic;
 236
 237     signal cr_write_valid  : std_ulogic;
 238     signal cr_bypass       : std_ulogic;
 239     signal cr_bypass_avail : std_ulogic;
 240
 241 begin
 242     control_0: entity work.control
 243         generic map (
 244             PIPELINE_DEPTH => 1
 245             )
 246         port map (
 247             clk         => clk,
 248             rst         => rst,
 249
 250             complete_in => complete_in,
 251             valid_in    => control_valid_in,
 252             busy_in     => busy_in,
 253             deferred    => deferred,
 254             flush_in    => flush_in,
 255             sgl_pipe_in => control_sgl_pipe,
 256             stop_mark_in => d_in.stop_mark,
 257
 258             gpr_write_valid_in => gpr_write_valid,
 259             gpr_write_in       => gpr_write,
 260             gpr_bypassable     => gpr_bypassable,
 261
 262             update_gpr_write_valid => update_gpr_write_valid,
 263             update_gpr_write_reg => update_gpr_write_reg,
 264
 265             gpr_a_read_valid_in  => gpr_a_read_valid,
 266             gpr_a_read_in        => gpr_a_read,
 267
 268             gpr_b_read_valid_in  => gpr_b_read_valid,
 269             gpr_b_read_in        => gpr_b_read,
 270
 271             gpr_c_read_valid_in  => gpr_c_read_valid,
 272             gpr_c_read_in        => gpr_c_read,
 273
 274             cr_read_in           => d_in.decode.input_cr,
 275             cr_write_in          => cr_write_valid,
 276             cr_bypass            => cr_bypass,
 277             cr_bypassable        => cr_bypass_avail,
 278
 279             valid_out   => control_valid_out,
 280             stall_out   => stall_out,
 281             stopped_out => stopped_out,
 282
 283             gpr_bypass_a => gpr_a_bypass,
 284             gpr_bypass_b => gpr_b_bypass,
 285             gpr_bypass_c => gpr_c_bypass
 286             );
 287
 288     deferred <= r.e.valid and busy_in;
 289
 290     decode2_0: process(clk)
 291     begin
 292         if rising_edge(clk) then
 293             if rst = '1' or flush_in = '1' or deferred = '0' then
 294                 if rin.e.valid = '1' then
 295                     report "execute " & to_hstring(rin.e.nia);
 296                 end if;
 297                 r <= rin;
 298             end if;
 299         end if;
 300     end process;
 301
 302     r_out.read1_reg <= d_in.ispr1 when d_in.decode.input_reg_a = SPR
 303                        else gpr_to_gspr(insn_ra(d_in.insn));
 304     r_out.read2_reg <= d_in.ispr2 when d_in.decode.input_reg_b = SPR
 305                        else fpr_to_gspr(insn_frb(d_in.insn)) when d_in.decode.input_reg_b = FRB and HAS_FPU
 306                        else gpr_to_gspr(insn_rb(d_in.insn));
 307     r_out.read3_reg <= gpr_to_gspr(insn_rcreg(d_in.insn)) when d_in.decode.input_reg_c = RCR
 308                        else fpr_to_gspr(insn_frt(d_in.insn)) when d_in.decode.input_reg_c = FRS and HAS_FPU
 309                        else gpr_to_gspr(insn_rs(d_in.insn));
 310
 311     c_out.read <= d_in.decode.input_cr;
 312
 313     decode2_1: process(all)
 314         variable v : reg_type;
 315         variable mul_a : std_ulogic_vector(63 downto 0);
 316         variable mul_b : std_ulogic_vector(63 downto 0);
 317         variable decoded_reg_a : decode_input_reg_t;
 318         variable decoded_reg_b : decode_input_reg_t;
 319         variable decoded_reg_c : decode_input_reg_t;
 320         variable decoded_reg_o : decode_output_reg_t;
 321         variable length : std_ulogic_vector(3 downto 0);
 322     begin
 323         v := r;
 324
 325         v.e := Decode2ToExecute1Init;
 326
 327         mul_a := (others => '0');
 328         mul_b := (others => '0');
 329
 330         --v.e.input_cr := d_in.decode.input_cr;
 331         v.e.output_cr := d_in.decode.output_cr;
 332
 333         decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
 334                                              d_in.nia);
 335         decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 336         decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 337         decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
 338
 339         r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
 340         r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
 341         r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
 342
 343         case d_in.decode.length is
 344             when is1B =>
 345                 length := "0001";
 346             when is2B =>
 347                 length := "0010";
 348             when is4B =>
 349                 length := "0100";
 350             when is8B =>
 351                 length := "1000";
 352             when NONE =>
 353                 length := "0000";
 354         end case;
 355
 356         -- execute unit
 357         v.e.nia := d_in.nia;
 358         v.e.unit := d_in.decode.unit;
 359         v.e.insn_type := d_in.decode.insn_type;
 360         v.e.read_reg1 := decoded_reg_a.reg;
 361         v.e.read_data1 := decoded_reg_a.data;
 362         v.e.bypass_data1 := gpr_a_bypass;
 363         v.e.read_reg2 := decoded_reg_b.reg;
 364         v.e.read_data2 := decoded_reg_b.data;
 365         v.e.bypass_data2 := gpr_b_bypass;
 366         v.e.read_data3 := decoded_reg_c.data;
 367         v.e.bypass_data3 := gpr_c_bypass;
 368         v.e.write_reg := decoded_reg_o.reg;
 369         v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 370         if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
 371             v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 372         end if;
 373         v.e.cr := c_in.read_cr_data;
 374         v.e.bypass_cr := cr_bypass;
 375         v.e.xerc := c_in.read_xerc_data;
 376         v.e.invert_a := d_in.decode.invert_a;
 377         v.e.invert_out := d_in.decode.invert_out;
 378         v.e.input_carry := d_in.decode.input_carry;
 379         v.e.output_carry := d_in.decode.output_carry;
 380         v.e.is_32bit := d_in.decode.is_32bit;
 381         v.e.is_signed := d_in.decode.is_signed;
 382         if d_in.decode.lr = '1' then
 383             v.e.lr := insn_lk(d_in.insn);
 384         end if;
 385         v.e.insn := d_in.insn;
 386         v.e.data_len := length;
 387         v.e.byte_reverse := d_in.decode.byte_reverse;
 388         v.e.sign_extend := d_in.decode.sign_extend;
 389         v.e.update := d_in.decode.update;
 390         v.e.reserve := d_in.decode.reserve;
 391         v.e.br_pred := d_in.br_pred;
 392
 393         -- issue control
 394         control_valid_in <= d_in.valid;
 395         control_sgl_pipe <= d_in.decode.sgl_pipe;
 396
 397         gpr_write_valid <= decoded_reg_o.reg_valid;
 398         gpr_write <= decoded_reg_o.reg;
 399         gpr_bypassable <= '0';
 400         if EX1_BYPASS and d_in.decode.unit = ALU then
 401             gpr_bypassable <= '1';
 402         end if;
 403         update_gpr_write_valid <= d_in.decode.update;
 404         update_gpr_write_reg <= decoded_reg_a.reg;
 405         if v.e.lr = '1' then
 406             -- there are no instructions that have both update=1 and lr=1
 407             update_gpr_write_valid <= '1';
 408             update_gpr_write_reg <= fast_spr_num(SPR_LR);
 409         end if;
 410
 411         gpr_a_read_valid <= decoded_reg_a.reg_valid;
 412         gpr_a_read <= decoded_reg_a.reg;
 413
 414         gpr_b_read_valid <= decoded_reg_b.reg_valid;
 415         gpr_b_read <= decoded_reg_b.reg;
 416
 417         gpr_c_read_valid <= decoded_reg_c.reg_valid;
 418         gpr_c_read <= decoded_reg_c.reg;
 419
 420         cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 421         cr_bypass_avail <= '0';
 422         if EX1_BYPASS and d_in.decode.unit = ALU then
 423             cr_bypass_avail <= d_in.decode.output_cr;
 424         end if;
 425
 426         v.e.valid := control_valid_out;
 427
 428         if rst = '1' or flush_in = '1' then
 429             v.e := Decode2ToExecute1Init;
 430         end if;
 431
 432         -- Update registers
 433         rin <= v;
 434
 435         -- Update outputs
 436         e_out <= r.e;
 437     end process;
 438
 439     d2_log: if LOG_LENGTH > 0 generate
 440         signal log_data : std_ulogic_vector(9 downto 0);
 441     begin
 442         dec2_log : process(clk)
 443         begin
 444             if rising_edge(clk) then
 445                 log_data <= r.e.nia(5 downto 2) &
 446                             r.e.valid &
 447                             stopped_out &
 448                             stall_out &
 449                             r.e.bypass_data3 &
 450                             r.e.bypass_data2 &
 451                             r.e.bypass_data1;
 452             end if;
 453         end process;
 454         log_out <= log_data;
 455     end generate;
 456
 457 end architecture behaviour;