decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12         port (
  13                 clk   : in std_ulogic;
  14                 rst   : in std_ulogic;
  15
  16                 complete_in : in std_ulogic;
  17                 stall_out : out std_ulogic;
  18
  19                 stopped_out : out std_ulogic;
  20
  21                 flush_in: in std_ulogic;
  22
  23                 d_in  : in Decode1ToDecode2Type;
  24
  25                 e_out : out Decode2ToExecute1Type;
  26                 m_out : out Decode2ToMultiplyType;
  27                 d_out : out Decode2ToDividerType;
  28                 l_out : out Decode2ToLoadstore1Type;
  29
  30                 r_in  : in RegisterFileToDecode2Type;
  31                 r_out : out Decode2ToRegisterFileType;
  32
  33                 c_in  : in CrFileToDecode2Type;
  34                 c_out : out Decode2ToCrFileType
  35         );
  36 end entity decode2;
  37
  38 architecture behaviour of decode2 is
  39         type state_type is (IDLE, WAIT_FOR_PREV_TO_COMPLETE, WAIT_FOR_CURR_TO_COMPLETE);
  40
  41         type reg_internal_type is record
  42                 state : state_type;
  43                 outstanding : integer;
  44         end record;
  45
  46         type reg_type is record
  47                 e : Decode2ToExecute1Type;
  48                 m : Decode2ToMultiplyType;
  49                 d : Decode2ToDividerType;
  50                 l : Decode2ToLoadstore1Type;
  51         end record;
  52
  53         signal r_int, rin_int : reg_internal_type;
  54         signal r, rin : reg_type;
  55
  56         type decode_input_reg_t is record
  57                 reg_valid : std_ulogic;
  58                 reg       : std_ulogic_vector(4 downto 0);
  59                 data      : std_ulogic_vector(63 downto 0);
  60         end record;
  61
  62         function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  63                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  64         begin
  65                 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  66                         return ('1', insn_ra(insn_in), reg_data);
  67                 else
  68                         return ('0', (others => '0'), (others => '0'));
  69                 end if;
  70         end;
  71
  72         function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  73                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  74         begin
  75                 case t is
  76                 when RB =>
  77                         return ('1', insn_rb(insn_in), reg_data);
  78                 when CONST_UI =>
  79                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  80                 when CONST_SI =>
  81                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  82                 when CONST_SI_HI =>
  83                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
  84                 when CONST_UI_HI =>
  85                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
  86                 when CONST_LI =>
  87                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
  88                 when CONST_BD =>
  89                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
  90                 when CONST_DS =>
  91                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
  92                 when CONST_M1 =>
  93                         return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
  94                 when NONE =>
  95                         return ('0', (others => '0'), (others => '0'));
  96                 end case;
  97         end;
  98
  99         function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 100                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 101         begin
 102                 case t is
 103                 when RS =>
 104                         return ('1', insn_rs(insn_in), reg_data);
 105                 when NONE =>
 106                         return ('0', (others => '0'), (others => '0'));
 107                 end case;
 108         end;
 109
 110         function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 111         begin
 112                 case t is
 113                 when RT =>
 114                         return insn_rt(insn_in);
 115                 when RA =>
 116                         return insn_ra(insn_in);
 117                 when NONE =>
 118                         return "00000";
 119                 end case;
 120         end;
 121
 122         function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 123         begin
 124                 case t is
 125                 when RC =>
 126                         return insn_rc(insn_in);
 127                 when ONE =>
 128                         return '1';
 129                 when NONE =>
 130                         return '0';
 131                 end case;
 132         end;
 133 begin
 134
 135         decode2_0: process(clk)
 136         begin
 137                 if rising_edge(clk) then
 138                         assert r_int.outstanding <= 1 report "Outstanding bad " & integer'image(r_int.outstanding) severity failure;
 139
 140                         if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' or rin.d.valid = '1' then
 141                                 report "execute " & to_hstring(rin.e.nia);
 142                         end if;
 143                         r <= rin;
 144                         r_int <= rin_int;
 145                 end if;
 146         end process;
 147
 148         r_out.read1_reg <= insn_ra(d_in.insn);
 149         r_out.read2_reg <= insn_rb(d_in.insn);
 150         r_out.read3_reg <= insn_rs(d_in.insn);
 151
 152         c_out.read <= d_in.decode.input_cr;
 153
 154         decode2_1: process(all)
 155                 variable v : reg_type;
 156                 variable v_int : reg_internal_type;
 157                 variable mul_a : std_ulogic_vector(63 downto 0);
 158                 variable mul_b : std_ulogic_vector(63 downto 0);
 159                 variable decoded_reg_a : decode_input_reg_t;
 160                 variable decoded_reg_b : decode_input_reg_t;
 161                 variable decoded_reg_c : decode_input_reg_t;
 162                 variable signed_division: std_ulogic;
 163                 variable is_valid : std_ulogic;
 164         begin
 165                 v := r;
 166                 v_int := r_int;
 167
 168                 v.e := Decode2ToExecute1Init;
 169                 v.l := Decode2ToLoadStore1Init;
 170                 v.m := Decode2ToMultiplyInit;
 171                 v.d := Decode2ToDividerInit;
 172
 173                 mul_a := (others => '0');
 174                 mul_b := (others => '0');
 175
 176                 --v.e.input_cr := d_in.decode.input_cr;
 177                 --v.m.input_cr := d_in.decode.input_cr;
 178                 --v.e.output_cr := d_in.decode.output_cr;
 179
 180                 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data);
 181                 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data);
 182                 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 183
 184                 r_out.read1_enable <= decoded_reg_a.reg_valid;
 185                 r_out.read2_enable <= decoded_reg_b.reg_valid;
 186                 r_out.read3_enable <= decoded_reg_c.reg_valid;
 187
 188                 -- execute unit
 189                 v.e.nia := d_in.nia;
 190                 v.e.insn_type := d_in.decode.insn_type;
 191                 v.e.read_reg1 := decoded_reg_a.reg;
 192                 v.e.read_data1 := decoded_reg_a.data;
 193                 v.e.read_reg2 := decoded_reg_b.reg;
 194                 v.e.read_data2 := decoded_reg_b.data;
 195                 v.e.read_data3 := decoded_reg_c.data;
 196                 v.e.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 197                 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 198                 v.e.cr := c_in.read_cr_data;
 199                 v.e.invert_a := d_in.decode.invert_a;
 200                 v.e.input_carry := d_in.decode.input_carry;
 201                 v.e.output_carry := d_in.decode.output_carry;
 202                 v.e.is_32bit := d_in.decode.is_32bit;
 203                 v.e.is_signed := d_in.decode.is_signed;
 204                 if d_in.decode.lr = '1' then
 205                         v.e.lr := insn_lk(d_in.insn);
 206                 end if;
 207                 v.e.insn := d_in.insn;
 208
 209                 -- multiply unit
 210                 v.m.insn_type := d_in.decode.insn_type;
 211                 mul_a := decoded_reg_a.data;
 212                 mul_b := decoded_reg_b.data;
 213                 v.m.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 214                 v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
 215
 216                 if d_in.decode.is_32bit = '1' then
 217                         if d_in.decode.is_signed = '1' then
 218                                 v.m.data1 := (others => mul_a(31));
 219                                 v.m.data1(31 downto 0) := mul_a(31 downto 0);
 220                                 v.m.data2 := (others => mul_b(31));
 221                                 v.m.data2(31 downto 0) := mul_b(31 downto 0);
 222                         else
 223                                 v.m.data1 := '0' & x"00000000" & mul_a(31 downto 0);
 224                                 v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
 225                         end if;
 226                 else
 227                         if d_in.decode.is_signed = '1' then
 228                                 v.m.data1 := mul_a(63) & mul_a;
 229                                 v.m.data2 := mul_b(63) & mul_b;
 230                         else
 231                                 v.m.data1 := '0' & mul_a;
 232                                 v.m.data2 := '0' & mul_b;
 233                         end if;
 234                 end if;
 235
 236                 -- divide unit
 237                 -- PPC divide and modulus instruction words have these bits in
 238                 -- the bottom 11 bits: o1dns 010t1 r
 239                 -- where o = OE for div instrs, signedness for mod instrs
 240                 --       d = 1 for div*, 0 for mod*
 241                 --       n = 1 for normal, 0 for extended (dividend << 32/64)
 242                 --       s = 1 for signed, 0 for unsigned (for div*)
 243                 --       t = 1 for 32-bit, 0 for 64-bit
 244                 --       r = RC bit (record condition code)
 245                 v.d.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 246                 v.d.is_modulus := not d_in.insn(8);
 247                 v.d.is_32bit := not d_in.insn(2);
 248                 if d_in.insn(8) = '1' then
 249                         signed_division := d_in.insn(6);
 250                 else
 251                         signed_division := d_in.insn(10);
 252                 end if;
 253                 v.d.is_signed := signed_division;
 254                 if d_in.insn(2) = '0' then
 255                         -- 64-bit forms
 256                         if d_in.insn(8) = '1' and d_in.insn(7) = '0' then
 257                                 v.d.is_extended := '1';
 258                         end if;
 259                         v.d.dividend := decoded_reg_a.data;
 260                         v.d.divisor := decoded_reg_b.data;
 261                 else
 262                         -- 32-bit forms
 263                         if d_in.insn(8) = '1' and d_in.insn(7) = '0' then   -- extended forms
 264                                 v.d.dividend := decoded_reg_a.data(31 downto 0) & x"00000000";
 265                         elsif signed_division = '1' and decoded_reg_a.data(31) = '1' then
 266                                 -- sign extend to 64 bits
 267                                 v.d.dividend := x"ffffffff" & decoded_reg_a.data(31 downto 0);
 268                         else
 269                                 v.d.dividend := x"00000000" & decoded_reg_a.data(31 downto 0);
 270                         end if;
 271                         if signed_division = '1' and decoded_reg_b.data(31) = '1' then
 272                                 v.d.divisor := x"ffffffff" & decoded_reg_b.data(31 downto 0);
 273                         else
 274                                 v.d.divisor := x"00000000" & decoded_reg_b.data(31 downto 0);
 275                         end if;
 276                 end if;
 277                 v.d.rc := decode_rc(d_in.decode.rc, d_in.insn);
 278
 279                 -- load/store unit
 280                 v.l.update_reg := decoded_reg_a.reg;
 281                 v.l.addr1 := decoded_reg_a.data;
 282                 v.l.addr2 := decoded_reg_b.data;
 283                 v.l.data := decoded_reg_c.data;
 284                 v.l.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 285
 286                 if d_in.decode.insn_type = OP_LOAD then
 287                         v.l.load := '1';
 288                 else
 289                         v.l.load := '0';
 290                 end if;
 291
 292                 case d_in.decode.length is
 293                 when is1B =>
 294                         v.l.length := "0001";
 295                 when is2B =>
 296                         v.l.length := "0010";
 297                 when is4B =>
 298                         v.l.length := "0100";
 299                 when is8B =>
 300                         v.l.length := "1000";
 301                 when NONE =>
 302                         v.l.length := "0000";
 303                 end case;
 304
 305                 v.l.byte_reverse := d_in.decode.byte_reverse;
 306                 v.l.sign_extend := d_in.decode.sign_extend;
 307                 v.l.update := d_in.decode.update;
 308
 309                 -- single issue
 310
 311                 if complete_in = '1' then
 312                         v_int.outstanding := v_int.outstanding - 1;
 313                 end if;
 314
 315                 -- state machine to handle instructions that must be single
 316                 -- through the pipeline.
 317                 stall_out <= '0';
 318                 is_valid := d_in.valid;
 319
 320                 -- Handle debugger stop
 321                 stopped_out <= '0';
 322                 if d_in.stop_mark = '1' and v_int.outstanding = 0 then
 323                     stopped_out <= '1';
 324                 end if;
 325
 326                 case v_int.state is
 327                 when IDLE =>
 328                         if (flush_in = '0') and (is_valid = '1') and (d_in.decode.sgl_pipe = '1') then
 329                                 if v_int.outstanding /= 0 then
 330                                         v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
 331                                         stall_out <= '1';
 332                                         is_valid := '0';
 333                                 else
 334                                         -- send insn out and wait on it to complete
 335                                         v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
 336                                 end if;
 337                         end if;
 338
 339                 when WAIT_FOR_PREV_TO_COMPLETE =>
 340                         if v_int.outstanding = 0 then
 341                                 -- send insn out and wait on it to complete
 342                                 v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
 343                         else
 344                                 stall_out <= '1';
 345                                 is_valid := '0';
 346                         end if;
 347
 348                 when WAIT_FOR_CURR_TO_COMPLETE =>
 349                         if v_int.outstanding = 0 then
 350                                 v_int.state := IDLE;
 351                         else
 352                                 stall_out <= '1';
 353                                 is_valid := '0';
 354                         end if;
 355                 end case;
 356
 357                 v.e.valid := '0';
 358                 v.m.valid := '0';
 359                 v.d.valid := '0';
 360                 v.l.valid := '0';
 361                 case d_in.decode.unit is
 362                 when ALU =>
 363                         v.e.valid := is_valid;
 364                 when LDST =>
 365                         v.l.valid := is_valid;
 366                 when MUL =>
 367                         v.m.valid := is_valid;
 368                 when DIV =>
 369                         v.d.valid := is_valid;
 370                 when NONE =>
 371                         v.e.valid := is_valid;
 372                         v.e.insn_type := OP_ILLEGAL;
 373                 end case;
 374
 375                 if flush_in = '1' then
 376                         v.e.valid := '0';
 377                         v.m.valid := '0';
 378                         v.d.valid := '0';
 379                         v.l.valid := '0';
 380                 end if;
 381
 382                 -- track outstanding instructions
 383                 if v.e.valid = '1' or v.l.valid = '1' or v.m.valid = '1' or v.d.valid = '1' then
 384                         v_int.outstanding := v_int.outstanding + 1;
 385                 end if;
 386
 387                 if rst = '1' then
 388                         v_int.state := IDLE;
 389                         v_int.outstanding := 0;
 390                         v.e := Decode2ToExecute1Init;
 391                         v.l := Decode2ToLoadStore1Init;
 392                         v.m := Decode2ToMultiplyInit;
 393                         v.d := Decode2ToDividerInit;
 394                 end if;
 395
 396                 -- Update registers
 397                 rin <= v;
 398                 rin_int <= v_int;
 399
 400                 -- Update outputs
 401                 e_out <= r.e;
 402                 l_out <= r.l;
 403                 m_out <= r.m;
 404                 d_out <= r.d;
 405         end process;
 406 end architecture behaviour;