decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12     generic (
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         -- Non-zero to enable log data collection
  16         LOG_LENGTH : natural := 0
  17         );
  18     port (
  19         clk   : in std_ulogic;
  20         rst   : in std_ulogic;
  21
  22         complete_in : in std_ulogic;
  23         busy_in   : in std_ulogic;
  24         stall_out : out std_ulogic;
  25
  26         stopped_out : out std_ulogic;
  27
  28         flush_in: in std_ulogic;
  29
  30         d_in  : in Decode1ToDecode2Type;
  31
  32         e_out : out Decode2ToExecute1Type;
  33
  34         r_in  : in RegisterFileToDecode2Type;
  35         r_out : out Decode2ToRegisterFileType;
  36
  37         c_in  : in CrFileToDecode2Type;
  38         c_out : out Decode2ToCrFileType;
  39
  40         log_out : out std_ulogic_vector(9 downto 0)
  41         );
  42 end entity decode2;
  43
  44 architecture behaviour of decode2 is
  45     type reg_type is record
  46         e : Decode2ToExecute1Type;
  47         repeat : std_ulogic;
  48     end record;
  49
  50     signal r, rin : reg_type;
  51
  52     signal deferred : std_ulogic;
  53
  54     type decode_input_reg_t is record
  55         reg_valid : std_ulogic;
  56         reg       : gspr_index_t;
  57         data      : std_ulogic_vector(63 downto 0);
  58     end record;
  59
  60     type decode_output_reg_t is record
  61         reg_valid : std_ulogic;
  62         reg       : gspr_index_t;
  63     end record;
  64
  65     function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  66                                  reg_data : std_ulogic_vector(63 downto 0);
  67                                  ispr : gspr_index_t;
  68                                  instr_addr : std_ulogic_vector(63 downto 0))
  69         return decode_input_reg_t is
  70     begin
  71         if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  72             return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  73         elsif t = SPR then
  74             -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  75             -- If it's all 0, we don't treat it as a dependency as slow SPRs
  76             -- operations are single issue.
  77             --
  78             assert is_fast_spr(ispr) =  '1' or ispr = "0000000"
  79                 report "Decode A says SPR but ISPR is invalid:" &
  80                 to_hstring(ispr) severity failure;
  81             return (is_fast_spr(ispr), ispr, reg_data);
  82         elsif t = CIA then
  83             return ('0', (others => '0'), instr_addr);
  84         elsif HAS_FPU and t = FRA then
  85             return ('1', fpr_to_gspr(insn_fra(insn_in)), reg_data);
  86         else
  87             return ('0', (others => '0'), (others => '0'));
  88         end if;
  89     end;
  90
  91     function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  92                                  reg_data : std_ulogic_vector(63 downto 0);
  93                                  ispr : gspr_index_t) return decode_input_reg_t is
  94         variable ret : decode_input_reg_t;
  95     begin
  96         case t is
  97             when RB =>
  98                 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
  99             when FRB =>
 100                 if HAS_FPU then
 101                     ret := ('1', fpr_to_gspr(insn_frb(insn_in)), reg_data);
 102                 else
 103                     ret := ('0', (others => '0'), (others => '0'));
 104                 end if;
 105             when CONST_UI =>
 106                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
 107             when CONST_SI =>
 108                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
 109             when CONST_SI_HI =>
 110                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
 111             when CONST_UI_HI =>
 112                 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
 113             when CONST_LI =>
 114                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
 115             when CONST_BD =>
 116                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 117             when CONST_DS =>
 118                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 119             when CONST_DQ =>
 120                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dq(insn_in)) & "0000", 64)));
 121             when CONST_DXHI4 =>
 122                 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
 123             when CONST_M1 =>
 124                 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 125             when CONST_SH =>
 126                 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 127             when CONST_SH32 =>
 128                 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 129             when SPR =>
 130                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 131                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 132                 -- operations are single issue.
 133                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 134                     report "Decode B says SPR but ISPR is invalid:" &
 135                     to_hstring(ispr) severity failure;
 136                 ret := (is_fast_spr(ispr), ispr, reg_data);
 137             when NONE =>
 138                 ret := ('0', (others => '0'), (others => '0'));
 139         end case;
 140
 141         return ret;
 142     end;
 143
 144     function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 145                                  reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 146     begin
 147         case t is
 148             when RS =>
 149                 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 150             when RCR =>
 151                 return ('1', gpr_to_gspr(insn_rcreg(insn_in)), reg_data);
 152             when FRS =>
 153                 if HAS_FPU then
 154                     return ('1', fpr_to_gspr(insn_frt(insn_in)), reg_data);
 155                 else
 156                     return ('0', (others => '0'), (others => '0'));
 157                 end if;
 158             when FRC =>
 159                 if HAS_FPU then
 160                     return ('1', fpr_to_gspr(insn_frc(insn_in)), reg_data);
 161                 else
 162                     return ('0', (others => '0'), (others => '0'));
 163                 end if;
 164             when NONE =>
 165                 return ('0', (others => '0'), (others => '0'));
 166         end case;
 167     end;
 168
 169     function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 170                                 ispr : gspr_index_t) return decode_output_reg_t is
 171     begin
 172         case t is
 173             when RT =>
 174                 return ('1', gpr_to_gspr(insn_rt(insn_in)));
 175             when RA =>
 176                 return ('1', gpr_to_gspr(insn_ra(insn_in)));
 177             when FRT =>
 178                 if HAS_FPU then
 179                     return ('1', fpr_to_gspr(insn_frt(insn_in)));
 180                 else
 181                     return ('0', "0000000");
 182                 end if;
 183             when SPR =>
 184                 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 185                 -- If it's all 0, we don't treat it as a dependency as slow SPRs
 186                 -- operations are single issue.
 187                 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
 188                     report "Decode B says SPR but ISPR is invalid:" &
 189                     to_hstring(ispr) severity failure;
 190                 return (is_fast_spr(ispr), ispr);
 191             when NONE =>
 192                 return ('0', "0000000");
 193         end case;
 194     end;
 195
 196     function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 197     begin
 198         case t is
 199             when RC =>
 200                 return insn_rc(insn_in);
 201             when ONE =>
 202                 return '1';
 203             when NONE =>
 204                 return '0';
 205         end case;
 206     end;
 207
 208     -- For now, use "rc" in the decode table to decide whether oe exists.
 209     -- This is not entirely correct architecturally: For mulhd and
 210     -- mulhdu, the OE field is reserved. It remains to be seen what an
 211     -- actual POWER9 does if we set it on those instructions, for now we
 212     -- test that further down when assigning to the multiplier oe input.
 213     --
 214     function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 215     begin
 216         case t is
 217             when RC =>
 218                 return insn_oe(insn_in);
 219             when OTHERS =>
 220                 return '0';
 221         end case;
 222     end;
 223
 224     -- control signals that are derived from insn_type
 225     type mux_select_array_t is array(insn_type_t) of std_ulogic_vector(2 downto 0);
 226
 227     constant result_select : mux_select_array_t := (
 228         OP_AND      => "001",           -- logical_result
 229         OP_OR       => "001",
 230         OP_XOR      => "001",
 231         OP_POPCNT   => "001",
 232         OP_PRTY     => "001",
 233         OP_CMPB     => "001",
 234         OP_EXTS     => "001",
 235         OP_BPERM    => "001",
 236         OP_BCD      => "001",
 237         OP_MTSPR    => "001",
 238         OP_RLC      => "010",           -- rotator_result
 239         OP_RLCL     => "010",
 240         OP_RLCR     => "010",
 241         OP_SHL      => "010",
 242         OP_SHR      => "010",
 243         OP_EXTSWSLI => "010",
 244         OP_MUL_L64  => "011",           -- muldiv_result
 245         OP_MUL_H64  => "011",
 246         OP_MUL_H32  => "011",
 247         OP_DIV      => "011",
 248         OP_DIVE     => "011",
 249         OP_MOD      => "011",
 250         OP_CNTZ     => "100",           -- countzero_result
 251         OP_MFSPR    => "101",           -- spr_result
 252         OP_B        => "110",           -- next_nia
 253         OP_BC       => "110",
 254         OP_BCREG    => "110",
 255         OP_ADDG6S   => "111",           -- misc_result
 256         OP_ISEL     => "111",
 257         OP_DARN     => "111",
 258         OP_MFMSR    => "111",
 259         OP_MFCR     => "111",
 260         OP_SETB     => "111",
 261         others      => "000"            -- default to adder_result
 262         );
 263
 264     constant subresult_select : mux_select_array_t := (
 265         OP_MUL_L64 => "000",            -- muldiv_result
 266         OP_MUL_H64 => "001",
 267         OP_MUL_H32 => "010",
 268         OP_DIV     => "011",
 269         OP_DIVE    => "011",
 270         OP_MOD     => "011",
 271         OP_ADDG6S  => "001",            -- misc_result
 272         OP_ISEL    => "010",
 273         OP_DARN    => "011",
 274         OP_MFMSR   => "100",
 275         OP_MFCR    => "101",
 276         OP_SETB    => "110",
 277         others     => "000"
 278         );
 279
 280     -- issue control signals
 281     signal control_valid_in : std_ulogic;
 282     signal control_valid_out : std_ulogic;
 283     signal control_stall_out : std_ulogic;
 284     signal control_sgl_pipe : std_logic;
 285
 286     signal gpr_write_valid : std_ulogic;
 287     signal gpr_write : gspr_index_t;
 288     signal gpr_bypassable  : std_ulogic;
 289
 290     signal gpr_a_read_valid : std_ulogic;
 291     signal gpr_a_read :gspr_index_t;
 292     signal gpr_a_bypass : std_ulogic;
 293
 294     signal gpr_b_read_valid : std_ulogic;
 295     signal gpr_b_read : gspr_index_t;
 296     signal gpr_b_bypass : std_ulogic;
 297
 298     signal gpr_c_read_valid : std_ulogic;
 299     signal gpr_c_read : gspr_index_t;
 300     signal gpr_c_bypass : std_ulogic;
 301
 302     signal cr_write_valid  : std_ulogic;
 303     signal cr_bypass       : std_ulogic;
 304     signal cr_bypass_avail : std_ulogic;
 305
 306 begin
 307     control_0: entity work.control
 308         generic map (
 309             PIPELINE_DEPTH => 1
 310             )
 311         port map (
 312             clk         => clk,
 313             rst         => rst,
 314
 315             complete_in => complete_in,
 316             valid_in    => control_valid_in,
 317             repeated    => r.repeat,
 318             busy_in     => busy_in,
 319             deferred    => deferred,
 320             flush_in    => flush_in,
 321             sgl_pipe_in => control_sgl_pipe,
 322             stop_mark_in => d_in.stop_mark,
 323
 324             gpr_write_valid_in => gpr_write_valid,
 325             gpr_write_in       => gpr_write,
 326             gpr_bypassable     => gpr_bypassable,
 327
 328             update_gpr_write_valid => '0',
 329             update_gpr_write_reg => 7x"00",
 330
 331             gpr_a_read_valid_in  => gpr_a_read_valid,
 332             gpr_a_read_in        => gpr_a_read,
 333
 334             gpr_b_read_valid_in  => gpr_b_read_valid,
 335             gpr_b_read_in        => gpr_b_read,
 336
 337             gpr_c_read_valid_in  => gpr_c_read_valid,
 338             gpr_c_read_in        => gpr_c_read,
 339
 340             cr_read_in           => d_in.decode.input_cr,
 341             cr_write_in          => cr_write_valid,
 342             cr_bypass            => cr_bypass,
 343             cr_bypassable        => cr_bypass_avail,
 344
 345             valid_out   => control_valid_out,
 346             stall_out   => control_stall_out,
 347             stopped_out => stopped_out,
 348
 349             gpr_bypass_a => gpr_a_bypass,
 350             gpr_bypass_b => gpr_b_bypass,
 351             gpr_bypass_c => gpr_c_bypass
 352             );
 353
 354     deferred <= r.e.valid and busy_in;
 355
 356     decode2_0: process(clk)
 357     begin
 358         if rising_edge(clk) then
 359             if rst = '1' or flush_in = '1' or deferred = '0' then
 360                 if rin.e.valid = '1' then
 361                     report "execute " & to_hstring(rin.e.nia);
 362                 end if;
 363                 r <= rin;
 364             end if;
 365         end if;
 366     end process;
 367
 368     c_out.read <= d_in.decode.input_cr;
 369
 370     decode2_1: process(all)
 371         variable v : reg_type;
 372         variable mul_a : std_ulogic_vector(63 downto 0);
 373         variable mul_b : std_ulogic_vector(63 downto 0);
 374         variable decoded_reg_a : decode_input_reg_t;
 375         variable decoded_reg_b : decode_input_reg_t;
 376         variable decoded_reg_c : decode_input_reg_t;
 377         variable decoded_reg_o : decode_output_reg_t;
 378         variable length : std_ulogic_vector(3 downto 0);
 379         variable op : insn_type_t;
 380     begin
 381         v := r;
 382
 383         v.e := Decode2ToExecute1Init;
 384
 385         mul_a := (others => '0');
 386         mul_b := (others => '0');
 387
 388         --v.e.input_cr := d_in.decode.input_cr;
 389         v.e.output_cr := d_in.decode.output_cr;
 390
 391         decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
 392                                              d_in.nia);
 393         decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 394         decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 395         decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispro);
 396
 397         if d_in.decode.lr = '1' then
 398             v.e.lr := insn_lk(d_in.insn);
 399             -- b and bc have even major opcodes; bcreg is considered absolute
 400             v.e.br_abs := insn_aa(d_in.insn) or d_in.insn(26);
 401         end if;
 402         op := d_in.decode.insn_type;
 403
 404         if d_in.decode.repeat /= NONE then
 405             v.e.repeat := '1';
 406             v.e.second := r.repeat;
 407             case d_in.decode.repeat is
 408                 when DRSE =>
 409                     -- do RS|1,RS for LE; RS,RS|1 for BE
 410                     if r.repeat = d_in.big_endian then
 411                         decoded_reg_c.reg(0) := '1';
 412                     end if;
 413                 when DRTE =>
 414                     -- do RT|1,RT for LE; RT,RT|1 for BE
 415                     if r.repeat = d_in.big_endian then
 416                         decoded_reg_o.reg(0) := '1';
 417                     end if;
 418                 when DUPD =>
 419                     -- update-form loads, 2nd instruction writes RA
 420                     if r.repeat = '1' then
 421                         decoded_reg_o.reg := decoded_reg_a.reg;
 422                     end if;
 423                 when others =>
 424             end case;
 425         elsif v.e.lr = '1' and decoded_reg_a.reg_valid = '1' then
 426             -- bcl/bclrl/bctarl that needs to write both CTR and LR has to be doubled
 427             v.e.repeat := '1';
 428             v.e.second := r.repeat;
 429             -- first one does CTR, second does LR
 430             decoded_reg_o.reg(0) := not r.repeat;
 431         end if;
 432
 433         r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
 434         r_out.read1_reg    <= decoded_reg_a.reg;
 435         r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
 436         r_out.read2_reg    <= decoded_reg_b.reg;
 437         r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
 438         r_out.read3_reg    <= decoded_reg_c.reg;
 439
 440         case d_in.decode.length is
 441             when is1B =>
 442                 length := "0001";
 443             when is2B =>
 444                 length := "0010";
 445             when is4B =>
 446                 length := "0100";
 447             when is8B =>
 448                 length := "1000";
 449             when NONE =>
 450                 length := "0000";
 451         end case;
 452
 453         -- execute unit
 454         v.e.nia := d_in.nia;
 455         v.e.unit := d_in.decode.unit;
 456         v.e.fac := d_in.decode.facility;
 457         v.e.read_reg1 := decoded_reg_a.reg;
 458         v.e.read_data1 := decoded_reg_a.data;
 459         v.e.bypass_data1 := gpr_a_bypass;
 460         v.e.read_reg2 := decoded_reg_b.reg;
 461         v.e.read_data2 := decoded_reg_b.data;
 462         v.e.bypass_data2 := gpr_b_bypass;
 463         v.e.read_data3 := decoded_reg_c.data;
 464         v.e.bypass_data3 := gpr_c_bypass;
 465         v.e.write_reg := decoded_reg_o.reg;
 466         v.e.write_reg_enable := decoded_reg_o.reg_valid;
 467         v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 468         if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
 469             v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 470         end if;
 471         v.e.cr := c_in.read_cr_data;
 472         v.e.bypass_cr := cr_bypass;
 473         v.e.xerc := c_in.read_xerc_data;
 474         v.e.invert_a := d_in.decode.invert_a;
 475         v.e.addm1 := '0';
 476         v.e.insn_type := op;
 477         v.e.invert_out := d_in.decode.invert_out;
 478         v.e.input_carry := d_in.decode.input_carry;
 479         v.e.output_carry := d_in.decode.output_carry;
 480         v.e.is_32bit := d_in.decode.is_32bit;
 481         v.e.is_signed := d_in.decode.is_signed;
 482         v.e.insn := d_in.insn;
 483         v.e.data_len := length;
 484         v.e.byte_reverse := d_in.decode.byte_reverse;
 485         v.e.sign_extend := d_in.decode.sign_extend;
 486         v.e.update := d_in.decode.update;
 487         v.e.reserve := d_in.decode.reserve;
 488         v.e.br_pred := d_in.br_pred;
 489         v.e.result_sel := result_select(op);
 490         v.e.sub_select := subresult_select(op);
 491         if op = OP_BC or op = OP_BCREG then
 492             if d_in.insn(23) = '0' and r.repeat = '0' and
 493                 not (d_in.decode.insn_type = OP_BCREG and d_in.insn(10) = '0') then
 494                 -- decrement CTR if BO(2) = 0 and not bcctr
 495                 v.e.addm1 := '1';
 496                 v.e.result_sel := "000";        -- select adder output
 497             end if;
 498         end if;
 499
 500         -- issue control
 501         control_valid_in <= d_in.valid;
 502         control_sgl_pipe <= d_in.decode.sgl_pipe;
 503
 504         gpr_write_valid <= v.e.write_reg_enable;
 505         gpr_write <= decoded_reg_o.reg;
 506         gpr_bypassable <= '0';
 507         if EX1_BYPASS and d_in.decode.unit = ALU then
 508             gpr_bypassable <= '1';
 509         end if;
 510
 511         gpr_a_read_valid <= decoded_reg_a.reg_valid;
 512         gpr_a_read <= decoded_reg_a.reg;
 513
 514         gpr_b_read_valid <= decoded_reg_b.reg_valid;
 515         gpr_b_read <= decoded_reg_b.reg;
 516
 517         gpr_c_read_valid <= decoded_reg_c.reg_valid;
 518         gpr_c_read <= decoded_reg_c.reg;
 519
 520         cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 521         cr_bypass_avail <= '0';
 522         if EX1_BYPASS and d_in.decode.unit = ALU then
 523             cr_bypass_avail <= d_in.decode.output_cr;
 524         end if;
 525
 526         v.e.valid := control_valid_out;
 527         if control_valid_out = '1' then
 528             v.repeat := v.e.repeat and not r.repeat;
 529         end if;
 530
 531         stall_out <= control_stall_out or v.repeat;
 532
 533         if rst = '1' or flush_in = '1' then
 534             v.e := Decode2ToExecute1Init;
 535             v.repeat := '0';
 536         end if;
 537
 538         -- Update registers
 539         rin <= v;
 540
 541         -- Update outputs
 542         e_out <= r.e;
 543     end process;
 544
 545     d2_log: if LOG_LENGTH > 0 generate
 546         signal log_data : std_ulogic_vector(9 downto 0);
 547     begin
 548         dec2_log : process(clk)
 549         begin
 550             if rising_edge(clk) then
 551                 log_data <= r.e.nia(5 downto 2) &
 552                             r.e.valid &
 553                             stopped_out &
 554                             stall_out &
 555                             r.e.bypass_data3 &
 556                             r.e.bypass_data2 &
 557                             r.e.bypass_data1;
 558             end if;
 559         end process;
 560         log_out <= log_data;
 561     end generate;
 562
 563 end architecture behaviour;