decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12         generic (
  13                 EX1_BYPASS : boolean := true
  14         );
  15         port (
  16                 clk   : in std_ulogic;
  17                 rst   : in std_ulogic;
  18
  19                 complete_in : in std_ulogic;
  20                 stall_in : in std_ulogic;
  21                 stall_out : out std_ulogic;
  22
  23                 stopped_out : out std_ulogic;
  24
  25                 flush_in: in std_ulogic;
  26
  27                 d_in  : in Decode1ToDecode2Type;
  28
  29                 e_out : out Decode2ToExecute1Type;
  30
  31                 r_in  : in RegisterFileToDecode2Type;
  32                 r_out : out Decode2ToRegisterFileType;
  33
  34                 c_in  : in CrFileToDecode2Type;
  35                 c_out : out Decode2ToCrFileType
  36         );
  37 end entity decode2;
  38
  39 architecture behaviour of decode2 is
  40         type reg_type is record
  41                 e : Decode2ToExecute1Type;
  42         end record;
  43
  44         signal r, rin : reg_type;
  45
  46         type decode_input_reg_t is record
  47                 reg_valid : std_ulogic;
  48                 reg       : gspr_index_t;
  49                 data      : std_ulogic_vector(63 downto 0);
  50         end record;
  51
  52         type decode_output_reg_t is record
  53                 reg_valid : std_ulogic;
  54                 reg       : gspr_index_t;
  55         end record;
  56
  57         function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  58                                      reg_data : std_ulogic_vector(63 downto 0);
  59                                      ispr : gspr_index_t) return decode_input_reg_t is
  60         begin
  61                 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  62                     assert is_fast_spr(ispr) = '0' report "Decode A says GPR but ISPR says SPR:" &
  63                         to_hstring(ispr) severity failure;
  64                     return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  65                 elsif t = SPR then
  66                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  67                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
  68                     -- operations are single issue.
  69                     --
  70                     assert is_fast_spr(ispr) =  '1' or ispr = "000000"
  71                         report "Decode A says SPR but ISPR is invalid:" &
  72                         to_hstring(ispr) severity failure;
  73                     return (is_fast_spr(ispr), ispr, reg_data);
  74                 else
  75                         return ('0', (others => '0'), (others => '0'));
  76                 end if;
  77         end;
  78
  79         function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  80                                      reg_data : std_ulogic_vector(63 downto 0);
  81                                      ispr : gspr_index_t) return decode_input_reg_t is
  82                 variable ret : decode_input_reg_t;
  83         begin
  84                 case t is
  85                 when RB =>
  86                     assert is_fast_spr(ispr) = '0' report "Decode B says GPR but ISPR says SPR:" &
  87                         to_hstring(ispr) severity failure;
  88                     ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
  89                 when CONST_UI =>
  90                         ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  91                 when CONST_SI =>
  92                         ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  93                 when CONST_SI_HI =>
  94                         ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
  95                 when CONST_UI_HI =>
  96                         ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
  97                 when CONST_LI =>
  98                         ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
  99                 when CONST_BD =>
 100                         ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 101                 when CONST_DS =>
 102                         ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 103                 when CONST_M1 =>
 104                         ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 105                 when CONST_SH =>
 106                         ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 107                 when CONST_SH32 =>
 108                         ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 109                 when SPR =>
 110                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 111                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
 112                     -- operations are single issue.
 113                     assert is_fast_spr(ispr) = '1' or ispr = "000000"
 114                         report "Decode B says SPR but ISPR is invalid:" &
 115                         to_hstring(ispr) severity failure;
 116                     ret := (is_fast_spr(ispr), ispr, reg_data);
 117                 when NONE =>
 118                         ret := ('0', (others => '0'), (others => '0'));
 119                 end case;
 120
 121                 return ret;
 122         end;
 123
 124         function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 125                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 126         begin
 127                 case t is
 128                 when RS =>
 129                         return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 130                 when NONE =>
 131                         return ('0', (others => '0'), (others => '0'));
 132                 end case;
 133         end;
 134
 135         function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 136                                     ispr : gspr_index_t) return decode_output_reg_t is
 137         begin
 138                 case t is
 139                 when RT =>
 140                     return ('1', gpr_to_gspr(insn_rt(insn_in)));
 141                 when RA =>
 142                     return ('1', gpr_to_gspr(insn_ra(insn_in)));
 143                 when SPR =>
 144                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 145                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
 146                     -- operations are single issue.
 147                     assert is_fast_spr(ispr) = '1' or ispr = "000000"
 148                         report "Decode B says SPR but ISPR is invalid:" &
 149                         to_hstring(ispr) severity failure;
 150                     return (is_fast_spr(ispr), ispr);
 151                 when NONE =>
 152                     return ('0', "000000");
 153                 end case;
 154         end;
 155
 156         function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 157         begin
 158                 case t is
 159                 when RC =>
 160                         return insn_rc(insn_in);
 161                 when ONE =>
 162                         return '1';
 163                 when NONE =>
 164                         return '0';
 165                 end case;
 166         end;
 167
 168         -- For now, use "rc" in the decode table to decide whether oe exists.
 169         -- This is not entirely correct architecturally: For mulhd and
 170         -- mulhdu, the OE field is reserved. It remains to be seen what an
 171         -- actual POWER9 does if we set it on those instructions, for now we
 172         -- test that further down when assigning to the multiplier oe input.
 173         --
 174         function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 175         begin
 176                 case t is
 177                 when RC =>
 178                         return insn_oe(insn_in);
 179                 when OTHERS =>
 180                         return '0';
 181                 end case;
 182         end;
 183
 184         -- issue control signals
 185         signal control_valid_in : std_ulogic;
 186         signal control_valid_out : std_ulogic;
 187         signal control_sgl_pipe : std_logic;
 188
 189         signal gpr_write_valid : std_ulogic;
 190         signal gpr_write : gspr_index_t;
 191         signal gpr_bypassable  : std_ulogic;
 192
 193         signal gpr_a_read_valid : std_ulogic;
 194         signal gpr_a_read :gspr_index_t;
 195         signal gpr_a_bypass : std_ulogic;
 196
 197         signal gpr_b_read_valid : std_ulogic;
 198         signal gpr_b_read : gspr_index_t;
 199         signal gpr_b_bypass : std_ulogic;
 200
 201         signal gpr_c_read_valid : std_ulogic;
 202         signal gpr_c_read : gpr_index_t;
 203         signal gpr_c_bypass : std_ulogic;
 204
 205         signal cr_write_valid : std_ulogic;
 206 begin
 207         control_0: entity work.control
 208         generic map (
 209                 PIPELINE_DEPTH => 1
 210         )
 211         port map (
 212                 clk         => clk,
 213                 rst         => rst,
 214
 215                 complete_in => complete_in,
 216                 valid_in    => control_valid_in,
 217                 stall_in    => stall_in,
 218                 flush_in    => flush_in,
 219                 sgl_pipe_in => control_sgl_pipe,
 220                 stop_mark_in => d_in.stop_mark,
 221
 222                 gpr_write_valid_in => gpr_write_valid,
 223                 gpr_write_in       => gpr_write,
 224                 gpr_bypassable     => gpr_bypassable,
 225
 226                 gpr_a_read_valid_in  => gpr_a_read_valid,
 227                 gpr_a_read_in        => gpr_a_read,
 228
 229                 gpr_b_read_valid_in  => gpr_b_read_valid,
 230                 gpr_b_read_in        => gpr_b_read,
 231
 232                 gpr_c_read_valid_in  => gpr_c_read_valid,
 233                 gpr_c_read_in        => gpr_c_read,
 234
 235                 cr_read_in           => d_in.decode.input_cr,
 236                 cr_write_in           => cr_write_valid,
 237
 238                 valid_out   => control_valid_out,
 239                 stall_out   => stall_out,
 240                 stopped_out => stopped_out,
 241
 242                 gpr_bypass_a => gpr_a_bypass,
 243                 gpr_bypass_b => gpr_b_bypass,
 244                 gpr_bypass_c => gpr_c_bypass
 245         );
 246
 247         decode2_0: process(clk)
 248         begin
 249                 if rising_edge(clk) then
 250                         if rin.e.valid = '1' then
 251                                 report "execute " & to_hstring(rin.e.nia);
 252                         end if;
 253                         r <= rin;
 254                 end if;
 255         end process;
 256
 257         r_out.read1_reg <= gpr_or_spr_to_gspr(insn_ra(d_in.insn), d_in.ispr1);
 258         r_out.read2_reg <= gpr_or_spr_to_gspr(insn_rb(d_in.insn), d_in.ispr2);
 259         r_out.read3_reg <= insn_rs(d_in.insn);
 260
 261         c_out.read <= d_in.decode.input_cr;
 262
 263         decode2_1: process(all)
 264                 variable v : reg_type;
 265                 variable mul_a : std_ulogic_vector(63 downto 0);
 266                 variable mul_b : std_ulogic_vector(63 downto 0);
 267                 variable decoded_reg_a : decode_input_reg_t;
 268                 variable decoded_reg_b : decode_input_reg_t;
 269                 variable decoded_reg_c : decode_input_reg_t;
 270                 variable decoded_reg_o : decode_output_reg_t;
 271                 variable length : std_ulogic_vector(3 downto 0);
 272         begin
 273                 v := r;
 274
 275                 v.e := Decode2ToExecute1Init;
 276
 277                 mul_a := (others => '0');
 278                 mul_b := (others => '0');
 279
 280                 --v.e.input_cr := d_in.decode.input_cr;
 281                 --v.e.output_cr := d_in.decode.output_cr;
 282
 283                 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1);
 284                 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 285                 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 286                 decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
 287
 288                 r_out.read1_enable <= decoded_reg_a.reg_valid;
 289                 r_out.read2_enable <= decoded_reg_b.reg_valid;
 290                 r_out.read3_enable <= decoded_reg_c.reg_valid;
 291
 292                 case d_in.decode.length is
 293                 when is1B =>
 294                         length := "0001";
 295                 when is2B =>
 296                         length := "0010";
 297                 when is4B =>
 298                         length := "0100";
 299                 when is8B =>
 300                         length := "1000";
 301                 when NONE =>
 302                         length := "0000";
 303                 end case;
 304
 305                 -- execute unit
 306                 v.e.nia := d_in.nia;
 307                 v.e.insn_type := d_in.decode.insn_type;
 308                 v.e.read_reg1 := decoded_reg_a.reg;
 309                 v.e.read_data1 := decoded_reg_a.data;
 310                 v.e.bypass_data1 := gpr_a_bypass;
 311                 v.e.read_reg2 := decoded_reg_b.reg;
 312                 v.e.read_data2 := decoded_reg_b.data;
 313                 v.e.bypass_data2 := gpr_b_bypass;
 314                 v.e.read_data3 := decoded_reg_c.data;
 315                 v.e.bypass_data3 := gpr_c_bypass;
 316                 v.e.write_reg := decoded_reg_o.reg;
 317                 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 318                 if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
 319                         v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 320                 end if;
 321                 v.e.cr := c_in.read_cr_data;
 322                 v.e.xerc := c_in.read_xerc_data;
 323                 v.e.invert_a := d_in.decode.invert_a;
 324                 v.e.invert_out := d_in.decode.invert_out;
 325                 v.e.input_carry := d_in.decode.input_carry;
 326                 v.e.output_carry := d_in.decode.output_carry;
 327                 v.e.is_32bit := d_in.decode.is_32bit;
 328                 v.e.is_signed := d_in.decode.is_signed;
 329                 if d_in.decode.lr = '1' then
 330                         v.e.lr := insn_lk(d_in.insn);
 331                 end if;
 332                 v.e.insn := d_in.insn;
 333                 v.e.data_len := length;
 334                 v.e.byte_reverse := d_in.decode.byte_reverse;
 335                 v.e.sign_extend := d_in.decode.sign_extend;
 336                 v.e.update := d_in.decode.update;
 337
 338                 -- issue control
 339                 control_valid_in <= d_in.valid;
 340                 control_sgl_pipe <= d_in.decode.sgl_pipe;
 341
 342                 gpr_write_valid <= decoded_reg_o.reg_valid;
 343                 gpr_write <= decoded_reg_o.reg;
 344                 gpr_bypassable <= '0';
 345                 if EX1_BYPASS and d_in.decode.unit = ALU then
 346                         gpr_bypassable <= '1';
 347                 end if;
 348
 349                 gpr_a_read_valid <= decoded_reg_a.reg_valid;
 350                 gpr_a_read <= decoded_reg_a.reg;
 351
 352                 gpr_b_read_valid <= decoded_reg_b.reg_valid;
 353                 gpr_b_read <= decoded_reg_b.reg;
 354
 355                 gpr_c_read_valid <= decoded_reg_c.reg_valid;
 356                 gpr_c_read <= gspr_to_gpr(decoded_reg_c.reg);
 357
 358                 cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 359
 360                 v.e.valid := control_valid_out;
 361                 if d_in.decode.unit = NONE then
 362                         v.e.insn_type := OP_ILLEGAL;
 363                 end if;
 364
 365                 if rst = '1' then
 366                         v.e := Decode2ToExecute1Init;
 367                 end if;
 368
 369                 -- Update registers
 370                 rin <= v;
 371
 372                 -- Update outputs
 373                 e_out <= r.e;
 374         end process;
 375 end architecture behaviour;