decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12         port (
  13                 clk   : in std_ulogic;
  14                 rst   : in std_ulogic;
  15
  16                 complete_in : in std_ulogic;
  17                 stall_out : out std_ulogic;
  18
  19                 stopped_out : out std_ulogic;
  20
  21                 flush_in: in std_ulogic;
  22
  23                 d_in  : in Decode1ToDecode2Type;
  24
  25                 e_out : out Decode2ToExecute1Type;
  26                 m_out : out Decode2ToMultiplyType;
  27                 d_out : out Decode2ToDividerType;
  28                 l_out : out Decode2ToLoadstore1Type;
  29
  30                 r_in  : in RegisterFileToDecode2Type;
  31                 r_out : out Decode2ToRegisterFileType;
  32
  33                 c_in  : in CrFileToDecode2Type;
  34                 c_out : out Decode2ToCrFileType
  35         );
  36 end entity decode2;
  37
  38 architecture behaviour of decode2 is
  39         type reg_type is record
  40                 e : Decode2ToExecute1Type;
  41                 m : Decode2ToMultiplyType;
  42                 d : Decode2ToDividerType;
  43                 l : Decode2ToLoadstore1Type;
  44         end record;
  45
  46         signal r, rin : reg_type;
  47
  48         type decode_input_reg_t is record
  49                 reg_valid : std_ulogic;
  50                 reg       : std_ulogic_vector(4 downto 0);
  51                 data      : std_ulogic_vector(63 downto 0);
  52         end record;
  53
  54         function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  55                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  56                 variable is_reg : std_ulogic;
  57         begin
  58                 is_reg := '0' when insn_ra(insn_in) = "00000" else '1';
  59
  60                 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  61                         --return (is_reg, insn_ra(insn_in), reg_data);
  62                         return ('1', insn_ra(insn_in), reg_data);
  63                 else
  64                         return ('0', (others => '0'), (others => '0'));
  65                 end if;
  66         end;
  67
  68         function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  69                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  70         begin
  71                 case t is
  72                 when RB =>
  73                         return ('1', insn_rb(insn_in), reg_data);
  74                 when CONST_UI =>
  75                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  76                 when CONST_SI =>
  77                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  78                 when CONST_SI_HI =>
  79                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
  80                 when CONST_UI_HI =>
  81                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
  82                 when CONST_LI =>
  83                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
  84                 when CONST_BD =>
  85                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
  86                 when CONST_DS =>
  87                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
  88                 when CONST_M1 =>
  89                         return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
  90                 when CONST_SH =>
  91                         return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
  92                 when CONST_SH32 =>
  93                         return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
  94                 when NONE =>
  95                         return ('0', (others => '0'), (others => '0'));
  96                 end case;
  97         end;
  98
  99         function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 100                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 101         begin
 102                 case t is
 103                 when RS =>
 104                         return ('1', insn_rs(insn_in), reg_data);
 105                 when NONE =>
 106                         return ('0', (others => '0'), (others => '0'));
 107                 end case;
 108         end;
 109
 110         function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 111         begin
 112                 case t is
 113                 when RT =>
 114                         return insn_rt(insn_in);
 115                 when RA =>
 116                         return insn_ra(insn_in);
 117                 when NONE =>
 118                         return "00000";
 119                 end case;
 120         end;
 121
 122         function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 123         begin
 124                 case t is
 125                 when RC =>
 126                         return insn_rc(insn_in);
 127                 when ONE =>
 128                         return '1';
 129                 when NONE =>
 130                         return '0';
 131                 end case;
 132         end;
 133
 134         -- issue control signals
 135         signal control_valid_in : std_ulogic;
 136         signal control_valid_out : std_ulogic;
 137         signal control_sgl_pipe : std_logic;
 138
 139         signal gpr_write_valid : std_ulogic;
 140         signal gpr_write : std_ulogic_vector(4 downto 0);
 141
 142         signal gpr_a_read_valid : std_ulogic;
 143         signal gpr_a_read : std_ulogic_vector(4 downto 0);
 144
 145         signal gpr_b_read_valid : std_ulogic;
 146         signal gpr_b_read : std_ulogic_vector(4 downto 0);
 147
 148         signal gpr_c_read_valid : std_ulogic;
 149         signal gpr_c_read : std_ulogic_vector(4 downto 0);
 150
 151         signal cr_write_valid : std_ulogic;
 152 begin
 153         control_0: entity work.control
 154         generic map (
 155                 PIPELINE_DEPTH => 1
 156         )
 157         port map (
 158                 clk         => clk,
 159                 rst         => rst,
 160
 161                 complete_in => complete_in,
 162                 valid_in    => control_valid_in,
 163                 flush_in    => flush_in,
 164                 sgl_pipe_in => control_sgl_pipe,
 165                 stop_mark_in => d_in.stop_mark,
 166
 167                 gpr_write_valid_in => gpr_write_valid,
 168                 gpr_write_in       => gpr_write,
 169
 170                 gpr_a_read_valid_in  => gpr_a_read_valid,
 171                 gpr_a_read_in        => gpr_a_read,
 172
 173                 gpr_b_read_valid_in  => gpr_b_read_valid,
 174                 gpr_b_read_in        => gpr_b_read,
 175
 176                 gpr_c_read_valid_in  => gpr_c_read_valid,
 177                 gpr_c_read_in        => gpr_c_read,
 178
 179                 cr_read_in           => d_in.decode.input_cr,
 180                 cr_write_in           => cr_write_valid,
 181
 182                 valid_out   => control_valid_out,
 183                 stall_out   => stall_out,
 184                 stopped_out => stopped_out
 185         );
 186
 187         decode2_0: process(clk)
 188         begin
 189                 if rising_edge(clk) then
 190                         if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' or rin.d.valid = '1' then
 191                                 report "execute " & to_hstring(rin.e.nia);
 192                         end if;
 193                         r <= rin;
 194                 end if;
 195         end process;
 196
 197         r_out.read1_reg <= insn_ra(d_in.insn);
 198         r_out.read2_reg <= insn_rb(d_in.insn);
 199         r_out.read3_reg <= insn_rs(d_in.insn);
 200
 201         c_out.read <= d_in.decode.input_cr;
 202
 203         decode2_1: process(all)
 204                 variable v : reg_type;
 205                 variable mul_a : std_ulogic_vector(63 downto 0);
 206                 variable mul_b : std_ulogic_vector(63 downto 0);
 207                 variable decoded_reg_a : decode_input_reg_t;
 208                 variable decoded_reg_b : decode_input_reg_t;
 209                 variable decoded_reg_c : decode_input_reg_t;
 210                 variable signed_division: std_ulogic;
 211                 variable length : std_ulogic_vector(3 downto 0);
 212         begin
 213                 v := r;
 214
 215                 v.e := Decode2ToExecute1Init;
 216                 v.l := Decode2ToLoadStore1Init;
 217                 v.m := Decode2ToMultiplyInit;
 218                 v.d := Decode2ToDividerInit;
 219
 220                 mul_a := (others => '0');
 221                 mul_b := (others => '0');
 222
 223                 --v.e.input_cr := d_in.decode.input_cr;
 224                 --v.m.input_cr := d_in.decode.input_cr;
 225                 --v.e.output_cr := d_in.decode.output_cr;
 226
 227                 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data);
 228                 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data);
 229                 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 230
 231                 r_out.read1_enable <= decoded_reg_a.reg_valid;
 232                 r_out.read2_enable <= decoded_reg_b.reg_valid;
 233                 r_out.read3_enable <= decoded_reg_c.reg_valid;
 234
 235                 case d_in.decode.length is
 236                 when is1B =>
 237                         length := "0001";
 238                 when is2B =>
 239                         length := "0010";
 240                 when is4B =>
 241                         length := "0100";
 242                 when is8B =>
 243                         length := "1000";
 244                 when NONE =>
 245                         length := "0000";
 246                 end case;
 247
 248                 -- execute unit
 249                 v.e.nia := d_in.nia;
 250                 v.e.insn_type := d_in.decode.insn_type;
 251                 v.e.read_reg1 := decoded_reg_a.reg;
 252                 v.e.read_data1 := decoded_reg_a.data;
 253                 v.e.read_reg2 := decoded_reg_b.reg;
 254                 v.e.read_data2 := decoded_reg_b.data;
 255                 v.e.read_data3 := decoded_reg_c.data;
 256                 v.e.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 257                 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 258                 v.e.cr := c_in.read_cr_data;
 259                 v.e.invert_a := d_in.decode.invert_a;
 260                 v.e.invert_out := d_in.decode.invert_out;
 261                 v.e.input_carry := d_in.decode.input_carry;
 262                 v.e.output_carry := d_in.decode.output_carry;
 263                 v.e.is_32bit := d_in.decode.is_32bit;
 264                 v.e.is_signed := d_in.decode.is_signed;
 265                 if d_in.decode.lr = '1' then
 266                         v.e.lr := insn_lk(d_in.insn);
 267                 end if;
 268                 v.e.insn := d_in.insn;
 269                 v.e.data_len := length;
 270
 271                 -- multiply unit
 272                 v.m.insn_type := d_in.decode.insn_type;
 273                 mul_a := decoded_reg_a.data;
 274                 mul_b := decoded_reg_b.data;
 275                 v.m.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 276                 v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
 277
 278                 if d_in.decode.is_32bit = '1' then
 279                         if d_in.decode.is_signed = '1' then
 280                                 v.m.data1 := (others => mul_a(31));
 281                                 v.m.data1(31 downto 0) := mul_a(31 downto 0);
 282                                 v.m.data2 := (others => mul_b(31));
 283                                 v.m.data2(31 downto 0) := mul_b(31 downto 0);
 284                         else
 285                                 v.m.data1 := '0' & x"00000000" & mul_a(31 downto 0);
 286                                 v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
 287                         end if;
 288                 else
 289                         if d_in.decode.is_signed = '1' then
 290                                 v.m.data1 := mul_a(63) & mul_a;
 291                                 v.m.data2 := mul_b(63) & mul_b;
 292                         else
 293                                 v.m.data1 := '0' & mul_a;
 294                                 v.m.data2 := '0' & mul_b;
 295                         end if;
 296                 end if;
 297
 298                 -- divide unit
 299                 -- PPC divide and modulus instruction words have these bits in
 300                 -- the bottom 11 bits: o1dns 010t1 r
 301                 -- where o = OE for div instrs, signedness for mod instrs
 302                 --       d = 1 for div*, 0 for mod*
 303                 --       n = 1 for normal, 0 for extended (dividend << 32/64)
 304                 --       s = 1 for signed, 0 for unsigned (for div*)
 305                 --       t = 1 for 32-bit, 0 for 64-bit
 306                 --       r = RC bit (record condition code)
 307                 v.d.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 308                 v.d.is_modulus := not d_in.insn(8);
 309                 v.d.is_32bit := d_in.insn(2);
 310                 if d_in.insn(8) = '1' then
 311                         signed_division := d_in.insn(6);
 312                 else
 313                         signed_division := d_in.insn(10);
 314                 end if;
 315                 v.d.is_signed := signed_division;
 316                 if d_in.insn(2) = '0' then
 317                         -- 64-bit forms
 318                         if d_in.insn(8) = '1' and d_in.insn(7) = '0' then
 319                                 v.d.is_extended := '1';
 320                         end if;
 321                         v.d.dividend := decoded_reg_a.data;
 322                         v.d.divisor := decoded_reg_b.data;
 323                 else
 324                         -- 32-bit forms
 325                         if d_in.insn(8) = '1' and d_in.insn(7) = '0' then   -- extended forms
 326                                 v.d.dividend := decoded_reg_a.data(31 downto 0) & x"00000000";
 327                         elsif signed_division = '1' and decoded_reg_a.data(31) = '1' then
 328                                 -- sign extend to 64 bits
 329                                 v.d.dividend := x"ffffffff" & decoded_reg_a.data(31 downto 0);
 330                         else
 331                                 v.d.dividend := x"00000000" & decoded_reg_a.data(31 downto 0);
 332                         end if;
 333                         if signed_division = '1' and decoded_reg_b.data(31) = '1' then
 334                                 v.d.divisor := x"ffffffff" & decoded_reg_b.data(31 downto 0);
 335                         else
 336                                 v.d.divisor := x"00000000" & decoded_reg_b.data(31 downto 0);
 337                         end if;
 338                 end if;
 339                 v.d.rc := decode_rc(d_in.decode.rc, d_in.insn);
 340
 341                 -- load/store unit
 342                 v.l.update_reg := decoded_reg_a.reg;
 343                 v.l.addr1 := decoded_reg_a.data;
 344                 v.l.addr2 := decoded_reg_b.data;
 345                 v.l.data := decoded_reg_c.data;
 346                 v.l.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 347
 348                 if d_in.decode.insn_type = OP_LOAD then
 349                         v.l.load := '1';
 350                 else
 351                         v.l.load := '0';
 352                 end if;
 353
 354                 v.l.length := length;
 355                 v.l.byte_reverse := d_in.decode.byte_reverse;
 356                 v.l.sign_extend := d_in.decode.sign_extend;
 357                 v.l.update := d_in.decode.update;
 358
 359                 -- issue control
 360                 control_valid_in <= d_in.valid;
 361                 control_sgl_pipe <= d_in.decode.sgl_pipe;
 362
 363                 gpr_write_valid <= '1' when d_in.decode.output_reg_a /= NONE else '0';
 364                 gpr_write <= decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 365
 366                 gpr_a_read_valid <= decoded_reg_a.reg_valid;
 367                 gpr_a_read <= decoded_reg_a.reg;
 368
 369                 gpr_b_read_valid <= decoded_reg_b.reg_valid;
 370                 gpr_b_read <= decoded_reg_b.reg;
 371
 372                 gpr_c_read_valid <= decoded_reg_c.reg_valid;
 373                 gpr_c_read <= decoded_reg_c.reg;
 374
 375                 cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 376
 377                 v.e.valid := '0';
 378                 v.m.valid := '0';
 379                 v.d.valid := '0';
 380                 v.l.valid := '0';
 381                 case d_in.decode.unit is
 382                 when ALU =>
 383                         v.e.valid := control_valid_out;
 384                 when LDST =>
 385                         v.l.valid := control_valid_out;
 386                 when MUL =>
 387                         v.m.valid := control_valid_out;
 388                 when DIV =>
 389                         v.d.valid := control_valid_out;
 390                 when NONE =>
 391                         v.e.valid := control_valid_out;
 392                         v.e.insn_type := OP_ILLEGAL;
 393                 end case;
 394
 395                 if rst = '1' then
 396                         v.e := Decode2ToExecute1Init;
 397                         v.l := Decode2ToLoadStore1Init;
 398                         v.m := Decode2ToMultiplyInit;
 399                         v.d := Decode2ToDividerInit;
 400                 end if;
 401
 402                 -- Update registers
 403                 rin <= v;
 404
 405                 -- Update outputs
 406                 e_out <= r.e;
 407                 l_out <= r.l;
 408                 m_out <= r.m;
 409                 d_out <= r.d;
 410         end process;
 411 end architecture behaviour;