2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
9 use work.insn_helpers.all;
13 EX1_BYPASS : boolean := true;
14 HAS_FPU : boolean := true;
15 -- Non-zero to enable log data collection
16 LOG_LENGTH : natural := 0
22 complete_in : in std_ulogic;
23 busy_in : in std_ulogic;
24 stall_out : out std_ulogic;
26 stopped_out : out std_ulogic;
28 flush_in: in std_ulogic;
30 d_in : in Decode1ToDecode2Type;
32 e_out : out Decode2ToExecute1Type;
34 r_in : in RegisterFileToDecode2Type;
35 r_out : out Decode2ToRegisterFileType;
37 c_in : in CrFileToDecode2Type;
38 c_out : out Decode2ToCrFileType;
40 log_out : out std_ulogic_vector(9 downto 0)
44 architecture behaviour of decode2 is
45 type reg_type is record
46 e : Decode2ToExecute1Type;
49 signal r, rin : reg_type;
51 signal deferred : std_ulogic;
53 type decode_input_reg_t is record
54 reg_valid : std_ulogic;
56 data : std_ulogic_vector(63 downto 0);
59 type decode_output_reg_t is record
60 reg_valid : std_ulogic;
64 function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
65 reg_data : std_ulogic_vector(63 downto 0);
67 instr_addr : std_ulogic_vector(63 downto 0))
68 return decode_input_reg_t is
70 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
71 return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
73 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
74 -- If it's all 0, we don't treat it as a dependency as slow SPRs
75 -- operations are single issue.
77 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
78 report "Decode A says SPR but ISPR is invalid:" &
79 to_hstring(ispr) severity failure;
80 return (is_fast_spr(ispr), ispr, reg_data);
82 return ('0', (others => '0'), instr_addr);
83 elsif HAS_FPU and t = FRA then
84 return ('1', fpr_to_gspr(insn_fra(insn_in)), reg_data);
86 return ('0', (others => '0'), (others => '0'));
90 function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
91 reg_data : std_ulogic_vector(63 downto 0);
92 ispr : gspr_index_t) return decode_input_reg_t is
93 variable ret : decode_input_reg_t;
97 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
100 ret := ('1', fpr_to_gspr(insn_frb(insn_in)), reg_data);
102 ret := ('0', (others => '0'), (others => '0'));
105 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
107 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
109 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
111 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
113 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
115 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
117 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
119 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
121 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
123 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
125 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
127 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
128 -- If it's all 0, we don't treat it as a dependency as slow SPRs
129 -- operations are single issue.
130 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
131 report "Decode B says SPR but ISPR is invalid:" &
132 to_hstring(ispr) severity failure;
133 ret := (is_fast_spr(ispr), ispr, reg_data);
135 ret := ('0', (others => '0'), (others => '0'));
141 function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
142 reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
146 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
148 return ('1', gpr_to_gspr(insn_rcreg(insn_in)), reg_data);
151 return ('1', fpr_to_gspr(insn_frt(insn_in)), reg_data);
153 return ('0', (others => '0'), (others => '0'));
156 return ('0', (others => '0'), (others => '0'));
160 function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
161 ispr : gspr_index_t) return decode_output_reg_t is
165 return ('1', gpr_to_gspr(insn_rt(insn_in)));
167 return ('1', gpr_to_gspr(insn_ra(insn_in)));
170 return ('1', fpr_to_gspr(insn_frt(insn_in)));
172 return ('0', "0000000");
175 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
176 -- If it's all 0, we don't treat it as a dependency as slow SPRs
177 -- operations are single issue.
178 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
179 report "Decode B says SPR but ISPR is invalid:" &
180 to_hstring(ispr) severity failure;
181 return (is_fast_spr(ispr), ispr);
183 return ('0', "0000000");
187 function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
191 return insn_rc(insn_in);
199 -- For now, use "rc" in the decode table to decide whether oe exists.
200 -- This is not entirely correct architecturally: For mulhd and
201 -- mulhdu, the OE field is reserved. It remains to be seen what an
202 -- actual POWER9 does if we set it on those instructions, for now we
203 -- test that further down when assigning to the multiplier oe input.
205 function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
209 return insn_oe(insn_in);
215 -- issue control signals
216 signal control_valid_in : std_ulogic;
217 signal control_valid_out : std_ulogic;
218 signal control_sgl_pipe : std_logic;
220 signal gpr_write_valid : std_ulogic;
221 signal gpr_write : gspr_index_t;
222 signal gpr_bypassable : std_ulogic;
224 signal update_gpr_write_valid : std_ulogic;
225 signal update_gpr_write_reg : gspr_index_t;
227 signal gpr_a_read_valid : std_ulogic;
228 signal gpr_a_read :gspr_index_t;
229 signal gpr_a_bypass : std_ulogic;
231 signal gpr_b_read_valid : std_ulogic;
232 signal gpr_b_read : gspr_index_t;
233 signal gpr_b_bypass : std_ulogic;
235 signal gpr_c_read_valid : std_ulogic;
236 signal gpr_c_read : gspr_index_t;
237 signal gpr_c_bypass : std_ulogic;
239 signal cr_write_valid : std_ulogic;
240 signal cr_bypass : std_ulogic;
241 signal cr_bypass_avail : std_ulogic;
244 control_0: entity work.control
252 complete_in => complete_in,
253 valid_in => control_valid_in,
255 deferred => deferred,
256 flush_in => flush_in,
257 sgl_pipe_in => control_sgl_pipe,
258 stop_mark_in => d_in.stop_mark,
260 gpr_write_valid_in => gpr_write_valid,
261 gpr_write_in => gpr_write,
262 gpr_bypassable => gpr_bypassable,
264 update_gpr_write_valid => update_gpr_write_valid,
265 update_gpr_write_reg => update_gpr_write_reg,
267 gpr_a_read_valid_in => gpr_a_read_valid,
268 gpr_a_read_in => gpr_a_read,
270 gpr_b_read_valid_in => gpr_b_read_valid,
271 gpr_b_read_in => gpr_b_read,
273 gpr_c_read_valid_in => gpr_c_read_valid,
274 gpr_c_read_in => gpr_c_read,
276 cr_read_in => d_in.decode.input_cr,
277 cr_write_in => cr_write_valid,
278 cr_bypass => cr_bypass,
279 cr_bypassable => cr_bypass_avail,
281 valid_out => control_valid_out,
282 stall_out => stall_out,
283 stopped_out => stopped_out,
285 gpr_bypass_a => gpr_a_bypass,
286 gpr_bypass_b => gpr_b_bypass,
287 gpr_bypass_c => gpr_c_bypass
290 deferred <= r.e.valid and busy_in;
292 decode2_0: process(clk)
294 if rising_edge(clk) then
295 if rst = '1' or flush_in = '1' or deferred = '0' then
296 if rin.e.valid = '1' then
297 report "execute " & to_hstring(rin.e.nia);
304 r_out.read1_reg <= d_in.ispr1 when d_in.decode.input_reg_a = SPR
305 else fpr_to_gspr(insn_fra(d_in.insn)) when d_in.decode.input_reg_a = FRA and HAS_FPU
306 else gpr_to_gspr(insn_ra(d_in.insn));
307 r_out.read2_reg <= d_in.ispr2 when d_in.decode.input_reg_b = SPR
308 else fpr_to_gspr(insn_frb(d_in.insn)) when d_in.decode.input_reg_b = FRB and HAS_FPU
309 else gpr_to_gspr(insn_rb(d_in.insn));
310 r_out.read3_reg <= gpr_to_gspr(insn_rcreg(d_in.insn)) when d_in.decode.input_reg_c = RCR
311 else fpr_to_gspr(insn_frt(d_in.insn)) when d_in.decode.input_reg_c = FRS and HAS_FPU
312 else gpr_to_gspr(insn_rs(d_in.insn));
314 c_out.read <= d_in.decode.input_cr;
316 decode2_1: process(all)
317 variable v : reg_type;
318 variable mul_a : std_ulogic_vector(63 downto 0);
319 variable mul_b : std_ulogic_vector(63 downto 0);
320 variable decoded_reg_a : decode_input_reg_t;
321 variable decoded_reg_b : decode_input_reg_t;
322 variable decoded_reg_c : decode_input_reg_t;
323 variable decoded_reg_o : decode_output_reg_t;
324 variable length : std_ulogic_vector(3 downto 0);
328 v.e := Decode2ToExecute1Init;
330 mul_a := (others => '0');
331 mul_b := (others => '0');
333 --v.e.input_cr := d_in.decode.input_cr;
334 v.e.output_cr := d_in.decode.output_cr;
336 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
338 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
339 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
340 decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
342 r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
343 r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
344 r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
346 case d_in.decode.length is
361 v.e.unit := d_in.decode.unit;
362 v.e.insn_type := d_in.decode.insn_type;
363 v.e.read_reg1 := decoded_reg_a.reg;
364 v.e.read_data1 := decoded_reg_a.data;
365 v.e.bypass_data1 := gpr_a_bypass;
366 v.e.read_reg2 := decoded_reg_b.reg;
367 v.e.read_data2 := decoded_reg_b.data;
368 v.e.bypass_data2 := gpr_b_bypass;
369 v.e.read_data3 := decoded_reg_c.data;
370 v.e.bypass_data3 := gpr_c_bypass;
371 v.e.write_reg := decoded_reg_o.reg;
372 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
373 if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
374 v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
376 v.e.cr := c_in.read_cr_data;
377 v.e.bypass_cr := cr_bypass;
378 v.e.xerc := c_in.read_xerc_data;
379 v.e.invert_a := d_in.decode.invert_a;
380 v.e.invert_out := d_in.decode.invert_out;
381 v.e.input_carry := d_in.decode.input_carry;
382 v.e.output_carry := d_in.decode.output_carry;
383 v.e.is_32bit := d_in.decode.is_32bit;
384 v.e.is_signed := d_in.decode.is_signed;
385 if d_in.decode.lr = '1' then
386 v.e.lr := insn_lk(d_in.insn);
388 v.e.insn := d_in.insn;
389 v.e.data_len := length;
390 v.e.byte_reverse := d_in.decode.byte_reverse;
391 v.e.sign_extend := d_in.decode.sign_extend;
392 v.e.update := d_in.decode.update;
393 v.e.reserve := d_in.decode.reserve;
394 v.e.br_pred := d_in.br_pred;
397 control_valid_in <= d_in.valid;
398 control_sgl_pipe <= d_in.decode.sgl_pipe;
400 gpr_write_valid <= decoded_reg_o.reg_valid;
401 gpr_write <= decoded_reg_o.reg;
402 gpr_bypassable <= '0';
403 if EX1_BYPASS and d_in.decode.unit = ALU then
404 gpr_bypassable <= '1';
406 update_gpr_write_valid <= d_in.decode.update;
407 update_gpr_write_reg <= decoded_reg_a.reg;
409 -- there are no instructions that have both update=1 and lr=1
410 update_gpr_write_valid <= '1';
411 update_gpr_write_reg <= fast_spr_num(SPR_LR);
414 gpr_a_read_valid <= decoded_reg_a.reg_valid;
415 gpr_a_read <= decoded_reg_a.reg;
417 gpr_b_read_valid <= decoded_reg_b.reg_valid;
418 gpr_b_read <= decoded_reg_b.reg;
420 gpr_c_read_valid <= decoded_reg_c.reg_valid;
421 gpr_c_read <= decoded_reg_c.reg;
423 cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
424 cr_bypass_avail <= '0';
425 if EX1_BYPASS and d_in.decode.unit = ALU then
426 cr_bypass_avail <= d_in.decode.output_cr;
429 v.e.valid := control_valid_out;
431 if rst = '1' or flush_in = '1' then
432 v.e := Decode2ToExecute1Init;
442 d2_log: if LOG_LENGTH > 0 generate
443 signal log_data : std_ulogic_vector(9 downto 0);
445 dec2_log : process(clk)
447 if rising_edge(clk) then
448 log_data <= r.e.nia(5 downto 2) &
460 end architecture behaviour;