2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
9 use work.insn_helpers.all;
16 complete_in : in std_ulogic;
17 stall_out : out std_ulogic;
19 stopped_out : out std_ulogic;
21 flush_in: in std_ulogic;
23 d_in : in Decode1ToDecode2Type;
25 e_out : out Decode2ToExecute1Type;
26 m_out : out Decode2ToMultiplyType;
27 d_out : out Decode2ToDividerType;
28 l_out : out Decode2ToLoadstore1Type;
30 r_in : in RegisterFileToDecode2Type;
31 r_out : out Decode2ToRegisterFileType;
33 c_in : in CrFileToDecode2Type;
34 c_out : out Decode2ToCrFileType
38 architecture behaviour of decode2 is
39 type reg_type is record
40 e : Decode2ToExecute1Type;
41 m : Decode2ToMultiplyType;
42 d : Decode2ToDividerType;
43 l : Decode2ToLoadstore1Type;
46 signal r, rin : reg_type;
48 type decode_input_reg_t is record
49 reg_valid : std_ulogic;
50 reg : std_ulogic_vector(4 downto 0);
51 data : std_ulogic_vector(63 downto 0);
54 function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
55 reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
56 variable is_reg : std_ulogic;
58 is_reg := '0' when insn_ra(insn_in) = "00000" else '1';
60 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
61 --return (is_reg, insn_ra(insn_in), reg_data);
62 return ('1', insn_ra(insn_in), reg_data);
64 return ('0', (others => '0'), (others => '0'));
68 function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
69 reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
73 return ('1', insn_rb(insn_in), reg_data);
75 return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
77 return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
79 return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
81 return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
83 return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
85 return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
87 return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
89 return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
91 return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
93 return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
95 return ('0', (others => '0'), (others => '0'));
99 function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
100 reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
104 return ('1', insn_rs(insn_in), reg_data);
106 return ('0', (others => '0'), (others => '0'));
110 function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
114 return insn_rt(insn_in);
116 return insn_ra(insn_in);
122 function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
126 return insn_rc(insn_in);
134 -- issue control signals
135 signal control_valid_in : std_ulogic;
136 signal control_valid_out : std_ulogic;
137 signal control_sgl_pipe : std_logic;
139 signal gpr_write_valid : std_ulogic;
140 signal gpr_write : std_ulogic_vector(4 downto 0);
142 signal gpr_a_read_valid : std_ulogic;
143 signal gpr_a_read : std_ulogic_vector(4 downto 0);
145 signal gpr_b_read_valid : std_ulogic;
146 signal gpr_b_read : std_ulogic_vector(4 downto 0);
148 signal gpr_c_read_valid : std_ulogic;
149 signal gpr_c_read : std_ulogic_vector(4 downto 0);
151 control_0: entity work.control
159 complete_in => complete_in,
160 valid_in => control_valid_in,
161 flush_in => flush_in,
162 sgl_pipe_in => control_sgl_pipe,
163 stop_mark_in => d_in.stop_mark,
165 gpr_write_valid_in => gpr_write_valid,
166 gpr_write_in => gpr_write,
168 gpr_a_read_valid_in => gpr_a_read_valid,
169 gpr_a_read_in => gpr_a_read,
171 gpr_b_read_valid_in => gpr_b_read_valid,
172 gpr_b_read_in => gpr_b_read,
174 gpr_c_read_valid_in => gpr_c_read_valid,
175 gpr_c_read_in => gpr_c_read,
177 valid_out => control_valid_out,
178 stall_out => stall_out,
179 stopped_out => stopped_out
182 decode2_0: process(clk)
184 if rising_edge(clk) then
185 if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' or rin.d.valid = '1' then
186 report "execute " & to_hstring(rin.e.nia);
192 r_out.read1_reg <= insn_ra(d_in.insn);
193 r_out.read2_reg <= insn_rb(d_in.insn);
194 r_out.read3_reg <= insn_rs(d_in.insn);
196 c_out.read <= d_in.decode.input_cr;
198 decode2_1: process(all)
199 variable v : reg_type;
200 variable mul_a : std_ulogic_vector(63 downto 0);
201 variable mul_b : std_ulogic_vector(63 downto 0);
202 variable decoded_reg_a : decode_input_reg_t;
203 variable decoded_reg_b : decode_input_reg_t;
204 variable decoded_reg_c : decode_input_reg_t;
205 variable signed_division: std_ulogic;
209 v.e := Decode2ToExecute1Init;
210 v.l := Decode2ToLoadStore1Init;
211 v.m := Decode2ToMultiplyInit;
212 v.d := Decode2ToDividerInit;
214 mul_a := (others => '0');
215 mul_b := (others => '0');
217 --v.e.input_cr := d_in.decode.input_cr;
218 --v.m.input_cr := d_in.decode.input_cr;
219 --v.e.output_cr := d_in.decode.output_cr;
221 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data);
222 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data);
223 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
225 r_out.read1_enable <= decoded_reg_a.reg_valid;
226 r_out.read2_enable <= decoded_reg_b.reg_valid;
227 r_out.read3_enable <= decoded_reg_c.reg_valid;
231 v.e.insn_type := d_in.decode.insn_type;
232 v.e.read_reg1 := decoded_reg_a.reg;
233 v.e.read_data1 := decoded_reg_a.data;
234 v.e.read_reg2 := decoded_reg_b.reg;
235 v.e.read_data2 := decoded_reg_b.data;
236 v.e.read_data3 := decoded_reg_c.data;
237 v.e.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
238 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
239 v.e.cr := c_in.read_cr_data;
240 v.e.invert_a := d_in.decode.invert_a;
241 v.e.invert_out := d_in.decode.invert_out;
242 v.e.input_carry := d_in.decode.input_carry;
243 v.e.output_carry := d_in.decode.output_carry;
244 v.e.is_32bit := d_in.decode.is_32bit;
245 v.e.is_signed := d_in.decode.is_signed;
246 if d_in.decode.lr = '1' then
247 v.e.lr := insn_lk(d_in.insn);
249 v.e.insn := d_in.insn;
252 v.m.insn_type := d_in.decode.insn_type;
253 mul_a := decoded_reg_a.data;
254 mul_b := decoded_reg_b.data;
255 v.m.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
256 v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
258 if d_in.decode.is_32bit = '1' then
259 if d_in.decode.is_signed = '1' then
260 v.m.data1 := (others => mul_a(31));
261 v.m.data1(31 downto 0) := mul_a(31 downto 0);
262 v.m.data2 := (others => mul_b(31));
263 v.m.data2(31 downto 0) := mul_b(31 downto 0);
265 v.m.data1 := '0' & x"00000000" & mul_a(31 downto 0);
266 v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
269 if d_in.decode.is_signed = '1' then
270 v.m.data1 := mul_a(63) & mul_a;
271 v.m.data2 := mul_b(63) & mul_b;
273 v.m.data1 := '0' & mul_a;
274 v.m.data2 := '0' & mul_b;
279 -- PPC divide and modulus instruction words have these bits in
280 -- the bottom 11 bits: o1dns 010t1 r
281 -- where o = OE for div instrs, signedness for mod instrs
282 -- d = 1 for div*, 0 for mod*
283 -- n = 1 for normal, 0 for extended (dividend << 32/64)
284 -- s = 1 for signed, 0 for unsigned (for div*)
285 -- t = 1 for 32-bit, 0 for 64-bit
286 -- r = RC bit (record condition code)
287 v.d.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
288 v.d.is_modulus := not d_in.insn(8);
289 v.d.is_32bit := d_in.insn(2);
290 if d_in.insn(8) = '1' then
291 signed_division := d_in.insn(6);
293 signed_division := d_in.insn(10);
295 v.d.is_signed := signed_division;
296 if d_in.insn(2) = '0' then
298 if d_in.insn(8) = '1' and d_in.insn(7) = '0' then
299 v.d.is_extended := '1';
301 v.d.dividend := decoded_reg_a.data;
302 v.d.divisor := decoded_reg_b.data;
305 if d_in.insn(8) = '1' and d_in.insn(7) = '0' then -- extended forms
306 v.d.dividend := decoded_reg_a.data(31 downto 0) & x"00000000";
307 elsif signed_division = '1' and decoded_reg_a.data(31) = '1' then
308 -- sign extend to 64 bits
309 v.d.dividend := x"ffffffff" & decoded_reg_a.data(31 downto 0);
311 v.d.dividend := x"00000000" & decoded_reg_a.data(31 downto 0);
313 if signed_division = '1' and decoded_reg_b.data(31) = '1' then
314 v.d.divisor := x"ffffffff" & decoded_reg_b.data(31 downto 0);
316 v.d.divisor := x"00000000" & decoded_reg_b.data(31 downto 0);
319 v.d.rc := decode_rc(d_in.decode.rc, d_in.insn);
322 v.l.update_reg := decoded_reg_a.reg;
323 v.l.addr1 := decoded_reg_a.data;
324 v.l.addr2 := decoded_reg_b.data;
325 v.l.data := decoded_reg_c.data;
326 v.l.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
328 if d_in.decode.insn_type = OP_LOAD then
334 case d_in.decode.length is
336 v.l.length := "0001";
338 v.l.length := "0010";
340 v.l.length := "0100";
342 v.l.length := "1000";
344 v.l.length := "0000";
347 v.l.byte_reverse := d_in.decode.byte_reverse;
348 v.l.sign_extend := d_in.decode.sign_extend;
349 v.l.update := d_in.decode.update;
352 control_valid_in <= d_in.valid;
353 control_sgl_pipe <= d_in.decode.sgl_pipe;
355 gpr_write_valid <= '1' when d_in.decode.output_reg_a /= NONE else '0';
356 gpr_write <= decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
358 gpr_a_read_valid <= decoded_reg_a.reg_valid;
359 gpr_a_read <= decoded_reg_a.reg;
361 gpr_b_read_valid <= decoded_reg_b.reg_valid;
362 gpr_b_read <= decoded_reg_b.reg;
364 gpr_c_read_valid <= decoded_reg_c.reg_valid;
365 gpr_c_read <= decoded_reg_c.reg;
371 case d_in.decode.unit is
373 v.e.valid := control_valid_out;
375 v.l.valid := control_valid_out;
377 v.m.valid := control_valid_out;
379 v.d.valid := control_valid_out;
381 v.e.valid := control_valid_out;
382 v.e.insn_type := OP_ILLEGAL;
386 v.e := Decode2ToExecute1Init;
387 v.l := Decode2ToLoadStore1Init;
388 v.m := Decode2ToMultiplyInit;
389 v.d := Decode2ToDividerInit;
401 end architecture behaviour;