decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12         port (
  13                 clk   : in std_ulogic;
  14                 rst   : in std_ulogic;
  15
  16                 complete_in : in std_ulogic;
  17                 stall_in : in std_ulogic;
  18                 stall_out : out std_ulogic;
  19
  20                 stopped_out : out std_ulogic;
  21
  22                 flush_in: in std_ulogic;
  23
  24                 d_in  : in Decode1ToDecode2Type;
  25
  26                 e_out : out Decode2ToExecute1Type;
  27                 l_out : out Decode2ToLoadstore1Type;
  28
  29                 r_in  : in RegisterFileToDecode2Type;
  30                 r_out : out Decode2ToRegisterFileType;
  31
  32                 c_in  : in CrFileToDecode2Type;
  33                 c_out : out Decode2ToCrFileType
  34         );
  35 end entity decode2;
  36
  37 architecture behaviour of decode2 is
  38         type reg_type is record
  39                 e : Decode2ToExecute1Type;
  40                 l : Decode2ToLoadstore1Type;
  41         end record;
  42
  43         signal r, rin : reg_type;
  44
  45         type decode_input_reg_t is record
  46                 reg_valid : std_ulogic;
  47                 reg       : gspr_index_t;
  48                 data      : std_ulogic_vector(63 downto 0);
  49         end record;
  50
  51         type decode_output_reg_t is record
  52                 reg_valid : std_ulogic;
  53                 reg       : gspr_index_t;
  54         end record;
  55
  56         function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  57                                      reg_data : std_ulogic_vector(63 downto 0);
  58                                      ispr : gspr_index_t) return decode_input_reg_t is
  59         begin
  60                 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  61                     assert is_fast_spr(ispr) = '0' report "Decode A says GPR but ISPR says SPR:" &
  62                         to_hstring(ispr) severity failure;
  63                     return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  64                 elsif t = SPR then
  65                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  66                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
  67                     -- operations are single issue.
  68                     --
  69                     assert is_fast_spr(ispr) =  '1' or ispr = "000000"
  70                         report "Decode A says SPR but ISPR is invalid:" &
  71                         to_hstring(ispr) severity failure;
  72                     return (is_fast_spr(ispr), ispr, reg_data);
  73                 else
  74                         return ('0', (others => '0'), (others => '0'));
  75                 end if;
  76         end;
  77
  78         function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  79                                      reg_data : std_ulogic_vector(63 downto 0);
  80                                      ispr : gspr_index_t) return decode_input_reg_t is
  81         begin
  82                 case t is
  83                 when RB =>
  84                     assert is_fast_spr(ispr) = '0' report "Decode B says GPR but ISPR says SPR:" &
  85                         to_hstring(ispr) severity failure;
  86                     return ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
  87                 when CONST_UI =>
  88                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  89                 when CONST_SI =>
  90                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  91                 when CONST_SI_HI =>
  92                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
  93                 when CONST_UI_HI =>
  94                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
  95                 when CONST_LI =>
  96                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
  97                 when CONST_BD =>
  98                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
  99                 when CONST_DS =>
 100                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 101                 when CONST_M1 =>
 102                         return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 103                 when CONST_SH =>
 104                         return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 105                 when CONST_SH32 =>
 106                         return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 107                 when SPR =>
 108                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 109                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
 110                     -- operations are single issue.
 111                     assert is_fast_spr(ispr) = '1' or ispr = "000000"
 112                         report "Decode B says SPR but ISPR is invalid:" &
 113                         to_hstring(ispr) severity failure;
 114                     return (is_fast_spr(ispr), ispr, reg_data);
 115                 when NONE =>
 116                         return ('0', (others => '0'), (others => '0'));
 117                 end case;
 118         end;
 119
 120         function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 121                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 122         begin
 123                 case t is
 124                 when RS =>
 125                         return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 126                 when NONE =>
 127                         return ('0', (others => '0'), (others => '0'));
 128                 end case;
 129         end;
 130
 131         function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 132                                     ispr : gspr_index_t) return decode_output_reg_t is
 133         begin
 134                 case t is
 135                 when RT =>
 136                     return ('1', gpr_to_gspr(insn_rt(insn_in)));
 137                 when RA =>
 138                     return ('1', gpr_to_gspr(insn_ra(insn_in)));
 139                 when SPR =>
 140                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 141                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
 142                     -- operations are single issue.
 143                     assert is_fast_spr(ispr) = '1' or ispr = "000000"
 144                         report "Decode B says SPR but ISPR is invalid:" &
 145                         to_hstring(ispr) severity failure;
 146                     return (is_fast_spr(ispr), ispr);
 147                 when NONE =>
 148                     return ('0', "000000");
 149                 end case;
 150         end;
 151
 152         function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 153         begin
 154                 case t is
 155                 when RC =>
 156                         return insn_rc(insn_in);
 157                 when ONE =>
 158                         return '1';
 159                 when NONE =>
 160                         return '0';
 161                 end case;
 162         end;
 163
 164         -- For now, use "rc" in the decode table to decide whether oe exists.
 165         -- This is not entirely correct architecturally: For mulhd and
 166         -- mulhdu, the OE field is reserved. It remains to be seen what an
 167         -- actual POWER9 does if we set it on those instructions, for now we
 168         -- test that further down when assigning to the multiplier oe input.
 169         --
 170         function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 171         begin
 172                 case t is
 173                 when RC =>
 174                         return insn_oe(insn_in);
 175                 when OTHERS =>
 176                         return '0';
 177                 end case;
 178         end;
 179
 180         -- issue control signals
 181         signal control_valid_in : std_ulogic;
 182         signal control_valid_out : std_ulogic;
 183         signal control_sgl_pipe : std_logic;
 184
 185         signal gpr_write_valid : std_ulogic;
 186         signal gpr_write : gspr_index_t;
 187
 188         signal gpr_a_read_valid : std_ulogic;
 189         signal gpr_a_read :gspr_index_t;
 190
 191         signal gpr_b_read_valid : std_ulogic;
 192         signal gpr_b_read : gspr_index_t;
 193
 194         signal gpr_c_read_valid : std_ulogic;
 195         signal gpr_c_read : gpr_index_t;
 196
 197         signal cr_write_valid : std_ulogic;
 198 begin
 199         control_0: entity work.control
 200         generic map (
 201                 PIPELINE_DEPTH => 1
 202         )
 203         port map (
 204                 clk         => clk,
 205                 rst         => rst,
 206
 207                 complete_in => complete_in,
 208                 valid_in    => control_valid_in,
 209                 stall_in    => stall_in,
 210                 flush_in    => flush_in,
 211                 sgl_pipe_in => control_sgl_pipe,
 212                 stop_mark_in => d_in.stop_mark,
 213
 214                 gpr_write_valid_in => gpr_write_valid,
 215                 gpr_write_in       => gpr_write,
 216
 217                 gpr_a_read_valid_in  => gpr_a_read_valid,
 218                 gpr_a_read_in        => gpr_a_read,
 219
 220                 gpr_b_read_valid_in  => gpr_b_read_valid,
 221                 gpr_b_read_in        => gpr_b_read,
 222
 223                 gpr_c_read_valid_in  => gpr_c_read_valid,
 224                 gpr_c_read_in        => gpr_c_read,
 225
 226                 cr_read_in           => d_in.decode.input_cr,
 227                 cr_write_in           => cr_write_valid,
 228
 229                 valid_out   => control_valid_out,
 230                 stall_out   => stall_out,
 231                 stopped_out => stopped_out
 232         );
 233
 234         decode2_0: process(clk)
 235         begin
 236                 if rising_edge(clk) then
 237                         if rin.e.valid = '1' or rin.l.valid = '1' then
 238                                 report "execute " & to_hstring(rin.e.nia);
 239                         end if;
 240                         r <= rin;
 241                 end if;
 242         end process;
 243
 244         r_out.read1_reg <= gpr_or_spr_to_gspr(insn_ra(d_in.insn), d_in.ispr1);
 245         r_out.read2_reg <= gpr_or_spr_to_gspr(insn_rb(d_in.insn), d_in.ispr2);
 246         r_out.read3_reg <= insn_rs(d_in.insn);
 247
 248         c_out.read <= d_in.decode.input_cr;
 249
 250         decode2_1: process(all)
 251                 variable v : reg_type;
 252                 variable mul_a : std_ulogic_vector(63 downto 0);
 253                 variable mul_b : std_ulogic_vector(63 downto 0);
 254                 variable decoded_reg_a : decode_input_reg_t;
 255                 variable decoded_reg_b : decode_input_reg_t;
 256                 variable decoded_reg_c : decode_input_reg_t;
 257                 variable decoded_reg_o : decode_output_reg_t;
 258                 variable length : std_ulogic_vector(3 downto 0);
 259         begin
 260                 v := r;
 261
 262                 v.e := Decode2ToExecute1Init;
 263                 v.l := Decode2ToLoadStore1Init;
 264
 265                 mul_a := (others => '0');
 266                 mul_b := (others => '0');
 267
 268                 --v.e.input_cr := d_in.decode.input_cr;
 269                 --v.e.output_cr := d_in.decode.output_cr;
 270
 271                 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1);
 272                 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 273                 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 274                 decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
 275
 276                 r_out.read1_enable <= decoded_reg_a.reg_valid;
 277                 r_out.read2_enable <= decoded_reg_b.reg_valid;
 278                 r_out.read3_enable <= decoded_reg_c.reg_valid;
 279
 280                 case d_in.decode.length is
 281                 when is1B =>
 282                         length := "0001";
 283                 when is2B =>
 284                         length := "0010";
 285                 when is4B =>
 286                         length := "0100";
 287                 when is8B =>
 288                         length := "1000";
 289                 when NONE =>
 290                         length := "0000";
 291                 end case;
 292
 293                 -- execute unit
 294                 v.e.nia := d_in.nia;
 295                 v.e.insn_type := d_in.decode.insn_type;
 296                 v.e.read_reg1 := decoded_reg_a.reg;
 297                 v.e.read_data1 := decoded_reg_a.data;
 298                 v.e.read_reg2 := decoded_reg_b.reg;
 299                 v.e.read_data2 := decoded_reg_b.data;
 300                 v.e.read_data3 := decoded_reg_c.data;
 301                 v.e.write_reg := decoded_reg_o.reg;
 302                 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 303                 if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
 304                         v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 305                 end if;
 306                 v.e.cr := c_in.read_cr_data;
 307                 v.e.xerc := c_in.read_xerc_data;
 308                 v.e.invert_a := d_in.decode.invert_a;
 309                 v.e.invert_out := d_in.decode.invert_out;
 310                 v.e.input_carry := d_in.decode.input_carry;
 311                 v.e.output_carry := d_in.decode.output_carry;
 312                 v.e.is_32bit := d_in.decode.is_32bit;
 313                 v.e.is_signed := d_in.decode.is_signed;
 314                 if d_in.decode.lr = '1' then
 315                         v.e.lr := insn_lk(d_in.insn);
 316                 end if;
 317                 v.e.insn := d_in.insn;
 318                 v.e.data_len := length;
 319
 320                 -- load/store unit
 321                 v.l.update_reg := gspr_to_gpr(decoded_reg_a.reg);
 322                 v.l.addr1 := decoded_reg_a.data;
 323                 v.l.addr2 := decoded_reg_b.data;
 324                 v.l.data := decoded_reg_c.data;
 325                 v.l.write_reg := gspr_to_gpr(decoded_reg_o.reg);
 326
 327                 if d_in.decode.insn_type = OP_LOAD then
 328                         v.l.load := '1';
 329                 else
 330                         v.l.load := '0';
 331                 end if;
 332
 333                 v.l.length := length;
 334                 v.l.byte_reverse := d_in.decode.byte_reverse;
 335                 v.l.sign_extend := d_in.decode.sign_extend;
 336                 v.l.update := d_in.decode.update;
 337                 v.l.xerc := c_in.read_xerc_data;
 338
 339                 -- issue control
 340                 control_valid_in <= d_in.valid;
 341                 control_sgl_pipe <= d_in.decode.sgl_pipe;
 342
 343                 gpr_write_valid <= decoded_reg_o.reg_valid;
 344                 gpr_write <= decoded_reg_o.reg;
 345
 346                 gpr_a_read_valid <= decoded_reg_a.reg_valid;
 347                 gpr_a_read <= decoded_reg_a.reg;
 348
 349                 gpr_b_read_valid <= decoded_reg_b.reg_valid;
 350                 gpr_b_read <= decoded_reg_b.reg;
 351
 352                 gpr_c_read_valid <= decoded_reg_c.reg_valid;
 353                 gpr_c_read <= gspr_to_gpr(decoded_reg_c.reg);
 354
 355                 cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 356
 357                 v.e.valid := '0';
 358                 v.l.valid := '0';
 359                 case d_in.decode.unit is
 360                 when ALU =>
 361                         v.e.valid := control_valid_out;
 362                 when LDST =>
 363                         v.l.valid := control_valid_out;
 364                 when NONE =>
 365                         v.e.valid := control_valid_out;
 366                         v.e.insn_type := OP_ILLEGAL;
 367                 end case;
 368
 369                 if rst = '1' then
 370                         v.e := Decode2ToExecute1Init;
 371                         v.l := Decode2ToLoadStore1Init;
 372                 end if;
 373
 374                 -- Update registers
 375                 rin <= v;
 376
 377                 -- Update outputs
 378                 e_out <= r.e;
 379                 l_out <= r.l;
 380         end process;
 381 end architecture behaviour;