decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12         port (
  13                 clk   : in std_ulogic;
  14                 rst   : in std_ulogic;
  15
  16                 complete_in : in std_ulogic;
  17                 stall_out : out std_ulogic;
  18
  19                 stopped_out : out std_ulogic;
  20
  21                 flush_in: in std_ulogic;
  22
  23                 d_in  : in Decode1ToDecode2Type;
  24
  25                 e_out : out Decode2ToExecute1Type;
  26                 m_out : out Decode2ToMultiplyType;
  27                 d_out : out Decode2ToDividerType;
  28                 l_out : out Decode2ToLoadstore1Type;
  29
  30                 r_in  : in RegisterFileToDecode2Type;
  31                 r_out : out Decode2ToRegisterFileType;
  32
  33                 c_in  : in CrFileToDecode2Type;
  34                 c_out : out Decode2ToCrFileType
  35         );
  36 end entity decode2;
  37
  38 architecture behaviour of decode2 is
  39         type reg_type is record
  40                 e : Decode2ToExecute1Type;
  41                 m : Decode2ToMultiplyType;
  42                 d : Decode2ToDividerType;
  43                 l : Decode2ToLoadstore1Type;
  44         end record;
  45
  46         signal r, rin : reg_type;
  47
  48         type decode_input_reg_t is record
  49                 reg_valid : std_ulogic;
  50                 reg       : std_ulogic_vector(4 downto 0);
  51                 data      : std_ulogic_vector(63 downto 0);
  52         end record;
  53
  54         function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  55                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  56         begin
  57                 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  58                         return ('1', insn_ra(insn_in), reg_data);
  59                 else
  60                         return ('0', (others => '0'), (others => '0'));
  61                 end if;
  62         end;
  63
  64         function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  65                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  66         begin
  67                 case t is
  68                 when RB =>
  69                         return ('1', insn_rb(insn_in), reg_data);
  70                 when CONST_UI =>
  71                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  72                 when CONST_SI =>
  73                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  74                 when CONST_SI_HI =>
  75                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
  76                 when CONST_UI_HI =>
  77                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
  78                 when CONST_LI =>
  79                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
  80                 when CONST_BD =>
  81                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
  82                 when CONST_DS =>
  83                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
  84                 when CONST_M1 =>
  85                         return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
  86                 when CONST_SH =>
  87                         return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
  88                 when CONST_SH32 =>
  89                         return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
  90                 when NONE =>
  91                         return ('0', (others => '0'), (others => '0'));
  92                 end case;
  93         end;
  94
  95         function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
  96                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  97         begin
  98                 case t is
  99                 when RS =>
 100                         return ('1', insn_rs(insn_in), reg_data);
 101                 when NONE =>
 102                         return ('0', (others => '0'), (others => '0'));
 103                 end case;
 104         end;
 105
 106         function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 107         begin
 108                 case t is
 109                 when RT =>
 110                         return insn_rt(insn_in);
 111                 when RA =>
 112                         return insn_ra(insn_in);
 113                 when NONE =>
 114                         return "00000";
 115                 end case;
 116         end;
 117
 118         function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 119         begin
 120                 case t is
 121                 when RC =>
 122                         return insn_rc(insn_in);
 123                 when ONE =>
 124                         return '1';
 125                 when NONE =>
 126                         return '0';
 127                 end case;
 128         end;
 129
 130         signal control_valid_in : std_ulogic;
 131         signal control_valid_out : std_ulogic;
 132         signal control_sgl_pipe : std_logic;
 133 begin
 134         control_0: entity work.control
 135         generic map (
 136                 PIPELINE_DEPTH => 2
 137         )
 138         port map (
 139                 clk         => clk,
 140                 rst         => rst,
 141
 142                 complete_in => complete_in,
 143                 valid_in    => control_valid_in,
 144                 flush_in    => flush_in,
 145                 sgl_pipe_in => control_sgl_pipe,
 146                 stop_mark_in => d_in.stop_mark,
 147
 148                 valid_out   => control_valid_out,
 149                 stall_out   => stall_out,
 150                 stopped_out => stopped_out
 151         );
 152
 153         decode2_0: process(clk)
 154         begin
 155                 if rising_edge(clk) then
 156                         if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' or rin.d.valid = '1' then
 157                                 report "execute " & to_hstring(rin.e.nia);
 158                         end if;
 159                         r <= rin;
 160                 end if;
 161         end process;
 162
 163         r_out.read1_reg <= insn_ra(d_in.insn);
 164         r_out.read2_reg <= insn_rb(d_in.insn);
 165         r_out.read3_reg <= insn_rs(d_in.insn);
 166
 167         c_out.read <= d_in.decode.input_cr;
 168
 169         decode2_1: process(all)
 170                 variable v : reg_type;
 171                 variable mul_a : std_ulogic_vector(63 downto 0);
 172                 variable mul_b : std_ulogic_vector(63 downto 0);
 173                 variable decoded_reg_a : decode_input_reg_t;
 174                 variable decoded_reg_b : decode_input_reg_t;
 175                 variable decoded_reg_c : decode_input_reg_t;
 176                 variable signed_division: std_ulogic;
 177         begin
 178                 v := r;
 179
 180                 v.e := Decode2ToExecute1Init;
 181                 v.l := Decode2ToLoadStore1Init;
 182                 v.m := Decode2ToMultiplyInit;
 183                 v.d := Decode2ToDividerInit;
 184
 185                 mul_a := (others => '0');
 186                 mul_b := (others => '0');
 187
 188                 --v.e.input_cr := d_in.decode.input_cr;
 189                 --v.m.input_cr := d_in.decode.input_cr;
 190                 --v.e.output_cr := d_in.decode.output_cr;
 191
 192                 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data);
 193                 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data);
 194                 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 195
 196                 r_out.read1_enable <= decoded_reg_a.reg_valid;
 197                 r_out.read2_enable <= decoded_reg_b.reg_valid;
 198                 r_out.read3_enable <= decoded_reg_c.reg_valid;
 199
 200                 -- execute unit
 201                 v.e.nia := d_in.nia;
 202                 v.e.insn_type := d_in.decode.insn_type;
 203                 v.e.read_reg1 := decoded_reg_a.reg;
 204                 v.e.read_data1 := decoded_reg_a.data;
 205                 v.e.read_reg2 := decoded_reg_b.reg;
 206                 v.e.read_data2 := decoded_reg_b.data;
 207                 v.e.read_data3 := decoded_reg_c.data;
 208                 v.e.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 209                 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 210                 v.e.cr := c_in.read_cr_data;
 211                 v.e.invert_a := d_in.decode.invert_a;
 212                 v.e.invert_out := d_in.decode.invert_out;
 213                 v.e.input_carry := d_in.decode.input_carry;
 214                 v.e.output_carry := d_in.decode.output_carry;
 215                 v.e.is_32bit := d_in.decode.is_32bit;
 216                 v.e.is_signed := d_in.decode.is_signed;
 217                 if d_in.decode.lr = '1' then
 218                         v.e.lr := insn_lk(d_in.insn);
 219                 end if;
 220                 v.e.insn := d_in.insn;
 221
 222                 -- multiply unit
 223                 v.m.insn_type := d_in.decode.insn_type;
 224                 mul_a := decoded_reg_a.data;
 225                 mul_b := decoded_reg_b.data;
 226                 v.m.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 227                 v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
 228
 229                 if d_in.decode.is_32bit = '1' then
 230                         if d_in.decode.is_signed = '1' then
 231                                 v.m.data1 := (others => mul_a(31));
 232                                 v.m.data1(31 downto 0) := mul_a(31 downto 0);
 233                                 v.m.data2 := (others => mul_b(31));
 234                                 v.m.data2(31 downto 0) := mul_b(31 downto 0);
 235                         else
 236                                 v.m.data1 := '0' & x"00000000" & mul_a(31 downto 0);
 237                                 v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
 238                         end if;
 239                 else
 240                         if d_in.decode.is_signed = '1' then
 241                                 v.m.data1 := mul_a(63) & mul_a;
 242                                 v.m.data2 := mul_b(63) & mul_b;
 243                         else
 244                                 v.m.data1 := '0' & mul_a;
 245                                 v.m.data2 := '0' & mul_b;
 246                         end if;
 247                 end if;
 248
 249                 -- divide unit
 250                 -- PPC divide and modulus instruction words have these bits in
 251                 -- the bottom 11 bits: o1dns 010t1 r
 252                 -- where o = OE for div instrs, signedness for mod instrs
 253                 --       d = 1 for div*, 0 for mod*
 254                 --       n = 1 for normal, 0 for extended (dividend << 32/64)
 255                 --       s = 1 for signed, 0 for unsigned (for div*)
 256                 --       t = 1 for 32-bit, 0 for 64-bit
 257                 --       r = RC bit (record condition code)
 258                 v.d.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 259                 v.d.is_modulus := not d_in.insn(8);
 260                 v.d.is_32bit := d_in.insn(2);
 261                 if d_in.insn(8) = '1' then
 262                         signed_division := d_in.insn(6);
 263                 else
 264                         signed_division := d_in.insn(10);
 265                 end if;
 266                 v.d.is_signed := signed_division;
 267                 if d_in.insn(2) = '0' then
 268                         -- 64-bit forms
 269                         if d_in.insn(8) = '1' and d_in.insn(7) = '0' then
 270                                 v.d.is_extended := '1';
 271                         end if;
 272                         v.d.dividend := decoded_reg_a.data;
 273                         v.d.divisor := decoded_reg_b.data;
 274                 else
 275                         -- 32-bit forms
 276                         if d_in.insn(8) = '1' and d_in.insn(7) = '0' then   -- extended forms
 277                                 v.d.dividend := decoded_reg_a.data(31 downto 0) & x"00000000";
 278                         elsif signed_division = '1' and decoded_reg_a.data(31) = '1' then
 279                                 -- sign extend to 64 bits
 280                                 v.d.dividend := x"ffffffff" & decoded_reg_a.data(31 downto 0);
 281                         else
 282                                 v.d.dividend := x"00000000" & decoded_reg_a.data(31 downto 0);
 283                         end if;
 284                         if signed_division = '1' and decoded_reg_b.data(31) = '1' then
 285                                 v.d.divisor := x"ffffffff" & decoded_reg_b.data(31 downto 0);
 286                         else
 287                                 v.d.divisor := x"00000000" & decoded_reg_b.data(31 downto 0);
 288                         end if;
 289                 end if;
 290                 v.d.rc := decode_rc(d_in.decode.rc, d_in.insn);
 291
 292                 -- load/store unit
 293                 v.l.update_reg := decoded_reg_a.reg;
 294                 v.l.addr1 := decoded_reg_a.data;
 295                 v.l.addr2 := decoded_reg_b.data;
 296                 v.l.data := decoded_reg_c.data;
 297                 v.l.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 298
 299                 if d_in.decode.insn_type = OP_LOAD then
 300                         v.l.load := '1';
 301                 else
 302                         v.l.load := '0';
 303                 end if;
 304
 305                 case d_in.decode.length is
 306                 when is1B =>
 307                         v.l.length := "0001";
 308                 when is2B =>
 309                         v.l.length := "0010";
 310                 when is4B =>
 311                         v.l.length := "0100";
 312                 when is8B =>
 313                         v.l.length := "1000";
 314                 when NONE =>
 315                         v.l.length := "0000";
 316                 end case;
 317
 318                 v.l.byte_reverse := d_in.decode.byte_reverse;
 319                 v.l.sign_extend := d_in.decode.sign_extend;
 320                 v.l.update := d_in.decode.update;
 321
 322                 -- issue control
 323                 control_valid_in <= d_in.valid;
 324                 control_sgl_pipe <= d_in.decode.sgl_pipe;
 325
 326                 v.e.valid := '0';
 327                 v.m.valid := '0';
 328                 v.d.valid := '0';
 329                 v.l.valid := '0';
 330                 case d_in.decode.unit is
 331                 when ALU =>
 332                         v.e.valid := control_valid_out;
 333                 when LDST =>
 334                         v.l.valid := control_valid_out;
 335                 when MUL =>
 336                         v.m.valid := control_valid_out;
 337                 when DIV =>
 338                         v.d.valid := control_valid_out;
 339                 when NONE =>
 340                         v.e.valid := control_valid_out;
 341                         v.e.insn_type := OP_ILLEGAL;
 342                 end case;
 343
 344                 if rst = '1' then
 345                         v.e := Decode2ToExecute1Init;
 346                         v.l := Decode2ToLoadStore1Init;
 347                         v.m := Decode2ToMultiplyInit;
 348                         v.d := Decode2ToDividerInit;
 349                 end if;
 350
 351                 -- Update registers
 352                 rin <= v;
 353
 354                 -- Update outputs
 355                 e_out <= r.e;
 356                 l_out <= r.l;
 357                 m_out <= r.m;
 358                 d_out <= r.d;
 359         end process;
 360 end architecture behaviour;