decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12         generic (
  13                 EX1_BYPASS : boolean := true
  14         );
  15         port (
  16                 clk   : in std_ulogic;
  17                 rst   : in std_ulogic;
  18
  19                 complete_in : in std_ulogic;
  20                 stall_in : in std_ulogic;
  21                 stall_out : out std_ulogic;
  22
  23                 stopped_out : out std_ulogic;
  24
  25                 flush_in: in std_ulogic;
  26
  27                 d_in  : in Decode1ToDecode2Type;
  28
  29                 e_out : out Decode2ToExecute1Type;
  30
  31                 r_in  : in RegisterFileToDecode2Type;
  32                 r_out : out Decode2ToRegisterFileType;
  33
  34                 c_in  : in CrFileToDecode2Type;
  35                 c_out : out Decode2ToCrFileType
  36         );
  37 end entity decode2;
  38
  39 architecture behaviour of decode2 is
  40         type reg_type is record
  41                 e : Decode2ToExecute1Type;
  42         end record;
  43
  44         signal r, rin : reg_type;
  45
  46         type decode_input_reg_t is record
  47                 reg_valid : std_ulogic;
  48                 reg       : gspr_index_t;
  49                 data      : std_ulogic_vector(63 downto 0);
  50         end record;
  51
  52         type decode_output_reg_t is record
  53                 reg_valid : std_ulogic;
  54                 reg       : gspr_index_t;
  55         end record;
  56
  57         function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  58                                      reg_data : std_ulogic_vector(63 downto 0);
  59                                      ispr : gspr_index_t) return decode_input_reg_t is
  60         begin
  61                 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
  62                     assert is_fast_spr(ispr) = '0' report "Decode A says GPR but ISPR says SPR:" &
  63                         to_hstring(ispr) severity failure;
  64                     return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
  65                 elsif t = SPR then
  66                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
  67                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
  68                     -- operations are single issue.
  69                     --
  70                     assert is_fast_spr(ispr) =  '1' or ispr = "000000"
  71                         report "Decode A says SPR but ISPR is invalid:" &
  72                         to_hstring(ispr) severity failure;
  73                     return (is_fast_spr(ispr), ispr, reg_data);
  74                 else
  75                         return ('0', (others => '0'), (others => '0'));
  76                 end if;
  77         end;
  78
  79         function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  80                                      reg_data : std_ulogic_vector(63 downto 0);
  81                                      ispr : gspr_index_t) return decode_input_reg_t is
  82                 variable ret : decode_input_reg_t;
  83         begin
  84                 case t is
  85                 when RB =>
  86                     assert is_fast_spr(ispr) = '0' report "Decode B says GPR but ISPR says SPR:" &
  87                         to_hstring(ispr) severity failure;
  88                     ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
  89                 when CONST_UI =>
  90                         ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  91                 when CONST_SI =>
  92                         ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  93                 when CONST_SI_HI =>
  94                         ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
  95                 when CONST_UI_HI =>
  96                         ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
  97                 when CONST_LI =>
  98                         ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
  99                 when CONST_BD =>
 100                         ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 101                 when CONST_DS =>
 102                         ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
 103                 when CONST_DX_HI =>
 104                         ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0000", 64)));
 105                 when CONST_M1 =>
 106                         ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 107                 when CONST_SH =>
 108                         ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
 109                 when CONST_SH32 =>
 110                         ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
 111                 when SPR =>
 112                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 113                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
 114                     -- operations are single issue.
 115                     assert is_fast_spr(ispr) = '1' or ispr = "000000"
 116                         report "Decode B says SPR but ISPR is invalid:" &
 117                         to_hstring(ispr) severity failure;
 118                     ret := (is_fast_spr(ispr), ispr, reg_data);
 119                 when NONE =>
 120                         ret := ('0', (others => '0'), (others => '0'));
 121                 end case;
 122
 123                 return ret;
 124         end;
 125
 126         function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 127                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 128         begin
 129                 case t is
 130                 when RS =>
 131                         return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
 132                 when NONE =>
 133                         return ('0', (others => '0'), (others => '0'));
 134                 end case;
 135         end;
 136
 137         function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
 138                                     ispr : gspr_index_t) return decode_output_reg_t is
 139         begin
 140                 case t is
 141                 when RT =>
 142                     return ('1', gpr_to_gspr(insn_rt(insn_in)));
 143                 when RA =>
 144                     return ('1', gpr_to_gspr(insn_ra(insn_in)));
 145                 when SPR =>
 146                     -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
 147                     -- If it's all 0, we don't treat it as a dependency as slow SPRs
 148                     -- operations are single issue.
 149                     assert is_fast_spr(ispr) = '1' or ispr = "000000"
 150                         report "Decode B says SPR but ISPR is invalid:" &
 151                         to_hstring(ispr) severity failure;
 152                     return (is_fast_spr(ispr), ispr);
 153                 when NONE =>
 154                     return ('0', "000000");
 155                 end case;
 156         end;
 157
 158         function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 159         begin
 160                 case t is
 161                 when RC =>
 162                         return insn_rc(insn_in);
 163                 when ONE =>
 164                         return '1';
 165                 when NONE =>
 166                         return '0';
 167                 end case;
 168         end;
 169
 170         -- For now, use "rc" in the decode table to decide whether oe exists.
 171         -- This is not entirely correct architecturally: For mulhd and
 172         -- mulhdu, the OE field is reserved. It remains to be seen what an
 173         -- actual POWER9 does if we set it on those instructions, for now we
 174         -- test that further down when assigning to the multiplier oe input.
 175         --
 176         function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 177         begin
 178                 case t is
 179                 when RC =>
 180                         return insn_oe(insn_in);
 181                 when OTHERS =>
 182                         return '0';
 183                 end case;
 184         end;
 185
 186         -- issue control signals
 187         signal control_valid_in : std_ulogic;
 188         signal control_valid_out : std_ulogic;
 189         signal control_sgl_pipe : std_logic;
 190
 191         signal gpr_write_valid : std_ulogic;
 192         signal gpr_write : gspr_index_t;
 193         signal gpr_bypassable  : std_ulogic;
 194
 195         signal gpr_a_read_valid : std_ulogic;
 196         signal gpr_a_read :gspr_index_t;
 197         signal gpr_a_bypass : std_ulogic;
 198
 199         signal gpr_b_read_valid : std_ulogic;
 200         signal gpr_b_read : gspr_index_t;
 201         signal gpr_b_bypass : std_ulogic;
 202
 203         signal gpr_c_read_valid : std_ulogic;
 204         signal gpr_c_read : gpr_index_t;
 205         signal gpr_c_bypass : std_ulogic;
 206
 207         signal cr_write_valid : std_ulogic;
 208 begin
 209         control_0: entity work.control
 210         generic map (
 211                 PIPELINE_DEPTH => 1
 212         )
 213         port map (
 214                 clk         => clk,
 215                 rst         => rst,
 216
 217                 complete_in => complete_in,
 218                 valid_in    => control_valid_in,
 219                 stall_in    => stall_in,
 220                 flush_in    => flush_in,
 221                 sgl_pipe_in => control_sgl_pipe,
 222                 stop_mark_in => d_in.stop_mark,
 223
 224                 gpr_write_valid_in => gpr_write_valid,
 225                 gpr_write_in       => gpr_write,
 226                 gpr_bypassable     => gpr_bypassable,
 227
 228                 gpr_a_read_valid_in  => gpr_a_read_valid,
 229                 gpr_a_read_in        => gpr_a_read,
 230
 231                 gpr_b_read_valid_in  => gpr_b_read_valid,
 232                 gpr_b_read_in        => gpr_b_read,
 233
 234                 gpr_c_read_valid_in  => gpr_c_read_valid,
 235                 gpr_c_read_in        => gpr_c_read,
 236
 237                 cr_read_in           => d_in.decode.input_cr,
 238                 cr_write_in           => cr_write_valid,
 239
 240                 valid_out   => control_valid_out,
 241                 stall_out   => stall_out,
 242                 stopped_out => stopped_out,
 243
 244                 gpr_bypass_a => gpr_a_bypass,
 245                 gpr_bypass_b => gpr_b_bypass,
 246                 gpr_bypass_c => gpr_c_bypass
 247         );
 248
 249         decode2_0: process(clk)
 250         begin
 251                 if rising_edge(clk) then
 252                         if rin.e.valid = '1' then
 253                                 report "execute " & to_hstring(rin.e.nia);
 254                         end if;
 255                         r <= rin;
 256                 end if;
 257         end process;
 258
 259         r_out.read1_reg <= gpr_or_spr_to_gspr(insn_ra(d_in.insn), d_in.ispr1);
 260         r_out.read2_reg <= gpr_or_spr_to_gspr(insn_rb(d_in.insn), d_in.ispr2);
 261         r_out.read3_reg <= insn_rs(d_in.insn);
 262
 263         c_out.read <= d_in.decode.input_cr;
 264
 265         decode2_1: process(all)
 266                 variable v : reg_type;
 267                 variable mul_a : std_ulogic_vector(63 downto 0);
 268                 variable mul_b : std_ulogic_vector(63 downto 0);
 269                 variable decoded_reg_a : decode_input_reg_t;
 270                 variable decoded_reg_b : decode_input_reg_t;
 271                 variable decoded_reg_c : decode_input_reg_t;
 272                 variable decoded_reg_o : decode_output_reg_t;
 273                 variable length : std_ulogic_vector(3 downto 0);
 274         begin
 275                 v := r;
 276
 277                 v.e := Decode2ToExecute1Init;
 278
 279                 mul_a := (others => '0');
 280                 mul_b := (others => '0');
 281
 282                 --v.e.input_cr := d_in.decode.input_cr;
 283                 --v.e.output_cr := d_in.decode.output_cr;
 284
 285                 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1);
 286                 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
 287                 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 288                 decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
 289
 290                 r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
 291                 r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
 292                 r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
 293
 294                 case d_in.decode.length is
 295                 when is1B =>
 296                         length := "0001";
 297                 when is2B =>
 298                         length := "0010";
 299                 when is4B =>
 300                         length := "0100";
 301                 when is8B =>
 302                         length := "1000";
 303                 when NONE =>
 304                         length := "0000";
 305                 end case;
 306
 307                 -- execute unit
 308                 v.e.nia := d_in.nia;
 309                 v.e.unit := d_in.decode.unit;
 310                 v.e.insn_type := d_in.decode.insn_type;
 311                 v.e.read_reg1 := decoded_reg_a.reg;
 312                 v.e.read_data1 := decoded_reg_a.data;
 313                 v.e.bypass_data1 := gpr_a_bypass;
 314                 v.e.read_reg2 := decoded_reg_b.reg;
 315                 v.e.read_data2 := decoded_reg_b.data;
 316                 v.e.bypass_data2 := gpr_b_bypass;
 317                 v.e.read_data3 := decoded_reg_c.data;
 318                 v.e.bypass_data3 := gpr_c_bypass;
 319                 v.e.write_reg := decoded_reg_o.reg;
 320                 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 321                 if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
 322                         v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
 323                 end if;
 324                 v.e.cr := c_in.read_cr_data;
 325                 v.e.xerc := c_in.read_xerc_data;
 326                 v.e.invert_a := d_in.decode.invert_a;
 327                 v.e.invert_out := d_in.decode.invert_out;
 328                 v.e.input_carry := d_in.decode.input_carry;
 329                 v.e.output_carry := d_in.decode.output_carry;
 330                 v.e.is_32bit := d_in.decode.is_32bit;
 331                 v.e.is_signed := d_in.decode.is_signed;
 332                 if d_in.decode.lr = '1' then
 333                         v.e.lr := insn_lk(d_in.insn);
 334                 end if;
 335                 v.e.insn := d_in.insn;
 336                 v.e.data_len := length;
 337                 v.e.byte_reverse := d_in.decode.byte_reverse;
 338                 v.e.sign_extend := d_in.decode.sign_extend;
 339                 v.e.update := d_in.decode.update;
 340                 v.e.reserve := d_in.decode.reserve;
 341
 342                 -- issue control
 343                 control_valid_in <= d_in.valid;
 344                 control_sgl_pipe <= d_in.decode.sgl_pipe;
 345
 346                 gpr_write_valid <= decoded_reg_o.reg_valid;
 347                 gpr_write <= decoded_reg_o.reg;
 348                 gpr_bypassable <= '0';
 349                 if EX1_BYPASS and d_in.decode.unit = ALU then
 350                         gpr_bypassable <= '1';
 351                 end if;
 352
 353                 gpr_a_read_valid <= decoded_reg_a.reg_valid;
 354                 gpr_a_read <= decoded_reg_a.reg;
 355
 356                 gpr_b_read_valid <= decoded_reg_b.reg_valid;
 357                 gpr_b_read <= decoded_reg_b.reg;
 358
 359                 gpr_c_read_valid <= decoded_reg_c.reg_valid;
 360                 gpr_c_read <= gspr_to_gpr(decoded_reg_c.reg);
 361
 362                 cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
 363
 364                 v.e.valid := control_valid_out;
 365                 if d_in.decode.unit = NONE then
 366                         v.e.insn_type := OP_ILLEGAL;
 367                 end if;
 368
 369                 if rst = '1' then
 370                         v.e := Decode2ToExecute1Init;
 371                 end if;
 372
 373                 -- Update registers
 374                 rin <= v;
 375
 376                 -- Update outputs
 377                 e_out <= r.e;
 378         end process;
 379 end architecture behaviour;