1 <?xml version=
"1.0" encoding=
"ISO-8859-1" ?>
2 <section niv='
2'
><title>User-defined Log File
</title>
3 <p>A global log file can be generated, logging the proccessing of all the components of the
4 software. This file is customizable, and user can choose which component to log, and the level of
6 <p>Each line in the log file is beginning with the code related to the logged software component:
</p>
8 <row><article><f>FAC
</f></article><def>file access tracing
</def></row>
9 <row><article><f>MCH
</f></article><def>disk cache tracing (used for
<f>.stm
</f>,
<f>.rcx
</f> and
<f>.spef
</f> files)
</def></row>
10 <row><article><f>MCC
</f></article><def>MOSFET characterization
</def></row>
11 <row><article><f>RCN
</f></article><def>RC networks construction
</def></row>
12 <row><article><f>TRC
</f></article><def>RC networks characterization
</def></row>
13 <row><article><f>YAG
</f></article><def>transistor netlist disassembly
</def></row>
14 <row><article><f>TAS
</f></article><def>information related to delay calculation
</def></row>
15 <row><article><f>STM
</f></article><def>information related to delay models
</def></row>
16 <row><article><f>EFG
</f></article><def>spice deck generation
</def></row>
17 <row><article><f>GSP
</f></article><def>automatic stimuli generation
</def></row>
18 <row><article><f>TLF
</f></article><def><f>.tlf
</f> file generation
</def></row>
19 <row><article><f>LIB
</f></article><def><f>.lib
</f> file generation
</def></row>
20 <row><article><f>ERR
</f></article><def>error redirection in log file
</def></row>
21 <row><article><f>PRS
</f></article><def>statistics related to netlist parsing
</def></row>
22 <row><article><f>SPI
</f></article><def>detailed logging of the spice netlist and technology file parser
</def></row>
25 <p>The
<f>avtLogFile
</f> variable activates the creation of the log file. The
<f>avtLogEnable
</f>
26 variable selects the software components to log and the level of log. Please refer to the 'Configuration
27 Variables' chapter for more details.
</p>