distrib/share/tutorials/yagle/dram/dram.net

   1
   2 .include ../techno/bsim4_dummy.hsp
   3
   4 .temp 25
   5
   6 .global vdd
   7 .global vss
   8 .global vddprch
   9
  10 .param g_l=0.1u
  11 .param g_w=0.6u
  12 .param cellcapa=100ff
  13 .param pi_r=5000
  14 .param pi_c=0.5pf
  15
  16
  17 vvdd vdd 0 1v
  18 vvss vss 0 0v
  19 vvddprch vddprch 0 0.6v
  20
  21 .subckt inv i o
  22 + l=0.1u w=0.6u
  23 mn vss i o vss tn l=l w=w
  24 mp vdd i o vdd tp l=l w='w*2'
  25 .ends
  26
  27 .subckt nand a b o
  28 + w=1u l=0.08u
  29 Mn1 o a int vss TN w='w' l=l
  30 Mn2 int b vss vss TN w='w' l=l
  31 Mp1 o a vdd vdd TP w='w*2' l=l
  32 Mp2 o b vdd vdd TP w='w*2' l=l
  33 .ends
  34
  35 .subckt nor a b o
  36 + w=1u l=0.08u
  37 Mp1 o a int vdd TP w='w*2' l=l
  38 Mp2 int b vdd vdd TP w='w*2' l=l
  39 Mn1 o a vss vss TN w='w' l=l
  40 Mn2 o b vss vss TN w='w' l=l
  41 .ends
  42
  43 .subckt delay a o
  44 + w=1u l=0.08u
  45 Mp1 o a int0 vdd TP w='w*2' l=l
  46 Mp2 int0 a int1 vdd TP w='w*2' l=l
  47 Mp3 int1 a vdd vdd TP w='w*2' l=l
  48 Mn1 o a int0s vss TN w='w*2' l=l
  49 Mn2 int0s a int1s vss TN w='w*2' l=l
  50 Mn3 int1s a vss vss TN w='w*2' l=l
  51 .ends
  52
  53 .subckt switch i o cp cn
  54 + w=1u l=0.08u
  55 Mp1 o cp i vdd TP w='w*2' l=l
  56 Mn1 o cn i vss TN w='w' l=l
  57 .ends
  58
  59 .subckt buff i o
  60 xb0 i r inv
  61 xb1 r o inv
  62 .ends
  63
  64 .subckt prech bl blb prch
  65 + w=1u l=0.08u
  66 Mp1 bl prch blb vddprch TP w='w*2' l=l
  67 Mp2 vddprch prch blb vddprch TP w='w*2' l=l
  68 Mp3 vddprch prch bl vddprch TP w='w*2' l=l
  69 .ends
  70
  71 .subckt xor i0 i1 q
  72 + w=1u l=0.08u
  73 Mtr_00012 vdd i1 sig6 vdd TP w='w*2' l=l
  74 Mtr_00011 sig6 sig5 q vdd TP w='w*2' l=l
  75 Mtr_00010 sig6 i0 vdd vdd TP w='w*2' l=l
  76 Mtr_00009 q sig9 sig6 vdd TP w='w*2' l=l
  77 Mtr_00008 vdd i0 sig5 vdd TP w='w*2' l=l
  78 Mtr_00007 sig9 i1 vdd vdd TP w='w*2' l=l
  79 Mtr_00006 vss i0 sig2 vss TN w='w' l=l
  80 Mtr_00005 sig2 i1 q vss TN w='w' l=l
  81 Mtr_00004 q sig5 sig3 vss TN w='w' l=l
  82 Mtr_00003 sig3 sig9 vss vss TN w='w' l=l
  83 Mtr_00002 vss i1 sig9 vss TN w='w' l=l
  84 Mtr_00001 sig5 i0 vss vss TN w='w' l=l
  85 .ends
  86
  87 .subckt sensamp bl0 blb0 bl1 blb1 wlen0 wlen1 prech saen bl blb eq0 eq1 blen
  88
  89 Mn1 bl0 wlen0 bl_in vss TN w='g_w' l=g_l
  90 Mn2 blb0 wlen0 blb_in vss TN w='g_w' l=g_l
  91 Mn3 bl1 wlen1 bl_in vss TN w='g_w' l=g_l
  92 Mn4 blb1 wlen1 blb_in vss TN w='g_w' l=g_l
  93 xprechsa bl_in blb_in prech prech
  94
  95 Mneq0 bl0 eq0 blb0 vss TN w='g_w' l=g_l
  96 Mneq1 bl1 eq1 blb1 vss TN w='g_w' l=g_l
  97
  98 Mn5 bl_in blb_in tozero vss TN w='g_w' l=g_l
  99 Mn6 blb_in bl_in tozero vss TN w='g_w' l=g_l
 100 Mn7 vss saen tozero vss TN w='g_w' l=g_l
 101
 102 Mp8 bl_in blb_in toone vdd TP w='g_w' l=g_l
 103 Mp9 blb_in bl_in toone vdd TP w='g_w' l=g_l
 104 Mp10 vdd saenb toone vdd TP w='g_w' l=g_l
 105
 106 xinvsaen saen saenb inv
 107
 108 Mn11 bl blen bl_in vss TN w='g_w' l=g_l
 109 Mn12 blb blen blb_in vss TN w='g_w' l=g_l
 110
 111 .ends
 112
 113 .subckt pi a b r='pi_r' c='pi_c'
 114 r1 a b 'r'
 115 c1 a 0 'c/2'
 116 c2 b 0 'c/2'
 117 .ends
 118
 119 .subckt cells bl0_up blb0_up bl1_dn blb1_dn wl0 wl1
 120
 121 Mn1 bl0_up wl0 mem00 vss TN w='g_w' l=g_l
 122 cmem00 mem00 0 'cellcapa'
 123 Mn2 blb0_dn wl1 mem01 vss TN w='g_w' l=g_l
 124 cmem01 mem01 0 'cellcapa'
 125 Mn3 blb0_up vss vss vss TN w='g_w' l=g_l
 126 Mn4 bl0_dn vss vss vss TN w='g_w' l=g_l
 127
 128 xpi0 bl0_up bl0_dn pi
 129 xpi0b blb0_up blb0_dn pi
 130
 131 Mn5 bl1_up wl0 mem10 vss TN w='g_w' l=g_l
 132 cmem10 mem10 0 'cellcapa'
 133 Mn6 blb1_dn wl1 mem11 vss TN w='g_w' l=g_l
 134 cmem11 mem11 0 'cellcapa'
 135 Mn7 blb1_up vss vss vss TN w='g_w' l=g_l
 136 Mn8 bl1_dn vss vss vss TN w='g_w' l=g_l
 137
 138 xpi1 bl1_up bl1_dn pi
 139 xpi1b blb1_up blb1_dn pi
 140
 141 .ends
 142
 143 .subckt writecell i in inb wen
 144 xinv i ib inv
 145 xinv i ib0 inv
 146 xinv ib0 ib0b inv
 147 xinvw wen wenb inv
 148 xswitchi ib0b in wenb wen switch
 149 xswitchib ib inb wenb wen switch
 150 .ends
 151
 152 .subckt tristate p n o
 153 + w=1u l=0.08u
 154 Mp1 o p vdd vdd TP w='w*2' l=l
 155 Mn1 o n vss vss TN w='w' l=l
 156 .ends
 157
 158 .subckt latch din dout ck
 159 + w=1u l=0.08u
 160 MM00 din  ck   dat vss tn w='w' l=l
 161 MM01 din  nck   dat vdd tp w='w*2' l=l
 162 Xi1  dat  dout inv
 163 MM00 dat0  nck   dat vss tn w='w' l=l
 164 MM01 dat0  ck   dat vdd tp w='w*2' l=l
 165 Xi2  dout dat0 inv
 166 Xi3  ck nck  inv
 167 .ends
 168
 169 .subckt dram a<0> a<1> din<0> din<1> dout write ck sel
 170
 171 xmcell bl0 blb0 bl1 blb1 wl0 wl1 cells
 172 xsensamp bl0 blb0 bl1 blb1 wlen0 wlen1 prech saen so sob prechb prechb blen sensamp
 173
 174 xnandwrite write ck writeb nand
 175 xinvwrite writeb writebb inv
 176 xbuffw writebb write_in buff
 177
 178 * inputs
 179
 180 xlatmaster0 din<0> dinb<0> ckb latch
 181 xlatslave0 dinb<0> dinbb<0> ck latch
 182
 183 xlatmaster1 din<1> dinb<1> ckb latch
 184 xlatslave1 dinb<1> dinbb<1> ck latch
 185
 186 xinvdin0 dinbb<0> din0b inv
 187 xinvdin1 dinbb<1> din1b inv
 188 xin0 din0b wdin0 wdin0b write_in writecell
 189 xin1 din1b wdin1 wdin1b write_in writecell
 190
 191 xinvsel sel selb inv
 192
 193 xswitchin0 wdin0b so selb sel switch
 194 xswitchin0 wdin0 sob selb sel switch
 195 xswitchin1 wdin1b so sel selb switch
 196 xswitchin1 wdin1 sob sel selb switch
 197
 198 * output
 199 xctrlout sob so ctrl xor
 200 xinvctrl ctrl ctrlb inv
 201 *xnandout so sob ioutctrl nand
 202 xinvout so ioutctrl inv
 203 xswitchctrl ioutctrl iout ctrlb ctrl switch
 204 xinv iout dout inv
 205
 206 * precharge
 207 *xibuff ck prech buff
 208 xdelayprech ck prechi delay w=0.4u
 209 c3 prechi 0 20ff
 210 xdelayprech prechi prech delay w=0.4u
 211 c2 prech 0 20ff
 212 xinvprech prech prechb inv
 213
 214 * decoding
 215 xlatmaster2 a<0> ab<0> ckb latch
 216 xlatslave2 ab<0> abb<0> ck latch
 217 xlatmaster3 a<1> ab<1> ckb latch
 218 xlatslave3 ab<1> abb<1> ck latch
 219 xinvck ck ckb inv
 220 xinvck ckb ckbb inv
 221 xa0 abb<0> ab0 inv
 222 xa1 abb<1> ab1 inv
 223 xa01 ab0 a0 inv
 224 xa11 ab1 a1 inv
 225 xnab0 ab0 ckbb ab0act nand
 226 xnab1 ab1 ckbb ab1act nand
 227 xna0 a0 ckbb a0act nand
 228 xna1 a1 ckbb a1act nand
 229
 230 * wl
 231 xinvab0 ab0act wl0 inv
 232 xinva0 a0act wl1 inv
 233
 234 * wlen
 235 xinvab1 ab1act wlen0 inv
 236 xinva1 a1act wlen1 inv
 237
 238 * saen
 239 xnorsa wlen0 wlen1 presaen nor
 240 xdelay0 presaen saen delay w=0.4u
 241 c1 saen 0 100ff
 242 *xdelay1 saenb saen delay w=0.4u
 243
 244 * blen
 245 xnorsablen wlen0 wlen1 preblen nor
 246 xinvblen preblen blen inv
 247
 248 .ends
 249