divider.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.decode_types.all;
   8
   9 entity divider is
  10     port (
  11         clk   : in std_logic;
  12         rst   : in std_logic;
  13         d_in  : in Decode2ToDividerType;
  14         d_out : out DividerToWritebackType
  15         );
  16 end entity divider;
  17
  18 architecture behaviour of divider is
  19     signal dend       : std_ulogic_vector(128 downto 0);
  20     signal div        : unsigned(63 downto 0);
  21     signal quot       : std_ulogic_vector(63 downto 0);
  22     signal result     : std_ulogic_vector(63 downto 0);
  23     signal sresult    : std_ulogic_vector(63 downto 0);
  24     signal oresult    : std_ulogic_vector(63 downto 0);
  25     signal qbit       : std_ulogic;
  26     signal running    : std_ulogic;
  27     signal signcheck  : std_ulogic;
  28     signal count      : unsigned(6 downto 0);
  29     signal neg_result : std_ulogic;
  30     signal is_modulus : std_ulogic;
  31     signal is_32bit   : std_ulogic;
  32     signal extended   : std_ulogic;
  33     signal is_signed  : std_ulogic;
  34     signal rc         : std_ulogic;
  35     signal write_reg  : std_ulogic_vector(4 downto 0);
  36     signal overflow   : std_ulogic;
  37     signal ovf32      : std_ulogic;
  38     signal did_ovf    : std_ulogic;
  39
  40 begin
  41     divider_0: process(clk)
  42     begin
  43         if rising_edge(clk) then
  44             if rst = '1' then
  45                 dend <= (others => '0');
  46                 div <= (others => '0');
  47                 quot <= (others => '0');
  48                 running <= '0';
  49                 count <= "0000000";
  50             elsif d_in.valid = '1' then
  51                 if d_in.is_extended = '1' and not (d_in.is_signed = '1' and d_in.dividend(63) = '1') then
  52                     dend <= '0' & d_in.dividend & x"0000000000000000";
  53                 else
  54                     dend <= '0' & x"0000000000000000" & d_in.dividend;
  55                 end if;
  56                 div <= unsigned(d_in.divisor);
  57                 quot <= (others => '0');
  58                 write_reg <= d_in.write_reg;
  59                 neg_result <= '0';
  60                 is_modulus <= d_in.is_modulus;
  61                 extended <= d_in.is_extended;
  62                 is_32bit <= d_in.is_32bit;
  63                 is_signed <= d_in.is_signed;
  64                 rc <= d_in.rc;
  65                 count <= "1111111";
  66                 running <= '1';
  67                 overflow <= '0';
  68                 ovf32 <= '0';
  69                 signcheck <= d_in.is_signed and (d_in.dividend(63) or d_in.divisor(63));
  70             elsif signcheck = '1' then
  71                 signcheck <= '0';
  72                 neg_result <= dend(63) xor (div(63) and not is_modulus);
  73                 if dend(63) = '1' then
  74                     if extended = '1' then
  75                         dend <= '0' & std_ulogic_vector(- signed(dend(63 downto 0))) & x"0000000000000000";
  76                     else
  77                         dend <= '0' & x"0000000000000000" & std_ulogic_vector(- signed(dend(63 downto 0)));
  78                     end if;
  79                 end if;
  80                 if div(63) = '1' then
  81                     div <= unsigned(- signed(div));
  82                 end if;
  83             elsif running = '1' then
  84                 if count = "0111111" then
  85                     running <= '0';
  86                 end if;
  87                 overflow <= quot(63);
  88                 if dend(128) = '1' or unsigned(dend(127 downto 64)) >= div then
  89                     ovf32 <= ovf32 or quot(31);
  90                     dend <= std_ulogic_vector(unsigned(dend(127 downto 64)) - div) &
  91                             dend(63 downto 0) & '0';
  92                     quot <= quot(62 downto 0) & '1';
  93                     count <= count + 1;
  94                 elsif dend(128 downto 57) = x"000000000000000000" and count(6 downto 3) /= "0111" then
  95                     -- consume 8 bits of zeroes in one cycle
  96                     ovf32 <= or (ovf32 & quot(31 downto 24));
  97                     dend <= dend(120 downto 0) & x"00";
  98                     quot <= quot(55 downto 0) & x"00";
  99                     count <= count + 8;
 100                 else
 101                     ovf32 <= ovf32 or quot(31);
 102                     dend <= dend(127 downto 0) & '0';
 103                     quot <= quot(62 downto 0) & '0';
 104                     count <= count + 1;
 105                 end if;
 106             else
 107                 count <= "0000000";
 108             end if;
 109         end if;
 110     end process;
 111
 112     divider_1: process(all)
 113     begin
 114         d_out.write_reg_nr <= write_reg;
 115         d_out.rc <= rc;
 116
 117         if is_modulus = '1' then
 118             result <= dend(128 downto 65);
 119         else
 120             result <= quot;
 121         end if;
 122         if neg_result = '1' then
 123             sresult <= std_ulogic_vector(- signed(result));
 124         else
 125             sresult <= result;
 126         end if;
 127         did_ovf <= '0';
 128         if is_32bit = '0' then
 129             did_ovf <= overflow or (is_signed and (sresult(63) xor neg_result));
 130         elsif is_signed = '1' then
 131             if ovf32 = '1' or sresult(32) /= sresult(31) then
 132                 did_ovf <= '1';
 133             end if;
 134         else
 135             did_ovf <= ovf32;
 136         end if;
 137         if did_ovf = '1' then
 138             oresult <= (others => '0');
 139         elsif (is_32bit = '1') and (is_modulus = '0') then
 140             -- 32-bit divisions set the top 32 bits of the result to 0
 141             oresult <= x"00000000" & sresult(31 downto 0);
 142         else
 143             oresult <= sresult;
 144         end if;
 145     end process;
 146
 147     divider_out: process(clk)
 148     begin
 149         if rising_edge(clk) then
 150             d_out.write_reg_data <= oresult;
 151             if count = "1000000" then
 152                 d_out.valid <= '1';
 153                 d_out.write_reg_enable <= '1';
 154             else
 155                 d_out.valid <= '0';
 156                 d_out.write_reg_enable <= '0';
 157             end if;
 158         end if;
 159     end process;
 160
 161 end architecture behaviour;