divider.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.decode_types.all;
   8 use work.crhelpers.all;
   9
  10 entity divider is
  11     port (
  12         clk   : in std_logic;
  13         rst   : in std_logic;
  14         d_in  : in Decode2ToDividerType;
  15         d_out : out DividerToWritebackType
  16         );
  17 end entity divider;
  18
  19 architecture behaviour of divider is
  20     signal dend       : std_ulogic_vector(128 downto 0);
  21     signal div        : unsigned(63 downto 0);
  22     signal quot       : std_ulogic_vector(63 downto 0);
  23     signal result     : std_ulogic_vector(63 downto 0);
  24     signal sresult    : std_ulogic_vector(63 downto 0);
  25     signal oresult    : std_ulogic_vector(63 downto 0);
  26     signal qbit       : std_ulogic;
  27     signal running    : std_ulogic;
  28     signal signcheck  : std_ulogic;
  29     signal count      : unsigned(6 downto 0);
  30     signal neg_result : std_ulogic;
  31     signal is_modulus : std_ulogic;
  32     signal is_32bit   : std_ulogic;
  33     signal extended   : std_ulogic;
  34     signal is_signed  : std_ulogic;
  35     signal rc         : std_ulogic;
  36     signal write_reg  : std_ulogic_vector(4 downto 0);
  37     signal overflow   : std_ulogic;
  38     signal ovf32      : std_ulogic;
  39     signal did_ovf    : std_ulogic;
  40     signal cr_data    : std_ulogic_vector(2 downto 0);
  41
  42 begin
  43     divider_0: process(clk)
  44     begin
  45         if rising_edge(clk) then
  46             if rst = '1' then
  47                 dend <= (others => '0');
  48                 div <= (others => '0');
  49                 quot <= (others => '0');
  50                 running <= '0';
  51                 count <= "0000000";
  52             elsif d_in.valid = '1' then
  53                 if d_in.is_extended = '1' and not (d_in.is_signed = '1' and d_in.dividend(63) = '1') then
  54                     dend <= '0' & d_in.dividend & x"0000000000000000";
  55                 else
  56                     dend <= '0' & x"0000000000000000" & d_in.dividend;
  57                 end if;
  58                 div <= unsigned(d_in.divisor);
  59                 quot <= (others => '0');
  60                 write_reg <= d_in.write_reg;
  61                 neg_result <= '0';
  62                 is_modulus <= d_in.is_modulus;
  63                 extended <= d_in.is_extended;
  64                 is_32bit <= d_in.is_32bit;
  65                 is_signed <= d_in.is_signed;
  66                 rc <= d_in.rc;
  67                 count <= "1111111";
  68                 running <= '1';
  69                 overflow <= '0';
  70                 ovf32 <= '0';
  71                 signcheck <= d_in.is_signed and (d_in.dividend(63) or d_in.divisor(63));
  72             elsif signcheck = '1' then
  73                 signcheck <= '0';
  74                 neg_result <= dend(63) xor (div(63) and not is_modulus);
  75                 if dend(63) = '1' then
  76                     if extended = '1' then
  77                         dend <= '0' & std_ulogic_vector(- signed(dend(63 downto 0))) & x"0000000000000000";
  78                     else
  79                         dend <= '0' & x"0000000000000000" & std_ulogic_vector(- signed(dend(63 downto 0)));
  80                     end if;
  81                 end if;
  82                 if div(63) = '1' then
  83                     div <= unsigned(- signed(div));
  84                 end if;
  85             elsif running = '1' then
  86                 if count = "0111111" then
  87                     running <= '0';
  88                 end if;
  89                 overflow <= quot(63);
  90                 if dend(128) = '1' or unsigned(dend(127 downto 64)) >= div then
  91                     ovf32 <= ovf32 or quot(31);
  92                     dend <= std_ulogic_vector(unsigned(dend(127 downto 64)) - div) &
  93                             dend(63 downto 0) & '0';
  94                     quot <= quot(62 downto 0) & '1';
  95                     count <= count + 1;
  96                 elsif dend(128 downto 57) = x"000000000000000000" and count(6 downto 3) /= "0111" then
  97                     -- consume 8 bits of zeroes in one cycle
  98                     ovf32 <= or (ovf32 & quot(31 downto 24));
  99                     dend <= dend(120 downto 0) & x"00";
 100                     quot <= quot(55 downto 0) & x"00";
 101                     count <= count + 8;
 102                 else
 103                     ovf32 <= ovf32 or quot(31);
 104                     dend <= dend(127 downto 0) & '0';
 105                     quot <= quot(62 downto 0) & '0';
 106                     count <= count + 1;
 107                 end if;
 108             else
 109                 count <= "0000000";
 110             end if;
 111         end if;
 112     end process;
 113
 114     divider_1: process(all)
 115     begin
 116         d_out.write_reg_nr <= write_reg;
 117         d_out.write_cr_mask <= num_to_fxm(0);
 118
 119         if is_modulus = '1' then
 120             result <= dend(128 downto 65);
 121         else
 122             result <= quot;
 123         end if;
 124         if neg_result = '1' then
 125             sresult <= std_ulogic_vector(- signed(result));
 126         else
 127             sresult <= result;
 128         end if;
 129         did_ovf <= '0';
 130         if is_32bit = '0' then
 131             did_ovf <= overflow or (is_signed and (sresult(63) xor neg_result));
 132         elsif is_signed = '1' then
 133             if ovf32 = '1' or sresult(32) /= sresult(31) then
 134                 did_ovf <= '1';
 135             end if;
 136         else
 137             did_ovf <= ovf32;
 138         end if;
 139         if did_ovf = '1' then
 140             oresult <= (others => '0');
 141         elsif (is_32bit = '1') and (is_modulus = '0') then
 142             -- 32-bit divisions set the top 32 bits of the result to 0
 143             oresult <= x"00000000" & sresult(31 downto 0);
 144         else
 145             oresult <= sresult;
 146         end if;
 147
 148         if (did_ovf = '1') or (or (sresult) = '0') then
 149             cr_data <= "001";
 150         elsif (sresult(63) = '1') and not ((is_32bit = '1') and (is_modulus = '0')) then
 151             cr_data <= "100";
 152         else
 153             cr_data <= "010";
 154         end if;
 155     end process;
 156
 157     divider_out: process(clk)
 158     begin
 159         if rising_edge(clk) then
 160             d_out.write_reg_data <= oresult;
 161             d_out.write_cr_data <= cr_data & '0' & x"0000000";
 162             if count = "1000000" then
 163                 d_out.valid <= '1';
 164                 d_out.write_reg_enable <= '1';
 165                 d_out.write_cr_enable <= rc;
 166             else
 167                 d_out.valid <= '0';
 168                 d_out.write_reg_enable <= '0';
 169                 d_out.write_cr_enable <= '0';
 170             end if;
 171         end if;
 172     end process;
 173
 174 end architecture behaviour;