divider.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.decode_types.all;
   8
   9 entity divider is
  10     port (
  11         clk   : in std_logic;
  12         rst   : in std_logic;
  13         d_in  : in Decode2ToDividerType;
  14         d_out : out DividerToWritebackType
  15         );
  16 end entity divider;
  17
  18 architecture behaviour of divider is
  19     signal dend       : std_ulogic_vector(128 downto 0);
  20     signal div        : unsigned(63 downto 0);
  21     signal quot       : std_ulogic_vector(63 downto 0);
  22     signal result     : std_ulogic_vector(63 downto 0);
  23     signal sresult    : std_ulogic_vector(64 downto 0);
  24     signal oresult    : std_ulogic_vector(63 downto 0);
  25     signal running    : std_ulogic;
  26     signal signcheck  : std_ulogic;
  27     signal count      : unsigned(6 downto 0);
  28     signal neg_result : std_ulogic;
  29     signal is_modulus : std_ulogic;
  30     signal is_32bit   : std_ulogic;
  31     signal extended   : std_ulogic;
  32     signal is_signed  : std_ulogic;
  33     signal rc         : std_ulogic;
  34     signal write_reg  : std_ulogic_vector(4 downto 0);
  35     signal overflow   : std_ulogic;
  36     signal ovf32      : std_ulogic;
  37     signal did_ovf    : std_ulogic;
  38     signal oe         : std_ulogic;
  39     signal xerc       : xer_common_t;
  40 begin
  41     divider_0: process(clk)
  42     begin
  43         if rising_edge(clk) then
  44             if rst = '1' then
  45                 dend <= (others => '0');
  46                 div <= (others => '0');
  47                 quot <= (others => '0');
  48                 running <= '0';
  49                 count <= "0000000";
  50             elsif d_in.valid = '1' then
  51                 if d_in.is_extended = '1' and not (d_in.is_signed = '1' and d_in.dividend(63) = '1') then
  52                     dend <= '0' & d_in.dividend & x"0000000000000000";
  53                 else
  54                     dend <= '0' & x"0000000000000000" & d_in.dividend;
  55                 end if;
  56                 div <= unsigned(d_in.divisor);
  57                 quot <= (others => '0');
  58                 write_reg <= d_in.write_reg;
  59                 neg_result <= '0';
  60                 is_modulus <= d_in.is_modulus;
  61                 extended <= d_in.is_extended;
  62                 is_32bit <= d_in.is_32bit;
  63                 is_signed <= d_in.is_signed;
  64                 rc <= d_in.rc;
  65                 oe <= d_in.oe;
  66                 xerc <= d_in.xerc;
  67                 count <= "1111111";
  68                 running <= '1';
  69                 overflow <= '0';
  70                 ovf32 <= '0';
  71                 signcheck <= d_in.is_signed and (d_in.dividend(63) or d_in.divisor(63));
  72             elsif signcheck = '1' then
  73                 signcheck <= '0';
  74                 neg_result <= dend(63) xor (div(63) and not is_modulus);
  75                 if dend(63) = '1' then
  76                     if extended = '1' then
  77                         dend <= '0' & std_ulogic_vector(- signed(dend(63 downto 0))) & x"0000000000000000";
  78                     else
  79                         dend <= '0' & x"0000000000000000" & std_ulogic_vector(- signed(dend(63 downto 0)));
  80                     end if;
  81                 end if;
  82                 if div(63) = '1' then
  83                     div <= unsigned(- signed(div));
  84                 end if;
  85             elsif running = '1' then
  86                 if count = "0111111" then
  87                     running <= '0';
  88                 end if;
  89                 overflow <= quot(63);
  90                 if dend(128) = '1' or unsigned(dend(127 downto 64)) >= div then
  91                     ovf32 <= ovf32 or quot(31);
  92                     dend <= std_ulogic_vector(unsigned(dend(127 downto 64)) - div) &
  93                             dend(63 downto 0) & '0';
  94                     quot <= quot(62 downto 0) & '1';
  95                     count <= count + 1;
  96                 elsif dend(128 downto 57) = x"000000000000000000" and count(6 downto 3) /= "0111" then
  97                     -- consume 8 bits of zeroes in one cycle
  98                     ovf32 <= or (ovf32 & quot(31 downto 24));
  99                     dend <= dend(120 downto 0) & x"00";
 100                     quot <= quot(55 downto 0) & x"00";
 101                     count <= count + 8;
 102                 else
 103                     ovf32 <= ovf32 or quot(31);
 104                     dend <= dend(127 downto 0) & '0';
 105                     quot <= quot(62 downto 0) & '0';
 106                     count <= count + 1;
 107                 end if;
 108             else
 109                 count <= "0000000";
 110             end if;
 111         end if;
 112     end process;
 113
 114     divider_1: process(all)
 115     begin
 116         d_out.write_reg_nr <= write_reg;
 117         d_out.rc <= rc;
 118
 119         if is_modulus = '1' then
 120             result <= dend(128 downto 65);
 121         else
 122             result <= quot;
 123         end if;
 124         if neg_result = '1' then
 125             sresult <= std_ulogic_vector(- signed('0' & result));
 126         else
 127             sresult <= '0' & result;
 128         end if;
 129         did_ovf <= '0';
 130         if is_32bit = '0' then
 131             did_ovf <= overflow or (is_signed and (sresult(64) xor sresult(63)));
 132         elsif is_signed = '1' then
 133             if ovf32 = '1' or sresult(32) /= sresult(31) then
 134                 did_ovf <= '1';
 135             end if;
 136         else
 137             did_ovf <= ovf32;
 138         end if;
 139         if did_ovf = '1' then
 140             oresult <= (others => '0');
 141         elsif (is_32bit = '1') and (is_modulus = '0') then
 142             -- 32-bit divisions set the top 32 bits of the result to 0
 143             oresult <= x"00000000" & sresult(31 downto 0);
 144         else
 145             oresult <= sresult(63 downto 0);
 146         end if;
 147     end process;
 148
 149     divider_out: process(clk)
 150     begin
 151         if rising_edge(clk) then
 152             d_out.valid <= '0';
 153             d_out.write_reg_data <= oresult;
 154             d_out.write_reg_enable <= '0';
 155             d_out.write_xerc_enable <= '0';
 156             d_out.xerc <= xerc;
 157             if count = "1000000" then
 158                 d_out.valid <= '1';
 159                 d_out.write_reg_enable <= '1';
 160                 d_out.write_xerc_enable <= oe;
 161
 162                 -- We must test oe because the RC update code in writeback
 163                 -- will use the xerc value to set CR0:SO so we must not clobber
 164                 -- xerc if OE wasn't set.
 165                 --
 166                 if oe = '1' then
 167                     d_out.xerc.ov <= did_ovf;
 168                     d_out.xerc.ov32 <= did_ovf;
 169                     d_out.xerc.so <= xerc.so or did_ovf;
 170                 end if;
 171             end if;
 172         end if;
 173     end process;
 174
 175 end architecture behaviour;