divider.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.decode_types.all;
   8 use work.crhelpers.all;
   9
  10 entity divider is
  11     port (
  12         clk   : in std_logic;
  13         rst   : in std_logic;
  14         d_in  : in Decode2ToDividerType;
  15         d_out : out DividerToWritebackType
  16         );
  17 end entity divider;
  18
  19 architecture behaviour of divider is
  20     signal dend       : std_ulogic_vector(127 downto 0);
  21     signal div        : unsigned(63 downto 0);
  22     signal quot       : std_ulogic_vector(63 downto 0);
  23     signal result     : std_ulogic_vector(63 downto 0);
  24     signal sresult    : std_ulogic_vector(63 downto 0);
  25     signal qbit       : std_ulogic;
  26     signal running    : std_ulogic;
  27     signal count      : unsigned(6 downto 0);
  28     signal neg_result : std_ulogic;
  29     signal is_modulus : std_ulogic;
  30     signal is_32bit   : std_ulogic;
  31     signal rc         : std_ulogic;
  32     signal write_reg  : std_ulogic_vector(4 downto 0);
  33
  34     function compare_zero(value : std_ulogic_vector(63 downto 0); is_32 : std_ulogic)
  35         return std_ulogic_vector is
  36     begin
  37         if is_32 = '1' then
  38             if value(31) = '1' then
  39                 return "1000";
  40             elsif unsigned(value(30 downto 0)) > 0 then
  41                 return "0100";
  42             else
  43                 return "0010";
  44             end if;
  45         else
  46             if value(63) = '1' then
  47                 return "1000";
  48             elsif unsigned(value(62 downto 0)) > 0 then
  49                 return "0100";
  50             else
  51                 return "0010";
  52             end if;
  53         end if;
  54     end function compare_zero;
  55
  56 begin
  57     divider_0: process(clk)
  58     begin
  59         if rising_edge(clk) then
  60             if rst = '1' then
  61                 dend <= (others => '0');
  62                 div <= (others => '0');
  63                 quot <= (others => '0');
  64                 running <= '0';
  65                 count <= "0000000";
  66             elsif d_in.valid = '1' then
  67                 if d_in.is_extended = '1' then
  68                     dend <= d_in.dividend & x"0000000000000000";
  69                 else
  70                     dend <= x"0000000000000000" & d_in.dividend;
  71                 end if;
  72                 div <= unsigned(d_in.divisor);
  73                 quot <= (others => '0');
  74                 write_reg <= d_in.write_reg;
  75                 neg_result <= d_in.neg_result;
  76                 is_modulus <= d_in.is_modulus;
  77                 is_32bit <= d_in.is_32bit;
  78                 rc <= d_in.rc;
  79                 count <= "0000000";
  80                 running <= '1';
  81             elsif running = '1' then
  82                 if count = "0111111" then
  83                     running <= '0';
  84                 end if;
  85                 if dend(127) = '1' or unsigned(dend(126 downto 63)) >= div then
  86                     dend <= std_ulogic_vector(unsigned(dend(126 downto 63)) - div) &
  87                             dend(62 downto 0) & '0';
  88                     quot <= quot(62 downto 0) & '1';
  89                     count <= count + 1;
  90                 elsif dend(127 downto 56) = x"000000000000000000" and count(5 downto 3) /= "111" then
  91                     -- consume 8 bits of zeroes in one cycle
  92                     dend <= dend(119 downto 0) & x"00";
  93                     quot <= quot(55 downto 0) & x"00";
  94                     count <= count + 8;
  95                 else
  96                     dend <= dend(126 downto 0) & '0';
  97                     quot <= quot(62 downto 0) & '0';
  98                     count <= count + 1;
  99                 end if;
 100             else
 101                 count <= "0000000";
 102             end if;
 103         end if;
 104     end process;
 105
 106     divider_1: process(all)
 107     begin
 108         d_out <= DividerToWritebackInit;
 109         d_out.write_reg_nr <= write_reg;
 110
 111         if is_modulus = '1' then
 112             result <= dend(127 downto 64);
 113         else
 114             result <= quot;
 115         end if;
 116         if neg_result = '1' then
 117             sresult <= std_ulogic_vector(- signed(result));
 118         else
 119             sresult <= result;
 120         end if;
 121         d_out.write_reg_data <= sresult;
 122
 123         if count(6) = '1' then
 124             d_out.valid <= '1';
 125             d_out.write_reg_enable <= '1';
 126             if rc = '1' then
 127                 d_out.write_cr_enable <= '1';
 128                 d_out.write_cr_mask <= num_to_fxm(0);
 129                 d_out.write_cr_data <= compare_zero(sresult, is_32bit) & x"0000000";
 130             end if;
 131         end if;
 132     end process;
 133
 134 end architecture behaviour;