divider.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.decode_types.all;
   8 use work.crhelpers.all;
   9
  10 entity divider is
  11     port (
  12         clk   : in std_logic;
  13         rst   : in std_logic;
  14         d_in  : in Decode2ToDividerType;
  15         d_out : out DividerToWritebackType
  16         );
  17 end entity divider;
  18
  19 architecture behaviour of divider is
  20     signal dend       : std_ulogic_vector(127 downto 0);
  21     signal div        : unsigned(63 downto 0);
  22     signal quot       : std_ulogic_vector(63 downto 0);
  23     signal result     : std_ulogic_vector(63 downto 0);
  24     signal sresult    : std_ulogic_vector(63 downto 0);
  25     signal qbit       : std_ulogic;
  26     signal running    : std_ulogic;
  27     signal signcheck  : std_ulogic;
  28     signal count      : unsigned(6 downto 0);
  29     signal neg_result : std_ulogic;
  30     signal is_modulus : std_ulogic;
  31     signal is_32bit   : std_ulogic;
  32     signal extended   : std_ulogic;
  33     signal rc         : std_ulogic;
  34     signal write_reg  : std_ulogic_vector(4 downto 0);
  35
  36     function compare_zero(value : std_ulogic_vector(63 downto 0); is_32 : std_ulogic)
  37         return std_ulogic_vector is
  38     begin
  39         if is_32 = '1' then
  40             if value(31) = '1' then
  41                 return "1000";
  42             elsif unsigned(value(30 downto 0)) > 0 then
  43                 return "0100";
  44             else
  45                 return "0010";
  46             end if;
  47         else
  48             if value(63) = '1' then
  49                 return "1000";
  50             elsif unsigned(value(62 downto 0)) > 0 then
  51                 return "0100";
  52             else
  53                 return "0010";
  54             end if;
  55         end if;
  56     end function compare_zero;
  57
  58 begin
  59     divider_0: process(clk)
  60     begin
  61         if rising_edge(clk) then
  62             if rst = '1' then
  63                 dend <= (others => '0');
  64                 div <= (others => '0');
  65                 quot <= (others => '0');
  66                 running <= '0';
  67                 count <= "0000000";
  68             elsif d_in.valid = '1' then
  69                 if d_in.is_extended = '1' and not (d_in.is_signed = '1' and d_in.dividend(63) = '1') then
  70                     dend <= d_in.dividend & x"0000000000000000";
  71                 else
  72                     dend <= x"0000000000000000" & d_in.dividend;
  73                 end if;
  74                 div <= unsigned(d_in.divisor);
  75                 quot <= (others => '0');
  76                 write_reg <= d_in.write_reg;
  77                 neg_result <= '0';
  78                 is_modulus <= d_in.is_modulus;
  79                 extended <= d_in.is_extended;
  80                 is_32bit <= d_in.is_32bit;
  81                 rc <= d_in.rc;
  82                 count <= "0000000";
  83                 running <= '1';
  84                 signcheck <= d_in.is_signed and (d_in.dividend(63) or d_in.divisor(63));
  85             elsif signcheck = '1' then
  86                 signcheck <= '0';
  87                 neg_result <= dend(63) xor (div(63) and not is_modulus);
  88                 if dend(63) = '1' then
  89                     if extended = '1' then
  90                         dend <= std_ulogic_vector(- signed(dend(63 downto 0))) & x"0000000000000000";
  91                     else
  92                         dend <= x"0000000000000000" & std_ulogic_vector(- signed(dend(63 downto 0)));
  93                     end if;
  94                 end if;
  95                 if div(63) = '1' then
  96                     div <= unsigned(- signed(div));
  97                 end if;
  98             elsif running = '1' then
  99                 if count = "0111111" then
 100                     running <= '0';
 101                 end if;
 102                 if dend(127) = '1' or unsigned(dend(126 downto 63)) >= div then
 103                     dend <= std_ulogic_vector(unsigned(dend(126 downto 63)) - div) &
 104                             dend(62 downto 0) & '0';
 105                     quot <= quot(62 downto 0) & '1';
 106                     count <= count + 1;
 107                 elsif dend(127 downto 56) = x"000000000000000000" and count(5 downto 3) /= "111" then
 108                     -- consume 8 bits of zeroes in one cycle
 109                     dend <= dend(119 downto 0) & x"00";
 110                     quot <= quot(55 downto 0) & x"00";
 111                     count <= count + 8;
 112                 else
 113                     dend <= dend(126 downto 0) & '0';
 114                     quot <= quot(62 downto 0) & '0';
 115                     count <= count + 1;
 116                 end if;
 117             else
 118                 count <= "0000000";
 119             end if;
 120         end if;
 121     end process;
 122
 123     divider_1: process(all)
 124     begin
 125         d_out <= DividerToWritebackInit;
 126         d_out.write_reg_nr <= write_reg;
 127
 128         if is_modulus = '1' then
 129             result <= dend(127 downto 64);
 130         else
 131             result <= quot;
 132         end if;
 133         if neg_result = '1' then
 134             sresult <= std_ulogic_vector(- signed(result));
 135         else
 136             sresult <= result;
 137         end if;
 138         d_out.write_reg_data <= sresult;
 139
 140         if count(6) = '1' then
 141             d_out.valid <= '1';
 142             d_out.write_reg_enable <= '1';
 143             if rc = '1' then
 144                 d_out.write_cr_enable <= '1';
 145                 d_out.write_cr_mask <= num_to_fxm(0);
 146                 d_out.write_cr_data <= compare_zero(sresult, is_32bit) & x"0000000";
 147             end if;
 148         end if;
 149     end process;
 150
 151 end architecture behaviour;