examples/basic/sel.py

   1 from nmigen import *
   2 from nmigen.cli import main
   3
   4
   5 class FlatGPIO(Elaboratable):
   6     def __init__(self, pins, bus):
   7         self.pins = pins
   8         self.bus  = bus
   9
  10     def elaborate(self, platform):
  11         bus  = self.bus
  12
  13         m = Module()
  14         m.d.comb += bus.r_data.eq(self.pins.word_select(bus.addr, len(bus.r_data)))
  15         with m.If(bus.we):
  16             m.d.sync += self.pins.word_select(bus.addr, len(bus.w_data)).eq(bus.w_data)
  17         return m
  18
  19
  20 if __name__ == "__main__":
  21     bus = Record([
  22         ("addr",   3),
  23         ("r_data", 2),
  24         ("w_data", 2),
  25         ("we",     1),
  26     ])
  27     pins = Signal(8)
  28     gpio = FlatGPIO(pins, bus)
  29     main(gpio, ports=[pins, bus.addr, bus.r_data, bus.w_data, bus.we])