1 # this file has been generated by sv2nmigen
3 from nmigen
import Signal
, Module
, Const
, Cat
, Elaboratable
7 class up_counter(Elaboratable
):
10 #self.clk = Signal() # input
11 #self.reset = Signal() # input
12 self
.counter
= Signal() # output
13 def elaborate(self
, platform
=None):
15 #m.d.comb += self.counter.eq(self.counter_up)
16 m
.d
.comb
+= self
.counter
.eq(self
.counter
+1)
18 #TODO test this on an icestorm compatible FPGA
20 #module up_counter(input logic clk,
24 # reg [3:0] counter_up;
26 # always @(posedge clk or posedge reset)
31 # counter_up <= counter_up + 4'd1;
33 # assign counter = counter_up;