examples/headless-versa-85.py

   1 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2 # This file is Copyright (c) 2022 Raptor Engineering, LLC <support@raptorengineering.com>
   3
   4 from nmigen import *
   5 from nmigen.lib.cdc import ResetSynchronizer
   6 from nmigen_soc import wishbone, memory
   7
   8 from lambdasoc.cpu.minerva import MinervaCPU
   9 from lambdasoc.periph.intc import GenericInterruptController
  10 from lambdasoc.periph.serial import AsyncSerialPeripheral
  11 from lambdasoc.periph.sram import SRAMPeripheral
  12 from lambdasoc.periph.timer import TimerPeripheral
  13 from lambdasoc.periph import Peripheral
  14 from lambdasoc.soc.base import SoC
  15
  16 from gram.core import gramCore
  17 from gram.phy.ecp5ddrphy import ECP5DDRPHY
  18 from gram.modules import MT41K64M16
  19 from gram.frontend.wishbone import gramWishbone
  20
  21 from nmigen_boards.versa_ecp5 import VersaECP5Platform85
  22 from ecp5_crg import ECP5CRG
  23 from uartbridge import UARTBridge
  24 from crg import *
  25
  26 class DDR3SoC(SoC, Elaboratable):
  27     def __init__(self, *,
  28                  ddrphy_addr, dramcore_addr,
  29                  ddr_addr):
  30         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
  31                                          features={"cti", "bte"})
  32
  33         self.crg = ECP5CRG()
  34
  35         self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0))
  36
  37         ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
  38             xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4, "cs":4, "reset":4})
  39         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
  40         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
  41
  42         ddrmodule = MT41K64M16(platform.default_clk_frequency, "1:2")
  43
  44         self.dramcore = DomainRenamer("dramsync")(gramCore(
  45             phy=self.ddrphy,
  46             geom_settings=ddrmodule.geom_settings,
  47             timing_settings=ddrmodule.timing_settings,
  48             clk_freq=platform.default_clk_frequency))
  49         self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
  50
  51         self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
  52         self._decoder.add(self.drambone.bus, addr=ddr_addr)
  53
  54         self.memory_map = self._decoder.bus.memory_map
  55
  56         self.clk_freq = platform.default_clk_frequency
  57
  58     def elaborate(self, platform):
  59         m = Module()
  60
  61         m.submodules.sysclk = self.crg
  62
  63         m.submodules.ub = self.ub
  64
  65         m.submodules.decoder = self._decoder
  66         m.submodules.ddrphy = self.ddrphy
  67         m.submodules.dramcore = self.dramcore
  68         m.submodules.drambone = self.drambone
  69
  70         m.d.comb += [
  71             self.ub.bus.connect(self._decoder.bus),
  72         ]
  73
  74         return m
  75
  76
  77 if __name__ == "__main__":
  78     platform = VersaECP5Platform85()
  79
  80     soc = DDR3SoC(ddrphy_addr=0x00008000, dramcore_addr=0x00009000,
  81         ddr_addr=0x10000000)
  82
  83     soc.build(do_build=True)
  84     platform.build(soc, do_program=True)