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HEAD
port_decl
[sv2nmigen.git]
/
examples
/
test_assignment.py
1
from
nmigen
.
compat
.
sim
import
run_simulation
2
3
import
assignment
4
5
def
tbench
(
dut
):
6
yield
dut
.
i
.
eq
(
1
)
7
yield
8
yield
9
yield
10
yield
dut
.
i
.
eq
(
0
)
11
yield
12
yield
13
yield
14
15
16
def
test_ass
():
17
dut
=
assignment
.
assignment
();
18
run_simulation
(
dut
,
tbench
(
dut
),
vcd_name
=
"test.vcd"
)
19
20
21
if
__name__
==
"__main__"
:
22
test_ass
()