execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true
  16         );
  17     port (
  18         clk   : in std_ulogic;
  19         rst   : in std_ulogic;
  20
  21         -- asynchronous
  22         flush_out : out std_ulogic;
  23         busy_out : out std_ulogic;
  24
  25         e_in  : in Decode2ToExecute1Type;
  26         l_in  : in Loadstore1ToExecute1Type;
  27
  28         ext_irq_in : std_ulogic;
  29
  30         -- asynchronous
  31         l_out : out Execute1ToLoadstore1Type;
  32         f_out : out Execute1ToFetch1Type;
  33
  34         e_out : out Execute1ToWritebackType;
  35
  36         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  37
  38         icache_inval : out std_ulogic;
  39         terminate_out : out std_ulogic;
  40
  41         log_out : out std_ulogic_vector(14 downto 0);
  42         log_rd_addr : out std_ulogic_vector(31 downto 0);
  43         log_rd_data : in std_ulogic_vector(63 downto 0);
  44         log_wr_addr : in std_ulogic_vector(31 downto 0)
  45         );
  46 end entity execute1;
  47
  48 architecture behaviour of execute1 is
  49     type reg_type is record
  50         e : Execute1ToWritebackType;
  51         f : Execute1ToFetch1Type;
  52         busy: std_ulogic;
  53         terminate: std_ulogic;
  54         lr_update : std_ulogic;
  55         next_lr : std_ulogic_vector(63 downto 0);
  56         mul_in_progress : std_ulogic;
  57         div_in_progress : std_ulogic;
  58         cntz_in_progress : std_ulogic;
  59         slow_op_insn : insn_type_t;
  60         slow_op_dest : gpr_index_t;
  61         slow_op_rc : std_ulogic;
  62         slow_op_oe : std_ulogic;
  63         slow_op_xerc : xer_common_t;
  64         last_nia : std_ulogic_vector(63 downto 0);
  65         log_addr_spr : std_ulogic_vector(31 downto 0);
  66     end record;
  67     constant reg_type_init : reg_type :=
  68         (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
  69          busy => '0', lr_update => '0', terminate => '0',
  70          mul_in_progress => '0', div_in_progress => '0', cntz_in_progress => '0',
  71          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  72          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
  73
  74     signal r, rin : reg_type;
  75
  76     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  77
  78     signal valid_in : std_ulogic;
  79     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  80     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  81     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  82     signal rot_sign_ext: std_ulogic;
  83     signal rotator_result: std_ulogic_vector(63 downto 0);
  84     signal rotator_carry: std_ulogic;
  85     signal logical_result: std_ulogic_vector(63 downto 0);
  86     signal countzero_result: std_ulogic_vector(63 downto 0);
  87
  88     -- multiply signals
  89     signal x_to_multiply: Execute1ToMultiplyType;
  90     signal multiply_to_x: MultiplyToExecute1Type;
  91
  92     -- divider signals
  93     signal x_to_divider: Execute1ToDividerType;
  94     signal divider_to_x: DividerToExecute1Type;
  95
  96     -- signals for logging
  97     signal exception_log : std_ulogic;
  98     signal irq_valid_log : std_ulogic;
  99     signal log_data : std_ulogic_vector(14 downto 0);
 100
 101     type privilege_level is (USER, SUPER);
 102     type op_privilege_array is array(insn_type_t) of privilege_level;
 103     constant op_privilege: op_privilege_array := (
 104         OP_ATTN => SUPER,
 105         OP_MFMSR => SUPER,
 106         OP_MTMSRD => SUPER,
 107         OP_RFID => SUPER,
 108         OP_TLBIE => SUPER,
 109         others => USER
 110         );
 111
 112     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 113         return boolean is
 114     begin
 115         if op_privilege(op) = SUPER then
 116             return true;
 117         elsif op = OP_MFSPR or op = OP_MTSPR then
 118             return insn(20) = '1';
 119         else
 120             return false;
 121         end if;
 122     end;
 123
 124     procedure set_carry(e: inout Execute1ToWritebackType;
 125                         carry32 : in std_ulogic;
 126                         carry : in std_ulogic) is
 127     begin
 128         e.xerc.ca32 := carry32;
 129         e.xerc.ca := carry;
 130         e.write_xerc_enable := '1';
 131     end;
 132
 133     procedure set_ov(e: inout Execute1ToWritebackType;
 134                      ov   : in std_ulogic;
 135                      ov32 : in std_ulogic) is
 136     begin
 137         e.xerc.ov32 := ov32;
 138         e.xerc.ov := ov;
 139         if ov = '1' then
 140             e.xerc.so := '1';
 141         end if;
 142         e.write_xerc_enable := '1';
 143     end;
 144
 145     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 146                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 147     begin
 148         return (ca xor msb_r) and not (msb_a xor msb_b);
 149     end;
 150
 151     function decode_input_carry(ic : carry_in_t;
 152                                 xerc : xer_common_t) return std_ulogic is
 153     begin
 154         case ic is
 155         when ZERO =>
 156             return '0';
 157         when CA =>
 158             return xerc.ca;
 159         when ONE =>
 160             return '1';
 161         end case;
 162     end;
 163
 164     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 165         return std_ulogic_vector is
 166         variable msr_out: std_ulogic_vector(63 downto 0);
 167     begin
 168         -- ISA says this:
 169         --  Defined MSR bits are classified as either full func-
 170         --  tion or partial function. Full function MSR bits are
 171         --  saved in SRR1 or HSRR1 when an interrupt other
 172         --  than a System Call Vectored interrupt occurs and
 173         --  restored by rfscv, rfid, or hrfid, while partial func-
 174         --  tion MSR bits are not saved or restored.
 175         --  Full function MSR bits lie in the range 0:32, 37:41, and
 176         --  48:63, and partial function MSR bits lie in the range
 177         --  33:36 and 42:47. (Note this is IBM bit numbering).
 178         msr_out := (others => '0');
 179         msr_out(63 downto 31) := msr(63 downto 31);
 180         msr_out(26 downto 22) := msr(26 downto 22);
 181         msr_out(15 downto 0)  := msr(15 downto 0);
 182         return msr_out;
 183     end;
 184
 185 begin
 186
 187     rotator_0: entity work.rotator
 188         port map (
 189             rs => c_in,
 190             ra => a_in,
 191             shift => b_in(6 downto 0),
 192             insn => e_in.insn,
 193             is_32bit => e_in.is_32bit,
 194             right_shift => right_shift,
 195             arith => e_in.is_signed,
 196             clear_left => rot_clear_left,
 197             clear_right => rot_clear_right,
 198             sign_ext_rs => rot_sign_ext,
 199             result => rotator_result,
 200             carry_out => rotator_carry
 201             );
 202
 203     logical_0: entity work.logical
 204         port map (
 205             rs => c_in,
 206             rb => b_in,
 207             op => e_in.insn_type,
 208             invert_in => e_in.invert_a,
 209             invert_out => e_in.invert_out,
 210             result => logical_result,
 211             datalen => e_in.data_len
 212             );
 213
 214     countzero_0: entity work.zero_counter
 215         port map (
 216             clk => clk,
 217             rs => c_in,
 218             count_right => e_in.insn(10),
 219             is_32bit => e_in.is_32bit,
 220             result => countzero_result
 221             );
 222
 223     multiply_0: entity work.multiply
 224         port map (
 225             clk => clk,
 226             m_in => x_to_multiply,
 227             m_out => multiply_to_x
 228             );
 229
 230     divider_0: entity work.divider
 231         port map (
 232             clk => clk,
 233             rst => rst,
 234             d_in => x_to_divider,
 235             d_out => divider_to_x
 236             );
 237
 238     dbg_msr_out <= ctrl.msr;
 239     log_rd_addr <= r.log_addr_spr;
 240
 241     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 242     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 243     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 244
 245     busy_out <= l_in.busy or r.busy;
 246     valid_in <= e_in.valid and not busy_out;
 247
 248     terminate_out <= r.terminate;
 249
 250     execute1_0: process(clk)
 251     begin
 252         if rising_edge(clk) then
 253             if rst = '1' then
 254                 r <= reg_type_init;
 255                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 256                 ctrl.irq_state <= WRITE_SRR0;
 257             else
 258                 r <= rin;
 259                 ctrl <= ctrl_tmp;
 260                 assert not (r.lr_update = '1' and valid_in = '1')
 261                     report "LR update collision with valid in EX1"
 262                     severity failure;
 263                 if r.lr_update = '1' then
 264                     report "LR update to " & to_hstring(r.next_lr);
 265                 end if;
 266             end if;
 267         end if;
 268     end process;
 269
 270     execute1_1: process(all)
 271         variable v : reg_type;
 272         variable a_inv : std_ulogic_vector(63 downto 0);
 273         variable result : std_ulogic_vector(63 downto 0);
 274         variable newcrf : std_ulogic_vector(3 downto 0);
 275         variable result_with_carry : std_ulogic_vector(64 downto 0);
 276         variable result_en : std_ulogic;
 277         variable crnum : crnum_t;
 278         variable crbit : integer range 0 to 31;
 279         variable scrnum : crnum_t;
 280         variable lo, hi : integer;
 281         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 282         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 283         variable bo, bi : std_ulogic_vector(4 downto 0);
 284         variable bf, bfa : std_ulogic_vector(2 downto 0);
 285         variable cr_op : std_ulogic_vector(9 downto 0);
 286         variable cr_operands : std_ulogic_vector(1 downto 0);
 287         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 288         variable btnum, banum, bbnum : integer range 0 to 31;
 289         variable crresult : std_ulogic;
 290         variable l : std_ulogic;
 291         variable next_nia : std_ulogic_vector(63 downto 0);
 292         variable carry_32, carry_64 : std_ulogic;
 293         variable sign1, sign2 : std_ulogic;
 294         variable abs1, abs2 : signed(63 downto 0);
 295         variable overflow : std_ulogic;
 296         variable zerohi, zerolo : std_ulogic;
 297         variable msb_a, msb_b : std_ulogic;
 298         variable a_lt : std_ulogic;
 299         variable lv : Execute1ToLoadstore1Type;
 300         variable irq_valid : std_ulogic;
 301         variable exception : std_ulogic;
 302         variable exception_nextpc : std_ulogic;
 303         variable trapval : std_ulogic_vector(4 downto 0);
 304         variable illegal : std_ulogic;
 305         variable is_branch : std_ulogic;
 306         variable taken_branch : std_ulogic;
 307         variable abs_branch : std_ulogic;
 308         variable spr_val : std_ulogic_vector(63 downto 0);
 309     begin
 310         result := (others => '0');
 311         result_with_carry := (others => '0');
 312         result_en := '0';
 313         newcrf := (others => '0');
 314         is_branch := '0';
 315         taken_branch := '0';
 316         abs_branch := '0';
 317
 318         v := r;
 319         v.e := Execute1ToWritebackInit;
 320         lv := Execute1ToLoadstore1Init;
 321         v.f.redirect := '0';
 322
 323         -- XER forwarding. To avoid having to track XER hazards, we
 324         -- use the previously latched value.
 325         --
 326         -- If the XER was modified by a multiply or a divide, those are
 327         -- single issue, we'll get the up to date value from decode2 from
 328         -- the register file.
 329         --
 330         -- If it was modified by an instruction older than the previous
 331         -- one in EX1, it will have also hit writeback and will be up
 332         -- to date in decode2.
 333         --
 334         -- That leaves us with the case where it was updated by the previous
 335         -- instruction in EX1. In that case, we can forward it back here.
 336         --
 337         -- This will break if we allow pipelining of multiply and divide,
 338         -- but ideally, those should go via EX1 anyway and run as a state
 339         -- machine from here.
 340         --
 341         -- One additional hazard to beware of is an XER:SO modifying instruction
 342         -- in EX1 followed immediately by a store conditional. Due to our
 343         -- writeback latency, the store will go down the LSU with the previous
 344         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 345         --
 346         -- We will need to handle that if we ever make stcx. not single issue
 347         --
 348         -- We always pass a valid XER value downto writeback even when
 349         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 350         -- to work for RC instructions.
 351         --
 352         if r.e.write_xerc_enable = '1' then
 353             v.e.xerc := r.e.xerc;
 354         else
 355             v.e.xerc := e_in.xerc;
 356         end if;
 357
 358         v.lr_update := '0';
 359         v.mul_in_progress := '0';
 360         v.div_in_progress := '0';
 361         v.cntz_in_progress := '0';
 362
 363         -- signals to multiply and divide units
 364         sign1 := '0';
 365         sign2 := '0';
 366         if e_in.is_signed = '1' then
 367             if e_in.is_32bit = '1' then
 368                 sign1 := a_in(31);
 369                 sign2 := b_in(31);
 370             else
 371                 sign1 := a_in(63);
 372                 sign2 := b_in(63);
 373             end if;
 374         end if;
 375         -- take absolute values
 376         if sign1 = '0' then
 377             abs1 := signed(a_in);
 378         else
 379             abs1 := - signed(a_in);
 380         end if;
 381         if sign2 = '0' then
 382             abs2 := signed(b_in);
 383         else
 384             abs2 := - signed(b_in);
 385         end if;
 386
 387         x_to_multiply <= Execute1ToMultiplyInit;
 388         x_to_multiply.is_32bit <= e_in.is_32bit;
 389
 390         x_to_divider <= Execute1ToDividerInit;
 391         x_to_divider.is_signed <= e_in.is_signed;
 392         x_to_divider.is_32bit <= e_in.is_32bit;
 393         if e_in.insn_type = OP_MOD then
 394             x_to_divider.is_modulus <= '1';
 395         end if;
 396
 397         x_to_multiply.neg_result <= sign1 xor sign2;
 398         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 399         if e_in.is_32bit = '0' then
 400             -- 64-bit forms
 401             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 402             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 403             if e_in.insn_type = OP_DIVE then
 404                 x_to_divider.is_extended <= '1';
 405             end if;
 406             x_to_divider.dividend <= std_ulogic_vector(abs1);
 407             x_to_divider.divisor <= std_ulogic_vector(abs2);
 408         else
 409             -- 32-bit forms
 410             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 411             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 412             x_to_divider.is_extended <= '0';
 413             if e_in.insn_type = OP_DIVE then   -- extended forms
 414                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 415             else
 416                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 417             end if;
 418             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 419         end if;
 420
 421         ctrl_tmp <= ctrl;
 422         -- FIXME: run at 512MHz not core freq
 423         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 424         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 425
 426         irq_valid := '0';
 427         if ctrl.msr(MSR_EE) = '1' then
 428             if ctrl.dec(63) = '1' then
 429                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
 430                 report "IRQ valid: DEC";
 431                 irq_valid := '1';
 432             elsif ext_irq_in = '1' then
 433                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
 434                 report "IRQ valid: External";
 435                 irq_valid := '1';
 436             end if;
 437         end if;
 438
 439         v.terminate := '0';
 440         icache_inval <= '0';
 441         v.busy := '0';
 442         -- send MSR[IR] and ~MSR[PR] up to fetch1
 443         v.f.virt_mode := ctrl.msr(MSR_IR);
 444         v.f.priv_mode := not ctrl.msr(MSR_PR);
 445
 446         -- Next insn adder used in a couple of places
 447         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 448
 449         -- rotator control signals
 450         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 451         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 452         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 453         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 454
 455         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 456         ctrl_tmp.irq_state <= WRITE_SRR0;
 457         exception := '0';
 458         illegal := '0';
 459         exception_nextpc := '0';
 460         v.e.exc_write_enable := '0';
 461         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 462         v.e.exc_write_data := e_in.nia;
 463         if valid_in = '1' then
 464             v.last_nia := e_in.nia;
 465         end if;
 466
 467         if ctrl.irq_state = WRITE_SRR1 then
 468             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 469             v.e.exc_write_data := ctrl.srr1;
 470             v.e.exc_write_enable := '1';
 471             ctrl_tmp.msr(MSR_SF) <= '1';
 472             ctrl_tmp.msr(MSR_EE) <= '0';
 473             ctrl_tmp.msr(MSR_PR) <= '0';
 474             ctrl_tmp.msr(MSR_IR) <= '0';
 475             ctrl_tmp.msr(MSR_DR) <= '0';
 476             ctrl_tmp.msr(MSR_RI) <= '0';
 477             ctrl_tmp.msr(MSR_LE) <= '1';
 478             v.e.valid := '1';
 479             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 480
 481         elsif irq_valid = '1' and valid_in = '1' then
 482             -- we need two cycles to write srr0 and 1
 483             -- will need more when we have to write HEIR
 484             -- Don't deliver the interrupt until we have a valid instruction
 485             -- coming in, so we have a valid NIA to put in SRR0.
 486             exception := '1';
 487
 488         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 489             instr_is_privileged(e_in.insn_type, e_in.insn) then
 490             -- generate a program interrupt
 491             exception := '1';
 492             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 493             -- set bit 45 to indicate privileged instruction type interrupt
 494             ctrl_tmp.srr1(63 - 45) <= '1';
 495             report "privileged instruction";
 496
 497         elsif valid_in = '1' and e_in.unit = ALU then
 498
 499             report "execute nia " & to_hstring(e_in.nia);
 500
 501             v.e.valid := '1';
 502             v.e.write_reg := e_in.write_reg;
 503             v.slow_op_insn := e_in.insn_type;
 504             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 505             v.slow_op_rc := e_in.rc;
 506             v.slow_op_oe := e_in.oe;
 507             v.slow_op_xerc := v.e.xerc;
 508
 509             case_0: case e_in.insn_type is
 510
 511             when OP_ILLEGAL =>
 512                 -- we need two cycles to write srr0 and 1
 513                 -- will need more when we have to write HEIR
 514                 illegal := '1';
 515             when OP_SC =>
 516                 -- check bit 1 of the instruction is 1 so we know this is sc;
 517                 -- 0 would mean scv, so generate an illegal instruction interrupt
 518                 -- we need two cycles to write srr0 and 1
 519                 if e_in.insn(1) = '1' then
 520                     exception := '1';
 521                     exception_nextpc := '1';
 522                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
 523                     report "sc";
 524                 else
 525                     illegal := '1';
 526                 end if;
 527             when OP_ATTN =>
 528                 -- check bits 1-10 of the instruction to make sure it's attn
 529                 -- if not then it is illegal
 530                 if e_in.insn(10 downto 1) = "0100000000" then
 531                     v.terminate := '1';
 532                     report "ATTN";
 533                 else
 534                     illegal := '1';
 535                 end if;
 536             when OP_NOP =>
 537                 -- Do nothing
 538             when OP_ADD | OP_CMP | OP_TRAP =>
 539                 if e_in.invert_a = '0' then
 540                     a_inv := a_in;
 541                 else
 542                     a_inv := not a_in;
 543                 end if;
 544                 result_with_carry := ppc_adde(a_inv, b_in,
 545                                               decode_input_carry(e_in.input_carry, v.e.xerc));
 546                 result := result_with_carry(63 downto 0);
 547                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 548                 carry_64 := result_with_carry(64);
 549                 if e_in.insn_type = OP_ADD then
 550                     if e_in.output_carry = '1' then
 551                         set_carry(v.e, carry_32, carry_64);
 552                     end if;
 553                     if e_in.oe = '1' then
 554                         set_ov(v.e,
 555                                calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
 556                                calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
 557                     end if;
 558                     result_en := '1';
 559                 else
 560                     -- trap, CMP and CMPL instructions
 561                     -- Note, we have done RB - RA, not RA - RB
 562                     if e_in.insn_type = OP_CMP then
 563                         l := insn_l(e_in.insn);
 564                     else
 565                         l := not e_in.is_32bit;
 566                     end if;
 567                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 568                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 569                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 570                         -- values are equal
 571                         trapval := "00100";
 572                     else
 573                         if l = '1' then
 574                             -- 64-bit comparison
 575                             msb_a := a_in(63);
 576                             msb_b := b_in(63);
 577                         else
 578                             -- 32-bit comparison
 579                             msb_a := a_in(31);
 580                             msb_b := b_in(31);
 581                         end if;
 582                         if msb_a /= msb_b then
 583                             -- Subtraction might overflow, but
 584                             -- comparison is clear from MSB difference.
 585                             -- for signed, 0 is greater; for unsigned, 1 is greater
 586                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 587                         else
 588                             -- Subtraction cannot overflow since MSBs are equal.
 589                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 590                             a_lt := (not l and carry_32) or (l and carry_64);
 591                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 592                         end if;
 593                     end if;
 594                     if e_in.insn_type = OP_CMP then
 595                         if e_in.is_signed = '1' then
 596                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 597                         else
 598                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 599                         end if;
 600                         bf := insn_bf(e_in.insn);
 601                         crnum := to_integer(unsigned(bf));
 602                         v.e.write_cr_enable := '1';
 603                         v.e.write_cr_mask := num_to_fxm(crnum);
 604                         for i in 0 to 7 loop
 605                             lo := i*4;
 606                             hi := lo + 3;
 607                             v.e.write_cr_data(hi downto lo) := newcrf;
 608                         end loop;
 609                     else
 610                         -- trap instructions (tw, twi, td, tdi)
 611                         if or (trapval and insn_to(e_in.insn)) = '1' then
 612                             -- generate trap-type program interrupt
 613                             exception := '1';
 614                             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 615                             -- set bit 46 to say trap occurred
 616                             ctrl_tmp.srr1(63 - 46) <= '1';
 617                             report "trap";
 618                         end if;
 619                     end if;
 620                 end if;
 621             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS =>
 622                 result := logical_result;
 623                 result_en := '1';
 624             when OP_B =>
 625                 is_branch := '1';
 626                 taken_branch := '1';
 627                 abs_branch := insn_aa(e_in.insn);
 628             when OP_BC =>
 629                 -- read_data1 is CTR
 630                 bo := insn_bo(e_in.insn);
 631                 bi := insn_bi(e_in.insn);
 632                 if bo(4-2) = '0' then
 633                     result := std_ulogic_vector(unsigned(a_in) - 1);
 634                     result_en := '1';
 635                     v.e.write_reg := fast_spr_num(SPR_CTR);
 636                 end if;
 637                 is_branch := '1';
 638                 taken_branch := ppc_bc_taken(bo, bi, e_in.cr, a_in);
 639                 abs_branch := insn_aa(e_in.insn);
 640             when OP_BCREG =>
 641                 -- read_data1 is CTR
 642                 -- read_data2 is target register (CTR, LR or TAR)
 643                 bo := insn_bo(e_in.insn);
 644                 bi := insn_bi(e_in.insn);
 645                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 646                     result := std_ulogic_vector(unsigned(a_in) - 1);
 647                     result_en := '1';
 648                     v.e.write_reg := fast_spr_num(SPR_CTR);
 649                 end if;
 650                 is_branch := '1';
 651                 taken_branch := ppc_bc_taken(bo, bi, e_in.cr, a_in);
 652                 abs_branch := '1';
 653
 654             when OP_RFID =>
 655                 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
 656                 v.f.priv_mode := not a_in(MSR_PR);
 657                 -- Can't use msr_copy here because the partial function MSR
 658                 -- bits should be left unchanged, not zeroed.
 659                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 660                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 661                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 662                 if a_in(MSR_PR) = '1' then
 663                     ctrl_tmp.msr(MSR_EE) <= '1';
 664                     ctrl_tmp.msr(MSR_IR) <= '1';
 665                     ctrl_tmp.msr(MSR_DR) <= '1';
 666                 end if;
 667                 -- mark this as a branch so CFAR gets updated
 668                 is_branch := '1';
 669                 taken_branch := '1';
 670                 abs_branch := '1';
 671
 672             when OP_CNTZ =>
 673                 v.e.valid := '0';
 674                 v.cntz_in_progress := '1';
 675                 v.busy := '1';
 676             when OP_ISEL =>
 677                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 678                 if e_in.cr(31-crbit) = '1' then
 679                     result := a_in;
 680                 else
 681                     result := b_in;
 682                 end if;
 683                 result_en := '1';
 684             when OP_CROP =>
 685                 cr_op := insn_cr(e_in.insn);
 686                 report "CR OP " & to_hstring(cr_op);
 687                 if cr_op(0) = '0' then -- MCRF
 688                     bf := insn_bf(e_in.insn);
 689                     bfa := insn_bfa(e_in.insn);
 690                     v.e.write_cr_enable := '1';
 691                     crnum := to_integer(unsigned(bf));
 692                     scrnum := to_integer(unsigned(bfa));
 693                     v.e.write_cr_mask := num_to_fxm(crnum);
 694                     for i in 0 to 7 loop
 695                         lo := (7-i)*4;
 696                         hi := lo + 3;
 697                         if i = scrnum then
 698                             newcrf := e_in.cr(hi downto lo);
 699                         end if;
 700                     end loop;
 701                     for i in 0 to 7 loop
 702                         lo := i*4;
 703                         hi := lo + 3;
 704                         v.e.write_cr_data(hi downto lo) := newcrf;
 705                     end loop;
 706                 else
 707                     v.e.write_cr_enable := '1';
 708                     bt := insn_bt(e_in.insn);
 709                     ba := insn_ba(e_in.insn);
 710                     bb := insn_bb(e_in.insn);
 711                     btnum := 31 - to_integer(unsigned(bt));
 712                     banum := 31 - to_integer(unsigned(ba));
 713                     bbnum := 31 - to_integer(unsigned(bb));
 714                     -- Bits 5-8 of cr_op give the truth table of the requested
 715                     -- logical operation
 716                     cr_operands := e_in.cr(banum) & e_in.cr(bbnum);
 717                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 718                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 719                     for i in 0 to 31 loop
 720                         if i = btnum then
 721                             v.e.write_cr_data(i) := crresult;
 722                         else
 723                             v.e.write_cr_data(i) := e_in.cr(i);
 724                         end if;
 725                     end loop;
 726                 end if;
 727             when OP_MFMSR =>
 728                 result := ctrl.msr;
 729                 result_en := '1';
 730             when OP_MFSPR =>
 731                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 732                     "=" & to_hstring(a_in);
 733                 result_en := '1';
 734                 if is_fast_spr(e_in.read_reg1) then
 735                     result := a_in;
 736                     if decode_spr_num(e_in.insn) = SPR_XER then
 737                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 738                         result(63 downto 32) := (others => '0');
 739                         result(63-32) := v.e.xerc.so;
 740                         result(63-33) := v.e.xerc.ov;
 741                         result(63-34) := v.e.xerc.ca;
 742                         result(63-35 downto 63-43) := "000000000";
 743                         result(63-44) := v.e.xerc.ov32;
 744                         result(63-45) := v.e.xerc.ca32;
 745                     end if;
 746                 else
 747                     spr_val := c_in;
 748                     case decode_spr_num(e_in.insn) is
 749                     when SPR_TB =>
 750                         spr_val := ctrl.tb;
 751                     when SPR_TBU =>
 752                         spr_val(63 downto 32) := (others => '0');
 753                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 754                     when SPR_DEC =>
 755                         spr_val := ctrl.dec;
 756                     when SPR_CFAR =>
 757                         spr_val := ctrl.cfar;
 758                     when 724 =>     -- LOG_ADDR SPR
 759                         spr_val := log_wr_addr & r.log_addr_spr;
 760                     when 725 =>     -- LOG_DATA SPR
 761                         spr_val := log_rd_data;
 762                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 763                     when others =>
 764                         -- mfspr from unimplemented SPRs should be a nop in
 765                         -- supervisor mode and a program interrupt for user mode
 766                         if ctrl.msr(MSR_PR) = '1' then
 767                             illegal := '1';
 768                         end if;
 769                     end case;
 770                     result := spr_val;
 771                 end if;
 772             when OP_MFCR =>
 773                 if e_in.insn(20) = '0' then
 774                     -- mfcr
 775                     result := x"00000000" & e_in.cr;
 776                 else
 777                     -- mfocrf
 778                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 779                     result := (others => '0');
 780                     for i in 0 to 7 loop
 781                         lo := (7-i)*4;
 782                         hi := lo + 3;
 783                         if crnum = i then
 784                             result(hi downto lo) := e_in.cr(hi downto lo);
 785                         end if;
 786                     end loop;
 787                 end if;
 788                 result_en := '1';
 789             when OP_MTCRF =>
 790                 v.e.write_cr_enable := '1';
 791                 if e_in.insn(20) = '0' then
 792                     -- mtcrf
 793                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 794                 else
 795                     -- mtocrf: We require one hot priority encoding here
 796                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 797                     v.e.write_cr_mask := num_to_fxm(crnum);
 798                 end if;
 799                 v.e.write_cr_data := c_in(31 downto 0);
 800             when OP_MTMSRD =>
 801                 if e_in.insn(16) = '1' then
 802                     -- just update EE and RI
 803                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 804                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 805                 else
 806                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 807                     -- and 63 (LE) (IBM bit numbering)
 808                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 809                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 810                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 811                     if c_in(MSR_PR) = '1' then
 812                         ctrl_tmp.msr(MSR_EE) <= '1';
 813                         ctrl_tmp.msr(MSR_IR) <= '1';
 814                         ctrl_tmp.msr(MSR_DR) <= '1';
 815                     end if;
 816                 end if;
 817             when OP_MTSPR =>
 818                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 819                     "=" & to_hstring(c_in);
 820                 if is_fast_spr(e_in.write_reg) then
 821                     result := c_in;
 822                     result_en := '1';
 823                     if decode_spr_num(e_in.insn) = SPR_XER then
 824                         v.e.xerc.so := c_in(63-32);
 825                         v.e.xerc.ov := c_in(63-33);
 826                         v.e.xerc.ca := c_in(63-34);
 827                         v.e.xerc.ov32 := c_in(63-44);
 828                         v.e.xerc.ca32 := c_in(63-45);
 829                         v.e.write_xerc_enable := '1';
 830                     end if;
 831                 else
 832                     -- slow spr
 833                     case decode_spr_num(e_in.insn) is
 834                     when SPR_DEC =>
 835                         ctrl_tmp.dec <= c_in;
 836                     when 724 =>     -- LOG_ADDR SPR
 837                         v.log_addr_spr := c_in(31 downto 0);
 838                     when others =>
 839                         -- mtspr to unimplemented SPRs should be a nop in
 840                         -- supervisor mode and a program interrupt for user mode
 841                         if ctrl.msr(MSR_PR) = '1' then
 842                             illegal := '1';
 843                         end if;
 844                     end case;
 845                 end if;
 846             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
 847                 result := rotator_result;
 848                 if e_in.output_carry = '1' then
 849                     set_carry(v.e, rotator_carry, rotator_carry);
 850                 end if;
 851                 result_en := '1';
 852
 853             when OP_ISYNC =>
 854                 v.f.redirect := '1';
 855                 v.f.redirect_nia := next_nia;
 856
 857             when OP_ICBI =>
 858                 icache_inval <= '1';
 859
 860             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
 861                 v.e.valid := '0';
 862                 v.mul_in_progress := '1';
 863                 v.busy := '1';
 864                 x_to_multiply.valid <= '1';
 865
 866             when OP_DIV | OP_DIVE | OP_MOD =>
 867                 v.e.valid := '0';
 868                 v.div_in_progress := '1';
 869                 v.busy := '1';
 870                 x_to_divider.valid <= '1';
 871
 872             when others =>
 873                 v.terminate := '1';
 874                 report "illegal";
 875             end case;
 876
 877             v.e.rc := e_in.rc and valid_in;
 878
 879             -- Mispredicted branches cause a redirect
 880             if is_branch = '1' then
 881                 if taken_branch = '1' then
 882                     ctrl_tmp.cfar <= e_in.nia;
 883                 end if;
 884                 if e_in.br_pred = '0' then
 885                     if abs_branch = '1' then
 886                         v.f.redirect_nia := b_in;
 887                     else
 888                         v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 889                     end if;
 890                 else
 891                     v.f.redirect_nia := next_nia;
 892                 end if;
 893                 if taken_branch /= e_in.br_pred then
 894                     v.f.redirect := '1';
 895                 end if;
 896             end if;
 897
 898             -- Update LR on the next cycle after a branch link
 899             -- If we're not writing back anything else, we can write back LR
 900             -- this cycle, otherwise we take an extra cycle.  We use the
 901             -- exc_write path since next_nia is written through that path
 902             -- in other places.
 903             if e_in.lr = '1' then
 904                 if result_en = '0' then
 905                     v.e.exc_write_enable := '1';
 906                     v.e.exc_write_data := next_nia;
 907                     v.e.exc_write_reg := fast_spr_num(SPR_LR);
 908                 else
 909                     v.lr_update := '1';
 910                     v.next_lr := next_nia;
 911                     v.e.valid := '0';
 912                     report "Delayed LR update to " & to_hstring(next_nia);
 913                     v.busy := '1';
 914                 end if;
 915             end if;
 916
 917         elsif valid_in = '1' then
 918             -- instruction for other units, i.e. LDST
 919             if e_in.unit = LDST then
 920                 lv.valid := '1';
 921             end if;
 922
 923         elsif r.f.redirect = '1' then
 924             v.e.valid := '1';
 925         elsif r.lr_update = '1' then
 926             v.e.exc_write_enable := '1';
 927             v.e.exc_write_data := r.next_lr;
 928             v.e.exc_write_reg := fast_spr_num(SPR_LR);
 929             v.e.valid := '1';
 930         elsif r.cntz_in_progress = '1' then
 931             -- cnt[lt]z always takes two cycles
 932             result := countzero_result;
 933             result_en := '1';
 934             v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 935             v.e.rc := v.slow_op_rc;
 936             v.e.xerc := v.slow_op_xerc;
 937             v.e.valid := '1';
 938         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
 939             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
 940                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
 941                 if r.mul_in_progress = '1' then
 942                     overflow := '0';
 943                     case r.slow_op_insn is
 944                         when OP_MUL_H32 =>
 945                             result := multiply_to_x.result(63 downto 32) &
 946                                       multiply_to_x.result(63 downto 32);
 947                         when OP_MUL_H64 =>
 948                             result := multiply_to_x.result(127 downto 64);
 949                         when others =>
 950                             -- i.e. OP_MUL_L64
 951                             result := multiply_to_x.result(63 downto 0);
 952                             overflow := multiply_to_x.overflow;
 953                     end case;
 954                 else
 955                     result := divider_to_x.write_reg_data;
 956                     overflow := divider_to_x.overflow;
 957                 end if;
 958                 result_en := '1';
 959                 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 960                 v.e.rc := v.slow_op_rc;
 961                 v.e.xerc := v.slow_op_xerc;
 962                 v.e.write_xerc_enable := v.slow_op_oe;
 963                 -- We must test oe because the RC update code in writeback
 964                 -- will use the xerc value to set CR0:SO so we must not clobber
 965                 -- xerc if OE wasn't set.
 966                 if v.slow_op_oe = '1' then
 967                     v.e.xerc.ov := overflow;
 968                     v.e.xerc.ov32 := overflow;
 969                     v.e.xerc.so := v.slow_op_xerc.so or overflow;
 970                 end if;
 971                 v.e.valid := '1';
 972             else
 973                 v.busy := '1';
 974                 v.mul_in_progress := r.mul_in_progress;
 975                 v.div_in_progress := r.div_in_progress;
 976             end if;
 977         end if;
 978
 979         if illegal = '1' then
 980             exception := '1';
 981             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 982             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
 983             -- set bit 44 to indicate we have an illegal
 984             ctrl_tmp.srr1(63 - 44) <= '1';
 985             report "illegal";
 986         end if;
 987         if exception = '1' then
 988             v.e.exc_write_enable := '1';
 989             if exception_nextpc = '1' then
 990                 v.e.exc_write_data := next_nia;
 991             end if;
 992         end if;
 993
 994         v.e.write_data := result;
 995         v.e.write_enable := result_en and not exception;
 996
 997         -- generate DSI or DSegI for load/store exceptions
 998         -- or ISI or ISegI for instruction fetch exceptions
 999         if l_in.exception = '1' then
1000             if l_in.instr_fault = '0' then
1001                 if l_in.segment_fault = '0' then
1002                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1003                 else
1004                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1005                 end if;
1006             else
1007                 if l_in.segment_fault = '0' then
1008                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1009                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1010                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1011                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1012                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1013                 else
1014                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1015                 end if;
1016             end if;
1017             v.e.exc_write_enable := '1';
1018             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1019             v.e.exc_write_data := r.last_nia;
1020             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1021         end if;
1022
1023         if exception = '1' or l_in.exception = '1' then
1024             ctrl_tmp.irq_state <= WRITE_SRR1;
1025             v.f.redirect := '1';
1026             v.f.virt_mode := '0';
1027             v.f.priv_mode := '1';
1028         end if;
1029
1030         if v.f.redirect = '1' then
1031             v.busy := '1';
1032             v.e.valid := '0';
1033         end if;
1034
1035         -- Outputs to loadstore1 (async)
1036         lv.op := e_in.insn_type;
1037         lv.nia := e_in.nia;
1038         lv.addr1 := a_in;
1039         lv.addr2 := b_in;
1040         lv.data := c_in;
1041         lv.write_reg := gspr_to_gpr(e_in.write_reg);
1042         lv.length := e_in.data_len;
1043         lv.byte_reverse := e_in.byte_reverse;
1044         lv.sign_extend := e_in.sign_extend;
1045         lv.update := e_in.update;
1046         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1047         lv.xerc := v.e.xerc;
1048         lv.reserve := e_in.reserve;
1049         lv.rc := e_in.rc;
1050         lv.insn := e_in.insn;
1051         -- decode l*cix and st*cix instructions here
1052         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1053             e_in.insn(5 downto 1) = "10101" then
1054             lv.ci := '1';
1055         end if;
1056         lv.virt_mode := ctrl.msr(MSR_DR);
1057         lv.priv_mode := not ctrl.msr(MSR_PR);
1058
1059         -- Update registers
1060         rin <= v;
1061
1062         -- update outputs
1063         f_out <= r.f;
1064         l_out <= lv;
1065         e_out <= r.e;
1066         flush_out <= f_out.redirect;
1067
1068         exception_log <= exception;
1069         irq_valid_log <= irq_valid;
1070     end process;
1071
1072     ex1_log : process(clk)
1073     begin
1074         if rising_edge(clk) then
1075             log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1076                         ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1077                         exception_log &
1078                         irq_valid_log &
1079                         std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1080                         "000" &
1081                         r.e.write_enable &
1082                         r.e.valid &
1083                         f_out.redirect &
1084                         r.busy &
1085                         flush_out;
1086         end if;
1087     end process;
1088     log_out <= log_data;
1089 end architecture behaviour;