execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33
  34         -- asynchronous
  35         l_out : out Execute1ToLoadstore1Type;
  36         f_out : out Execute1ToFetch1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40
  41         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  42
  43         icache_inval : out std_ulogic;
  44         terminate_out : out std_ulogic;
  45
  46         log_out : out std_ulogic_vector(14 downto 0);
  47         log_rd_addr : out std_ulogic_vector(31 downto 0);
  48         log_rd_data : in std_ulogic_vector(63 downto 0);
  49         log_wr_addr : in std_ulogic_vector(31 downto 0)
  50         );
  51 end entity execute1;
  52
  53 architecture behaviour of execute1 is
  54     type reg_type is record
  55         e : Execute1ToWritebackType;
  56         cur_instr : Decode2ToExecute1Type;
  57         busy: std_ulogic;
  58         terminate: std_ulogic;
  59         fp_exception_next : std_ulogic;
  60         trace_next : std_ulogic;
  61         prev_op : insn_type_t;
  62         lr_update : std_ulogic;
  63         next_lr : std_ulogic_vector(63 downto 0);
  64         mul_in_progress : std_ulogic;
  65         mul_finish : std_ulogic;
  66         div_in_progress : std_ulogic;
  67         cntz_in_progress : std_ulogic;
  68         last_nia : std_ulogic_vector(63 downto 0);
  69         redirect : std_ulogic;
  70         abs_br : std_ulogic;
  71         taken_br : std_ulogic;
  72         br_last : std_ulogic;
  73         do_intr : std_ulogic;
  74         vector : integer range 0 to 16#fff#;
  75         br_offset : std_ulogic_vector(63 downto 0);
  76         redir_mode : std_ulogic_vector(3 downto 0);
  77         log_addr_spr : std_ulogic_vector(31 downto 0);
  78     end record;
  79     constant reg_type_init : reg_type :=
  80         (e => Execute1ToWritebackInit,
  81          cur_instr => Decode2ToExecute1Init,
  82          busy => '0', lr_update => '0', terminate => '0',
  83          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL,
  84          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  85          next_lr => (others => '0'), last_nia => (others => '0'),
  86          redirect => '0', abs_br => '0', taken_br => '0', br_last => '0', do_intr => '0', vector => 0,
  87          br_offset => (others => '0'), redir_mode => "0000",
  88          others => (others => '0'));
  89
  90     signal r, rin : reg_type;
  91
  92     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  93     signal cr_in : std_ulogic_vector(31 downto 0);
  94
  95     signal valid_in : std_ulogic;
  96     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  97     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  98     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  99     signal rot_sign_ext: std_ulogic;
 100     signal rotator_result: std_ulogic_vector(63 downto 0);
 101     signal rotator_carry: std_ulogic;
 102     signal logical_result: std_ulogic_vector(63 downto 0);
 103     signal countzero_result: std_ulogic_vector(63 downto 0);
 104     signal alu_result: std_ulogic_vector(63 downto 0);
 105     signal adder_result: std_ulogic_vector(63 downto 0);
 106     signal misc_result: std_ulogic_vector(63 downto 0);
 107     signal muldiv_result: std_ulogic_vector(63 downto 0);
 108     signal spr_result: std_ulogic_vector(63 downto 0);
 109     signal result_mux_sel: std_ulogic_vector(2 downto 0);
 110     signal sub_mux_sel: std_ulogic_vector(2 downto 0);
 111     signal current: Decode2ToExecute1Type;
 112
 113     -- multiply signals
 114     signal x_to_multiply: MultiplyInputType;
 115     signal multiply_to_x: MultiplyOutputType;
 116
 117     -- divider signals
 118     signal x_to_divider: Execute1ToDividerType;
 119     signal divider_to_x: DividerToExecute1Type;
 120
 121     -- random number generator signals
 122     signal random_raw  : std_ulogic_vector(63 downto 0);
 123     signal random_cond : std_ulogic_vector(63 downto 0);
 124     signal random_err  : std_ulogic;
 125
 126     -- signals for logging
 127     signal exception_log : std_ulogic;
 128     signal irq_valid_log : std_ulogic;
 129
 130     type privilege_level is (USER, SUPER);
 131     type op_privilege_array is array(insn_type_t) of privilege_level;
 132     constant op_privilege: op_privilege_array := (
 133         OP_ATTN => SUPER,
 134         OP_MFMSR => SUPER,
 135         OP_MTMSRD => SUPER,
 136         OP_RFID => SUPER,
 137         OP_TLBIE => SUPER,
 138         others => USER
 139         );
 140
 141     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 142         return boolean is
 143     begin
 144         if op_privilege(op) = SUPER then
 145             return true;
 146         elsif op = OP_MFSPR or op = OP_MTSPR then
 147             return insn(20) = '1';
 148         else
 149             return false;
 150         end if;
 151     end;
 152
 153     procedure set_carry(e: inout Execute1ToWritebackType;
 154                         carry32 : in std_ulogic;
 155                         carry : in std_ulogic) is
 156     begin
 157         e.xerc.ca32 := carry32;
 158         e.xerc.ca := carry;
 159         e.write_xerc_enable := '1';
 160     end;
 161
 162     procedure set_ov(e: inout Execute1ToWritebackType;
 163                      ov   : in std_ulogic;
 164                      ov32 : in std_ulogic) is
 165     begin
 166         e.xerc.ov32 := ov32;
 167         e.xerc.ov := ov;
 168         if ov = '1' then
 169             e.xerc.so := '1';
 170         end if;
 171         e.write_xerc_enable := '1';
 172     end;
 173
 174     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 175                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 176     begin
 177         return (ca xor msb_r) and not (msb_a xor msb_b);
 178     end;
 179
 180     function decode_input_carry(ic : carry_in_t;
 181                                 xerc : xer_common_t) return std_ulogic is
 182     begin
 183         case ic is
 184         when ZERO =>
 185             return '0';
 186         when CA =>
 187             return xerc.ca;
 188         when OV =>
 189             return xerc.ov;
 190         when ONE =>
 191             return '1';
 192         end case;
 193     end;
 194
 195     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 196         return std_ulogic_vector is
 197         variable msr_out: std_ulogic_vector(63 downto 0);
 198     begin
 199         -- ISA says this:
 200         --  Defined MSR bits are classified as either full func-
 201         --  tion or partial function. Full function MSR bits are
 202         --  saved in SRR1 or HSRR1 when an interrupt other
 203         --  than a System Call Vectored interrupt occurs and
 204         --  restored by rfscv, rfid, or hrfid, while partial func-
 205         --  tion MSR bits are not saved or restored.
 206         --  Full function MSR bits lie in the range 0:32, 37:41, and
 207         --  48:63, and partial function MSR bits lie in the range
 208         --  33:36 and 42:47. (Note this is IBM bit numbering).
 209         msr_out := (others => '0');
 210         msr_out(63 downto 31) := msr(63 downto 31);
 211         msr_out(26 downto 22) := msr(26 downto 22);
 212         msr_out(15 downto 0)  := msr(15 downto 0);
 213         return msr_out;
 214     end;
 215
 216     -- Tell vivado to keep the hierarchy for the random module so that the
 217     -- net names in the xdc file match.
 218     attribute keep_hierarchy : string;
 219     attribute keep_hierarchy of random_0 : label is "yes";
 220
 221 begin
 222
 223     rotator_0: entity work.rotator
 224         port map (
 225             rs => c_in,
 226             ra => a_in,
 227             shift => b_in(6 downto 0),
 228             insn => e_in.insn,
 229             is_32bit => e_in.is_32bit,
 230             right_shift => right_shift,
 231             arith => e_in.is_signed,
 232             clear_left => rot_clear_left,
 233             clear_right => rot_clear_right,
 234             sign_ext_rs => rot_sign_ext,
 235             result => rotator_result,
 236             carry_out => rotator_carry
 237             );
 238
 239     logical_0: entity work.logical
 240         port map (
 241             rs => c_in,
 242             rb => b_in,
 243             op => e_in.insn_type,
 244             invert_in => e_in.invert_a,
 245             invert_out => e_in.invert_out,
 246             result => logical_result,
 247             datalen => e_in.data_len
 248             );
 249
 250     countzero_0: entity work.zero_counter
 251         port map (
 252             clk => clk,
 253             rs => c_in,
 254             count_right => e_in.insn(10),
 255             is_32bit => e_in.is_32bit,
 256             result => countzero_result
 257             );
 258
 259     multiply_0: entity work.multiply
 260         port map (
 261             clk => clk,
 262             m_in => x_to_multiply,
 263             m_out => multiply_to_x
 264             );
 265
 266     divider_0: entity work.divider
 267         port map (
 268             clk => clk,
 269             rst => rst,
 270             d_in => x_to_divider,
 271             d_out => divider_to_x
 272             );
 273
 274     random_0: entity work.random
 275         port map (
 276             clk => clk,
 277             data => random_cond,
 278             raw => random_raw,
 279             err => random_err
 280             );
 281
 282     dbg_msr_out <= ctrl.msr;
 283     log_rd_addr <= r.log_addr_spr;
 284
 285     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 286     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 287     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 288
 289     busy_out <= l_in.busy or r.busy or fp_in.busy;
 290     valid_in <= e_in.valid and not busy_out;
 291
 292     terminate_out <= r.terminate;
 293
 294     current <= e_in when r.busy = '0' else r.cur_instr;
 295
 296     -- Result mux
 297     with current.result_sel select alu_result <=
 298         adder_result       when "000",
 299         logical_result     when "001",
 300         rotator_result     when "010",
 301         muldiv_result      when "011",
 302         countzero_result   when "100",
 303         spr_result         when "101",
 304         misc_result        when others;
 305
 306     execute1_0: process(clk)
 307     begin
 308         if rising_edge(clk) then
 309             if rst = '1' then
 310                 r <= reg_type_init;
 311                 ctrl.tb <= (others => '0');
 312                 ctrl.dec <= (others => '0');
 313                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 314                 ctrl.irq_state <= WRITE_SRR0;
 315             else
 316                 r <= rin;
 317                 ctrl <= ctrl_tmp;
 318                 assert not (r.lr_update = '1' and valid_in = '1')
 319                     report "LR update collision with valid in EX1"
 320                     severity failure;
 321                 if r.lr_update = '1' then
 322                     report "LR update to " & to_hstring(r.next_lr);
 323                 end if;
 324             end if;
 325         end if;
 326     end process;
 327
 328     execute1_1: process(all)
 329         variable v : reg_type;
 330         variable a_inv : std_ulogic_vector(63 downto 0);
 331         variable b_or_m1 : std_ulogic_vector(63 downto 0);
 332         variable addg6s : std_ulogic_vector(63 downto 0);
 333         variable isel_result : std_ulogic_vector(63 downto 0);
 334         variable darn : std_ulogic_vector(63 downto 0);
 335         variable mfcr_result : std_ulogic_vector(63 downto 0);
 336         variable setb_result : std_ulogic_vector(63 downto 0);
 337         variable newcrf : std_ulogic_vector(3 downto 0);
 338         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 339         variable crnum : crnum_t;
 340         variable crbit : integer range 0 to 31;
 341         variable scrnum : crnum_t;
 342         variable lo, hi : integer;
 343         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 344         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 345         variable bo, bi : std_ulogic_vector(4 downto 0);
 346         variable bf, bfa : std_ulogic_vector(2 downto 0);
 347         variable cr_op : std_ulogic_vector(9 downto 0);
 348         variable cr_operands : std_ulogic_vector(1 downto 0);
 349         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 350         variable btnum, banum, bbnum : integer range 0 to 31;
 351         variable crresult : std_ulogic;
 352         variable l : std_ulogic;
 353         variable next_nia : std_ulogic_vector(63 downto 0);
 354         variable carry_32, carry_64 : std_ulogic;
 355         variable sign1, sign2 : std_ulogic;
 356         variable abs1, abs2 : signed(63 downto 0);
 357         variable overflow : std_ulogic;
 358         variable zerohi, zerolo : std_ulogic;
 359         variable msb_a, msb_b : std_ulogic;
 360         variable a_lt : std_ulogic;
 361         variable a_lt_lo : std_ulogic;
 362         variable a_lt_hi : std_ulogic;
 363         variable lv : Execute1ToLoadstore1Type;
 364         variable irq_valid : std_ulogic;
 365         variable exception : std_ulogic;
 366         variable exception_nextpc : std_ulogic;
 367         variable trapval : std_ulogic_vector(4 downto 0);
 368         variable illegal : std_ulogic;
 369         variable is_branch : std_ulogic;
 370         variable is_direct_branch : std_ulogic;
 371         variable taken_branch : std_ulogic;
 372         variable abs_branch : std_ulogic;
 373         variable spr_val : std_ulogic_vector(63 downto 0);
 374         variable addend : std_ulogic_vector(127 downto 0);
 375         variable do_trace : std_ulogic;
 376         variable hold_wr_data : std_ulogic;
 377         variable f : Execute1ToFetch1Type;
 378         variable fv : Execute1ToFPUType;
 379     begin
 380         sum_with_carry := (others => '0');
 381         newcrf := (others => '0');
 382         is_branch := '0';
 383         is_direct_branch := '0';
 384         taken_branch := '0';
 385         abs_branch := '0';
 386         hold_wr_data := '0';
 387
 388         v := r;
 389         v.e := Execute1ToWritebackInit;
 390         v.redirect := '0';
 391         v.abs_br := '0';
 392         v.do_intr := '0';
 393         v.vector := 0;
 394         v.br_offset := (others => '0');
 395         v.redir_mode := ctrl.msr(MSR_IR) & not ctrl.msr(MSR_PR) &
 396                         not ctrl.msr(MSR_LE) & not ctrl.msr(MSR_SF);
 397         v.taken_br := '0';
 398         v.br_last := '0';
 399
 400         lv := Execute1ToLoadstore1Init;
 401         fv := Execute1ToFPUInit;
 402
 403         -- XER forwarding. To avoid having to track XER hazards, we use
 404         -- the previously latched value.  Since the XER common bits
 405         -- (SO, OV[32] and CA[32]) are only modified by instructions that are
 406         -- handled here, we can just forward the result being sent to
 407         -- writeback.
 408         if r.e.write_xerc_enable = '1' or r.busy = '1' then
 409             v.e.xerc := r.e.xerc;
 410         else
 411             v.e.xerc := e_in.xerc;
 412         end if;
 413
 414         -- CR forwarding
 415         cr_in <= e_in.cr;
 416         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 417             for i in 0 to 7 loop
 418                 if r.e.write_cr_mask(i) = '1' then
 419                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 420                 end if;
 421             end loop;
 422         end if;
 423
 424         v.lr_update := '0';
 425         v.mul_in_progress := '0';
 426         v.div_in_progress := '0';
 427         v.cntz_in_progress := '0';
 428         v.mul_finish := '0';
 429
 430         spr_result <= (others => '0');
 431         spr_val := (others => '0');
 432
 433         -- Main adder
 434         if e_in.invert_a = '0' then
 435             a_inv := a_in;
 436         else
 437             a_inv := not a_in;
 438         end if;
 439         if e_in.addm1 = '0' then
 440             b_or_m1 := b_in;
 441         else
 442             b_or_m1 := (others => '1');
 443         end if;
 444         sum_with_carry := ppc_adde(a_inv, b_or_m1,
 445                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 446         adder_result <= sum_with_carry(63 downto 0);
 447         carry_32 := sum_with_carry(32) xor a_inv(32) xor b_in(32);
 448         carry_64 := sum_with_carry(64);
 449
 450         -- signals to multiply and divide units
 451         sign1 := '0';
 452         sign2 := '0';
 453         if e_in.is_signed = '1' then
 454             if e_in.is_32bit = '1' then
 455                 sign1 := a_in(31);
 456                 sign2 := b_in(31);
 457             else
 458                 sign1 := a_in(63);
 459                 sign2 := b_in(63);
 460             end if;
 461         end if;
 462         -- take absolute values
 463         if sign1 = '0' then
 464             abs1 := signed(a_in);
 465         else
 466             abs1 := - signed(a_in);
 467         end if;
 468         if sign2 = '0' then
 469             abs2 := signed(b_in);
 470         else
 471             abs2 := - signed(b_in);
 472         end if;
 473
 474         -- Interface to multiply and divide units
 475         x_to_multiply <= MultiplyInputInit;
 476         x_to_multiply.is_32bit <= e_in.is_32bit;
 477
 478         x_to_divider <= Execute1ToDividerInit;
 479         x_to_divider.is_signed <= e_in.is_signed;
 480         x_to_divider.is_32bit <= e_in.is_32bit;
 481         if e_in.insn_type = OP_MOD then
 482             x_to_divider.is_modulus <= '1';
 483         end if;
 484
 485         addend := (others => '0');
 486         if e_in.insn(26) = '0' then
 487             -- integer multiply-add, major op 4 (if it is a multiply)
 488             addend(63 downto 0) := c_in;
 489             if e_in.is_signed = '1' then
 490                 addend(127 downto 64) := (others => c_in(63));
 491             end if;
 492         end if;
 493         if (sign1 xor sign2) = '1' then
 494             addend := not addend;
 495         end if;
 496
 497         x_to_multiply.not_result <= sign1 xor sign2;
 498         x_to_multiply.addend <= addend;
 499         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 500         if e_in.is_32bit = '0' then
 501             -- 64-bit forms
 502             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 503             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 504             if e_in.insn_type = OP_DIVE then
 505                 x_to_divider.is_extended <= '1';
 506             end if;
 507             x_to_divider.dividend <= std_ulogic_vector(abs1);
 508             x_to_divider.divisor <= std_ulogic_vector(abs2);
 509         else
 510             -- 32-bit forms
 511             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 512             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 513             x_to_divider.is_extended <= '0';
 514             if e_in.insn_type = OP_DIVE then   -- extended forms
 515                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 516             else
 517                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 518             end if;
 519             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 520         end if;
 521
 522         case current.sub_select(1 downto 0) is
 523             when "00" =>
 524                 muldiv_result <= multiply_to_x.result(63 downto 0);
 525             when "01" =>
 526                 muldiv_result <= multiply_to_x.result(127 downto 64);
 527             when "10" =>
 528                 muldiv_result <= multiply_to_x.result(63 downto 32) &
 529                                  multiply_to_x.result(63 downto 32);
 530             when others =>
 531                 muldiv_result <= divider_to_x.write_reg_data;
 532         end case;
 533
 534         -- Compute misc_result
 535         case current.sub_select is
 536             when "000" =>
 537                 misc_result <= (others => '0');
 538             when "001" =>
 539                 -- addg6s
 540                 addg6s := (others => '0');
 541                 for i in 0 to 14 loop
 542                     lo := i * 4;
 543                     hi := (i + 1) * 4;
 544                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 545                         addg6s(lo + 3 downto lo) := "0110";
 546                     end if;
 547                 end loop;
 548                 if sum_with_carry(64) = '0' then
 549                     addg6s(63 downto 60) := "0110";
 550                 end if;
 551                 misc_result <= addg6s;
 552             when "010" =>
 553                 -- isel
 554                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 555                 if cr_in(31-crbit) = '1' then
 556                     isel_result := a_in;
 557                 else
 558                     isel_result := b_in;
 559                 end if;
 560                 misc_result <= isel_result;
 561             when "011" =>
 562                 -- darn
 563                 darn := (others => '1');
 564                 if random_err = '0' then
 565                     case e_in.insn(17 downto 16) is
 566                         when "00" =>
 567                             darn := x"00000000" & random_cond(31 downto 0);
 568                         when "10" =>
 569                             darn := random_raw;
 570                         when others =>
 571                             darn := random_cond;
 572                     end case;
 573                 end if;
 574                 misc_result <= darn;
 575             when "100" =>
 576                 -- mfmsr
 577                 misc_result <= ctrl.msr;
 578             when "101" =>
 579                 if e_in.insn(20) = '0' then
 580                     -- mfcr
 581                     mfcr_result := x"00000000" & cr_in;
 582                 else
 583                     -- mfocrf
 584                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 585                     mfcr_result := (others => '0');
 586                     for i in 0 to 7 loop
 587                         lo := (7-i)*4;
 588                         hi := lo + 3;
 589                         if crnum = i then
 590                             mfcr_result(hi downto lo) := cr_in(hi downto lo);
 591                         end if;
 592                     end loop;
 593                 end if;
 594                 misc_result <= mfcr_result;
 595             when "110" =>
 596                 -- setb
 597                 bfa := insn_bfa(e_in.insn);
 598                 crbit := to_integer(unsigned(bfa)) * 4;
 599                 setb_result := (others => '0');
 600                 if cr_in(31 - crbit) = '1' then
 601                     setb_result := (others => '1');
 602                 elsif cr_in(30 - crbit) = '1' then
 603                     setb_result(0) := '1';
 604                 end if;
 605                 misc_result <= setb_result;
 606             when others =>
 607                 misc_result <= (others => '0');
 608         end case;
 609
 610         -- compute comparison results
 611         -- Note, we have done RB - RA, not RA - RB
 612         if e_in.insn_type = OP_CMP then
 613             l := insn_l(e_in.insn);
 614         else
 615             l := not e_in.is_32bit;
 616         end if;
 617         zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 618         zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 619         if zerolo = '1' and (l = '0' or zerohi = '1') then
 620             -- values are equal
 621             trapval := "00100";
 622         else
 623             a_lt_lo := '0';
 624             a_lt_hi := '0';
 625             if unsigned(a_in(30 downto 0)) < unsigned(b_in(30 downto 0)) then
 626                 a_lt_lo := '1';
 627             end if;
 628             if unsigned(a_in(62 downto 31)) < unsigned(b_in(62 downto 31)) then
 629                 a_lt_hi := '1';
 630             end if;
 631             if l = '1' then
 632                 -- 64-bit comparison
 633                 msb_a := a_in(63);
 634                 msb_b := b_in(63);
 635                 a_lt := a_lt_hi or (zerohi and (a_in(31) xnor b_in(31)) and a_lt_lo);
 636             else
 637                 -- 32-bit comparison
 638                 msb_a := a_in(31);
 639                 msb_b := b_in(31);
 640                 a_lt := a_lt_lo;
 641             end if;
 642             if msb_a /= msb_b then
 643                 -- Comparison is clear from MSB difference.
 644                 -- for signed, 0 is greater; for unsigned, 1 is greater
 645                 trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 646             else
 647                 -- MSBs are equal, so signed and unsigned comparisons give the
 648                 -- same answer.
 649                 trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 650             end if;
 651         end if;
 652
 653         ctrl_tmp <= ctrl;
 654         -- FIXME: run at 512MHz not core freq
 655         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 656         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 657
 658         irq_valid := '0';
 659         if ctrl.msr(MSR_EE) = '1' then
 660             if ctrl.dec(63) = '1' then
 661                 v.vector := 16#900#;
 662                 report "IRQ valid: DEC";
 663                 irq_valid := '1';
 664             elsif ext_irq_in = '1' then
 665                 v.vector := 16#500#;
 666                 report "IRQ valid: External";
 667                 irq_valid := '1';
 668             end if;
 669         end if;
 670
 671         v.terminate := '0';
 672         icache_inval <= '0';
 673         v.busy := '0';
 674
 675         -- Next insn adder used in a couple of places
 676         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 677
 678         -- rotator control signals
 679         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 680         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 681         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 682         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 683
 684         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 685         ctrl_tmp.irq_state <= WRITE_SRR0;
 686         exception := '0';
 687         illegal := '0';
 688         exception_nextpc := '0';
 689         v.e.exc_write_enable := '0';
 690         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 691         if valid_in = '1' then
 692             v.e.exc_write_data := e_in.nia;
 693             v.last_nia := e_in.nia;
 694         else
 695             v.e.exc_write_data := r.last_nia;
 696         end if;
 697
 698         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 699
 700         do_trace := valid_in and ctrl.msr(MSR_SE);
 701         if valid_in = '1' then
 702             v.prev_op := e_in.insn_type;
 703         end if;
 704
 705         -- Determine if there is any exception to be taken
 706         -- before/instead of executing this instruction
 707         if valid_in = '1' and e_in.second = '0' then
 708             if HAS_FPU and r.fp_exception_next = '1' then
 709                 -- This is used for FP-type program interrupts that
 710                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 711                 exception := '1';
 712                 v.vector := 16#700#;
 713                 ctrl_tmp.srr1(63 - 43) <= '1';
 714                 ctrl_tmp.srr1(63 - 47) <= '1';
 715             elsif r.trace_next = '1' then
 716                 -- Generate a trace interrupt rather than executing the next instruction
 717                 -- or taking any asynchronous interrupt
 718                 exception := '1';
 719                 v.vector := 16#d00#;
 720                 ctrl_tmp.srr1(63 - 33) <= '1';
 721                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 722                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 723                     ctrl_tmp.srr1(63 - 35) <= '1';
 724                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 725                     ctrl_tmp.srr1(63 - 36) <= '1';
 726                 end if;
 727
 728             elsif irq_valid = '1' then
 729                 -- Don't deliver the interrupt until we have a valid instruction
 730                 -- coming in, so we have a valid NIA to put in SRR0.
 731                 exception := '1';
 732
 733             elsif ctrl.msr(MSR_PR) = '1' and instr_is_privileged(e_in.insn_type, e_in.insn) then
 734                 -- generate a program interrupt
 735                 exception := '1';
 736                 v.vector := 16#700#;
 737                 -- set bit 45 to indicate privileged instruction type interrupt
 738                 ctrl_tmp.srr1(63 - 45) <= '1';
 739                 report "privileged instruction";
 740
 741             elsif not HAS_FPU and e_in.fac = FPU then
 742                 -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 743                 illegal := '1';
 744
 745             elsif HAS_FPU and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
 746                 -- generate a floating-point unavailable interrupt
 747                 exception := '1';
 748                 v.vector := 16#800#;
 749                 report "FP unavailable interrupt";
 750             end if;
 751         end if;
 752
 753         if valid_in = '1' and exception = '0' and illegal = '0' and e_in.unit = ALU then
 754             report "execute nia " & to_hstring(e_in.nia);
 755
 756             v.cur_instr := e_in;
 757             v.next_lr := next_nia;
 758             v.e.valid := '1';
 759
 760             case_0: case e_in.insn_type is
 761
 762             when OP_ILLEGAL =>
 763                 -- we need two cycles to write srr0 and 1
 764                 -- will need more when we have to write HEIR
 765                 illegal := '1';
 766             when OP_SC =>
 767                 -- check bit 1 of the instruction is 1 so we know this is sc;
 768                 -- 0 would mean scv, so generate an illegal instruction interrupt
 769                 -- we need two cycles to write srr0 and 1
 770                 if e_in.insn(1) = '1' then
 771                     exception := '1';
 772                     exception_nextpc := '1';
 773                     v.vector := 16#C00#;
 774                     report "sc";
 775                 else
 776                     illegal := '1';
 777                 end if;
 778             when OP_ATTN =>
 779                 -- check bits 1-10 of the instruction to make sure it's attn
 780                 -- if not then it is illegal
 781                 if e_in.insn(10 downto 1) = "0100000000" then
 782                     v.terminate := '1';
 783                     report "ATTN";
 784                 else
 785                     illegal := '1';
 786                 end if;
 787             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 788                 -- Do nothing
 789             when OP_ADD =>
 790                 if e_in.output_carry = '1' then
 791                     if e_in.input_carry /= OV then
 792                         set_carry(v.e, carry_32, carry_64);
 793                     else
 794                         v.e.xerc.ov := carry_64;
 795                         v.e.xerc.ov32 := carry_32;
 796                         v.e.write_xerc_enable := '1';
 797                     end if;
 798                 end if;
 799                 if e_in.oe = '1' then
 800                     set_ov(v.e,
 801                            calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 802                            calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 803                 end if;
 804             when OP_CMP =>
 805                 -- CMP and CMPL instructions
 806                 if e_in.is_signed = '1' then
 807                     newcrf := trapval(4 downto 2) & v.e.xerc.so;
 808                 else
 809                     newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 810                 end if;
 811                 bf := insn_bf(e_in.insn);
 812                 crnum := to_integer(unsigned(bf));
 813                 v.e.write_cr_enable := '1';
 814                 v.e.write_cr_mask := num_to_fxm(crnum);
 815                 for i in 0 to 7 loop
 816                     lo := i*4;
 817                     hi := lo + 3;
 818                     v.e.write_cr_data(hi downto lo) := newcrf;
 819                 end loop;
 820             when OP_TRAP =>
 821                 -- trap instructions (tw, twi, td, tdi)
 822                 v.vector := 16#700#;
 823                 -- set bit 46 to say trap occurred
 824                 ctrl_tmp.srr1(63 - 46) <= '1';
 825                 if or (trapval and insn_to(e_in.insn)) = '1' then
 826                     -- generate trap-type program interrupt
 827                     exception := '1';
 828                     report "trap";
 829                 end if;
 830             when OP_ADDG6S =>
 831             when OP_CMPRB =>
 832                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 833                 bf := insn_bf(e_in.insn);
 834                 crnum := to_integer(unsigned(bf));
 835                 v.e.write_cr_enable := '1';
 836                 v.e.write_cr_mask := num_to_fxm(crnum);
 837                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 838                                      newcrf & newcrf & newcrf & newcrf;
 839             when OP_CMPEQB =>
 840                 newcrf := ppc_cmpeqb(a_in, b_in);
 841                 bf := insn_bf(e_in.insn);
 842                 crnum := to_integer(unsigned(bf));
 843                 v.e.write_cr_enable := '1';
 844                 v.e.write_cr_mask := num_to_fxm(crnum);
 845                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 846                                      newcrf & newcrf & newcrf & newcrf;
 847             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 848                     OP_BPERM | OP_BCD =>
 849             when OP_B =>
 850                 is_branch := '1';
 851                 taken_branch := '1';
 852                 is_direct_branch := '1';
 853                 abs_branch := insn_aa(e_in.insn);
 854                 if ctrl.msr(MSR_BE) = '1' then
 855                     do_trace := '1';
 856                 end if;
 857             when OP_BC =>
 858                 -- read_data1 is CTR
 859                 bo := insn_bo(e_in.insn);
 860                 bi := insn_bi(e_in.insn);
 861                 is_branch := '1';
 862                 is_direct_branch := '1';
 863                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 864                 abs_branch := insn_aa(e_in.insn);
 865                 if ctrl.msr(MSR_BE) = '1' then
 866                     do_trace := '1';
 867                 end if;
 868             when OP_BCREG =>
 869                 -- read_data1 is CTR
 870                 -- read_data2 is target register (CTR, LR or TAR)
 871                 bo := insn_bo(e_in.insn);
 872                 bi := insn_bi(e_in.insn);
 873                 is_branch := '1';
 874                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 875                 abs_branch := '1';
 876                 if ctrl.msr(MSR_BE) = '1' then
 877                     do_trace := '1';
 878                 end if;
 879
 880             when OP_RFID =>
 881                 v.redir_mode := (a_in(MSR_IR) or a_in(MSR_PR)) & not a_in(MSR_PR) &
 882                                 not a_in(MSR_LE) & not a_in(MSR_SF);
 883                 -- Can't use msr_copy here because the partial function MSR
 884                 -- bits should be left unchanged, not zeroed.
 885                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 886                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 887                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 888                 if a_in(MSR_PR) = '1' then
 889                     ctrl_tmp.msr(MSR_EE) <= '1';
 890                     ctrl_tmp.msr(MSR_IR) <= '1';
 891                     ctrl_tmp.msr(MSR_DR) <= '1';
 892                 end if;
 893                 -- mark this as a branch so CFAR gets updated
 894                 is_branch := '1';
 895                 taken_branch := '1';
 896                 abs_branch := '1';
 897                 if HAS_FPU then
 898                     v.fp_exception_next := fp_in.exception and
 899                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 900                 end if;
 901                 do_trace := '0';
 902
 903             when OP_CNTZ =>
 904                 v.e.valid := '0';
 905                 v.cntz_in_progress := '1';
 906                 v.busy := '1';
 907             when OP_ISEL =>
 908             when OP_CROP =>
 909                 cr_op := insn_cr(e_in.insn);
 910                 report "CR OP " & to_hstring(cr_op);
 911                 if cr_op(0) = '0' then -- MCRF
 912                     bf := insn_bf(e_in.insn);
 913                     bfa := insn_bfa(e_in.insn);
 914                     v.e.write_cr_enable := '1';
 915                     crnum := to_integer(unsigned(bf));
 916                     scrnum := to_integer(unsigned(bfa));
 917                     v.e.write_cr_mask := num_to_fxm(crnum);
 918                     for i in 0 to 7 loop
 919                         lo := (7-i)*4;
 920                         hi := lo + 3;
 921                         if i = scrnum then
 922                             newcrf := cr_in(hi downto lo);
 923                         end if;
 924                     end loop;
 925                     for i in 0 to 7 loop
 926                         lo := i*4;
 927                         hi := lo + 3;
 928                         v.e.write_cr_data(hi downto lo) := newcrf;
 929                     end loop;
 930                 else
 931                     v.e.write_cr_enable := '1';
 932                     bt := insn_bt(e_in.insn);
 933                     ba := insn_ba(e_in.insn);
 934                     bb := insn_bb(e_in.insn);
 935                     btnum := 31 - to_integer(unsigned(bt));
 936                     banum := 31 - to_integer(unsigned(ba));
 937                     bbnum := 31 - to_integer(unsigned(bb));
 938                     -- Bits 5-8 of cr_op give the truth table of the requested
 939                     -- logical operation
 940                     cr_operands := cr_in(banum) & cr_in(bbnum);
 941                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 942                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 943                     for i in 0 to 31 loop
 944                         if i = btnum then
 945                             v.e.write_cr_data(i) := crresult;
 946                         else
 947                             v.e.write_cr_data(i) := cr_in(i);
 948                         end if;
 949                     end loop;
 950                 end if;
 951             when OP_MCRXRX =>
 952                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 953                 bf := insn_bf(e_in.insn);
 954                 crnum := to_integer(unsigned(bf));
 955                 v.e.write_cr_enable := '1';
 956                 v.e.write_cr_mask := num_to_fxm(crnum);
 957                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 958                                      newcrf & newcrf & newcrf & newcrf;
 959             when OP_DARN =>
 960             when OP_MFMSR =>
 961             when OP_MFSPR =>
 962                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 963                     "=" & to_hstring(a_in);
 964                 if is_fast_spr(e_in.read_reg1) = '1' then
 965                     spr_val := a_in;
 966                     if decode_spr_num(e_in.insn) = SPR_XER then
 967                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 968                         spr_val(63 downto 32) := (others => '0');
 969                         spr_val(63-32) := v.e.xerc.so;
 970                         spr_val(63-33) := v.e.xerc.ov;
 971                         spr_val(63-34) := v.e.xerc.ca;
 972                         spr_val(63-35 downto 63-43) := "000000000";
 973                         spr_val(63-44) := v.e.xerc.ov32;
 974                         spr_val(63-45) := v.e.xerc.ca32;
 975                     end if;
 976                 else
 977                     spr_val := c_in;
 978                     case decode_spr_num(e_in.insn) is
 979                     when SPR_TB =>
 980                         spr_val := ctrl.tb;
 981                     when SPR_TBU =>
 982                         spr_val(63 downto 32) := (others => '0');
 983                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 984                     when SPR_DEC =>
 985                         spr_val := ctrl.dec;
 986                     when SPR_CFAR =>
 987                         spr_val := ctrl.cfar;
 988                     when SPR_PVR =>
 989                         spr_val(63 downto 32) := (others => '0');
 990                         spr_val(31 downto 0) := PVR_MICROWATT;
 991                     when 724 =>     -- LOG_ADDR SPR
 992                         spr_val := log_wr_addr & r.log_addr_spr;
 993                     when 725 =>     -- LOG_DATA SPR
 994                         spr_val := log_rd_data;
 995                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 996                     when others =>
 997                         -- mfspr from unimplemented SPRs should be a nop in
 998                         -- supervisor mode and a program interrupt for user mode
 999                         if is_fast_spr(e_in.read_reg1) = '0' and ctrl.msr(MSR_PR) = '1' then
1000                             illegal := '1';
1001                         end if;
1002                     end case;
1003                 end if;
1004                 spr_result <= spr_val;
1005
1006             when OP_MFCR =>
1007             when OP_MTCRF =>
1008                 v.e.write_cr_enable := '1';
1009                 if e_in.insn(20) = '0' then
1010                     -- mtcrf
1011                     v.e.write_cr_mask := insn_fxm(e_in.insn);
1012                 else
1013                     -- mtocrf: We require one hot priority encoding here
1014                     crnum := fxm_to_num(insn_fxm(e_in.insn));
1015                     v.e.write_cr_mask := num_to_fxm(crnum);
1016                 end if;
1017                 v.e.write_cr_data := c_in(31 downto 0);
1018             when OP_MTMSRD =>
1019                 if e_in.insn(16) = '1' then
1020                     -- just update EE and RI
1021                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
1022                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
1023                 else
1024                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
1025                     -- and 63 (LE) (IBM bit numbering)
1026                     if e_in.is_32bit = '0' then
1027                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
1028                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
1029                     end if;
1030                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
1031                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
1032                     if c_in(MSR_PR) = '1' then
1033                         ctrl_tmp.msr(MSR_EE) <= '1';
1034                         ctrl_tmp.msr(MSR_IR) <= '1';
1035                         ctrl_tmp.msr(MSR_DR) <= '1';
1036                     end if;
1037                     if HAS_FPU then
1038                         v.fp_exception_next := fp_in.exception and
1039                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
1040                     end if;
1041                 end if;
1042             when OP_MTSPR =>
1043                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
1044                     "=" & to_hstring(c_in);
1045                 if is_fast_spr(e_in.write_reg) then
1046                     if decode_spr_num(e_in.insn) = SPR_XER then
1047                         v.e.xerc.so := c_in(63-32);
1048                         v.e.xerc.ov := c_in(63-33);
1049                         v.e.xerc.ca := c_in(63-34);
1050                         v.e.xerc.ov32 := c_in(63-44);
1051                         v.e.xerc.ca32 := c_in(63-45);
1052                         v.e.write_xerc_enable := '1';
1053                     end if;
1054                 else
1055                     -- slow spr
1056                     case decode_spr_num(e_in.insn) is
1057                     when SPR_DEC =>
1058                         ctrl_tmp.dec <= c_in;
1059                     when 724 =>     -- LOG_ADDR SPR
1060                         v.log_addr_spr := c_in(31 downto 0);
1061                     when others =>
1062                         -- mtspr to unimplemented SPRs should be a nop in
1063                         -- supervisor mode and a program interrupt for user mode
1064                         if ctrl.msr(MSR_PR) = '1' then
1065                             illegal := '1';
1066                         end if;
1067                     end case;
1068                 end if;
1069             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1070                 if e_in.output_carry = '1' then
1071                     set_carry(v.e, rotator_carry, rotator_carry);
1072                 end if;
1073             when OP_SETB =>
1074
1075             when OP_ISYNC =>
1076                 v.redirect := '1';
1077                 v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1078
1079             when OP_ICBI =>
1080                 icache_inval <= '1';
1081
1082             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1083                 v.e.valid := '0';
1084                 v.mul_in_progress := '1';
1085                 v.busy := '1';
1086                 x_to_multiply.valid <= '1';
1087
1088             when OP_DIV | OP_DIVE | OP_MOD =>
1089                 v.e.valid := '0';
1090                 v.div_in_progress := '1';
1091                 v.busy := '1';
1092                 x_to_divider.valid <= '1';
1093
1094             when others =>
1095                 v.terminate := '1';
1096                 report "illegal";
1097             end case;
1098
1099             -- Mispredicted branches cause a redirect
1100             if is_branch = '1' then
1101                 if taken_branch = '1' then
1102                     ctrl_tmp.cfar <= e_in.nia;
1103                 end if;
1104                 if taken_branch = '1' then
1105                     v.br_offset := b_in;
1106                     v.abs_br := abs_branch;
1107                 else
1108                     v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1109                 end if;
1110                 if taken_branch /= e_in.br_pred then
1111                     v.redirect := '1';
1112                 end if;
1113                 v.br_last := is_direct_branch;
1114                 v.taken_br := taken_branch;
1115             end if;
1116
1117         elsif valid_in = '1' and exception = '0' and illegal = '0' then
1118             -- instruction for other units, i.e. LDST
1119             if e_in.unit = LDST then
1120                 lv.valid := '1';
1121             elsif e_in.unit = NONE then
1122                 illegal := '1';
1123             elsif HAS_FPU and e_in.unit = FPU then
1124                 fv.valid := '1';
1125             end if;
1126             -- Handling an ITLB miss doesn't count as having executed an instruction
1127             if e_in.insn_type = OP_FETCH_FAILED then
1128                 do_trace := '0';
1129             end if;
1130         end if;
1131
1132         -- The following cases all occur when r.busy = 1 and therefore
1133         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1134         -- the cases above which depend on valid_in = 1.
1135
1136         if ctrl.irq_state = WRITE_SRR1 then
1137             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
1138             v.e.exc_write_data := ctrl.srr1;
1139             v.e.exc_write_enable := '1';
1140             ctrl_tmp.msr(MSR_SF) <= '1';
1141             ctrl_tmp.msr(MSR_EE) <= '0';
1142             ctrl_tmp.msr(MSR_PR) <= '0';
1143             ctrl_tmp.msr(MSR_SE) <= '0';
1144             ctrl_tmp.msr(MSR_BE) <= '0';
1145             ctrl_tmp.msr(MSR_FP) <= '0';
1146             ctrl_tmp.msr(MSR_FE0) <= '0';
1147             ctrl_tmp.msr(MSR_FE1) <= '0';
1148             ctrl_tmp.msr(MSR_IR) <= '0';
1149             ctrl_tmp.msr(MSR_DR) <= '0';
1150             ctrl_tmp.msr(MSR_RI) <= '0';
1151             ctrl_tmp.msr(MSR_LE) <= '1';
1152             v.trace_next := '0';
1153             v.fp_exception_next := '0';
1154             report "Writing SRR1: " & to_hstring(ctrl.srr1);
1155
1156         elsif r.cntz_in_progress = '1' then
1157             -- cnt[lt]z always takes two cycles
1158             v.e.valid := '1';
1159         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1160             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1161                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1162                 if r.mul_in_progress = '1' then
1163                     overflow := '0';
1164                 else
1165                     overflow := divider_to_x.overflow;
1166                 end if;
1167                 if r.mul_in_progress = '1' and current.oe = '1' then
1168                     -- have to wait until next cycle for overflow indication
1169                     v.mul_finish := '1';
1170                     v.busy := '1';
1171                 else
1172                     v.e.write_xerc_enable := current.oe;
1173                     -- We must test oe because the RC update code in writeback
1174                     -- will use the xerc value to set CR0:SO so we must not clobber
1175                     -- xerc if OE wasn't set.
1176                     if current.oe = '1' then
1177                         v.e.xerc.ov := overflow;
1178                         v.e.xerc.ov32 := overflow;
1179                         if overflow = '1' then
1180                             v.e.xerc.so := '1';
1181                         end if;
1182                     end if;
1183                     v.e.valid := '1';
1184                 end if;
1185             else
1186                 v.busy := '1';
1187                 v.mul_in_progress := r.mul_in_progress;
1188                 v.div_in_progress := r.div_in_progress;
1189             end if;
1190         elsif r.mul_finish = '1' then
1191             hold_wr_data := '1';
1192             v.e.write_xerc_enable := current.oe;
1193             v.e.xerc.ov := multiply_to_x.overflow;
1194             v.e.xerc.ov32 := multiply_to_x.overflow;
1195             if multiply_to_x.overflow = '1' then
1196                 v.e.xerc.so := '1';
1197             end if;
1198             v.e.valid := '1';
1199         end if;
1200         -- When doing delayed LR update, keep r.e.write_data unchanged
1201         -- next cycle in case it is needed for a forwarded result (e.g. CTR).
1202         if r.lr_update = '1' then
1203             hold_wr_data := '1';
1204         end if;
1205
1206         -- Generate FP-type program interrupt.  fp_in.interrupt will only
1207         -- be set during the execution of a FP instruction.
1208         -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1209         -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1210         if HAS_FPU and fp_in.interrupt = '1' then
1211             v.vector := 16#700#;
1212             ctrl_tmp.srr1(63 - 43) <= '1';
1213             exception := '1';
1214         end if;
1215
1216         if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1217             exception := '1';
1218             v.vector := 16#700#;
1219             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1220             -- set bit 44 to indicate we have an illegal
1221             ctrl_tmp.srr1(63 - 44) <= '1';
1222             report "illegal";
1223         end if;
1224         if exception = '1' then
1225             v.e.exc_write_enable := '1';
1226             if exception_nextpc = '1' then
1227                 v.e.exc_write_data := next_nia;
1228             end if;
1229         end if;
1230
1231         -- generate DSI or DSegI for load/store exceptions
1232         -- or ISI or ISegI for instruction fetch exceptions
1233         if l_in.exception = '1' then
1234             if l_in.alignment = '1' then
1235                 v.vector := 16#600#;
1236             elsif l_in.instr_fault = '0' then
1237                 if l_in.segment_fault = '0' then
1238                     v.vector := 16#300#;
1239                 else
1240                     v.vector := 16#380#;
1241                 end if;
1242             else
1243                 if l_in.segment_fault = '0' then
1244                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1245                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1246                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1247                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1248                     v.vector := 16#400#;
1249                 else
1250                     v.vector := 16#480#;
1251                 end if;
1252             end if;
1253             v.e.exc_write_enable := '1';
1254             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1255             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1256         end if;
1257
1258         if exception = '1' or l_in.exception = '1' then
1259             ctrl_tmp.irq_state <= WRITE_SRR1;
1260             v.redirect := '1';
1261             v.do_intr := '1';
1262         end if;
1263
1264         if do_trace = '1' then
1265             v.trace_next := '1';
1266         end if;
1267
1268         if hold_wr_data = '0' then
1269             v.e.write_data := alu_result;
1270         else
1271             v.e.write_data := r.e.write_data;
1272         end if;
1273         v.e.write_reg := current.write_reg;
1274         v.e.write_enable := current.write_reg_enable and v.e.valid and not exception;
1275         v.e.rc := current.rc and v.e.valid and not exception;
1276
1277         -- Update LR on the next cycle after a branch link
1278         -- If we're not writing back anything else, we can write back LR
1279         -- this cycle, otherwise we take an extra cycle.  We use the
1280         -- exc_write path since next_nia is written through that path
1281         -- in other places.
1282         if v.e.valid = '1' and exception = '0' and current.lr = '1' then
1283             if current.write_reg_enable = '0' then
1284                 v.e.exc_write_enable := '1';
1285                 v.e.exc_write_data := next_nia;
1286                 v.e.exc_write_reg := fast_spr_num(SPR_LR);
1287             else
1288                 v.lr_update := '1';
1289                 v.e.valid := '0';
1290                 report "Delayed LR update to " & to_hstring(next_nia);
1291                 v.busy := '1';
1292             end if;
1293         end if;
1294         if r.lr_update = '1' then
1295             v.e.exc_write_enable := '1';
1296             v.e.exc_write_data := r.next_lr;
1297             v.e.exc_write_reg := fast_spr_num(SPR_LR);
1298             v.e.valid := '1';
1299         end if;
1300
1301         -- Defer completion for one cycle when redirecting.
1302         -- This also ensures r.busy = 1 when ctrl.irq_state = WRITE_SRR1
1303         if v.redirect = '1' then
1304             v.busy := '1';
1305             v.e.valid := '0';
1306         end if;
1307         if r.redirect = '1' then
1308             v.e.valid := '1';
1309         end if;
1310
1311         -- Outputs to fetch1
1312         f.redirect := r.redirect;
1313         f.br_nia := r.last_nia;
1314         f.br_last := r.br_last and not r.do_intr;
1315         f.br_taken := r.taken_br;
1316         if r.do_intr = '1' then
1317             f.redirect_nia := std_ulogic_vector(to_unsigned(r.vector, 64));
1318             f.virt_mode := '0';
1319             f.priv_mode := '1';
1320             -- XXX need an interrupt LE bit here, e.g. from LPCR
1321             f.big_endian := '0';
1322             f.mode_32bit := '0';
1323         else
1324             if r.abs_br = '1' then
1325                 f.redirect_nia := r.br_offset;
1326             else
1327                 f.redirect_nia := std_ulogic_vector(unsigned(r.last_nia) + unsigned(r.br_offset));
1328             end if;
1329             -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
1330             f.virt_mode := r.redir_mode(3);
1331             f.priv_mode := r.redir_mode(2);
1332             f.big_endian := r.redir_mode(1);
1333             f.mode_32bit := r.redir_mode(0);
1334         end if;
1335
1336         -- Outputs to loadstore1 (async)
1337         lv.op := e_in.insn_type;
1338         lv.nia := e_in.nia;
1339         lv.addr1 := a_in;
1340         lv.addr2 := b_in;
1341         lv.data := c_in;
1342         lv.write_reg := e_in.write_reg;
1343         lv.length := e_in.data_len;
1344         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1345         lv.sign_extend := e_in.sign_extend;
1346         lv.update := e_in.update;
1347         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1348         lv.xerc := v.e.xerc;
1349         lv.reserve := e_in.reserve;
1350         lv.rc := e_in.rc;
1351         lv.insn := e_in.insn;
1352         -- decode l*cix and st*cix instructions here
1353         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1354             e_in.insn(5 downto 1) = "10101" then
1355             lv.ci := '1';
1356         end if;
1357         lv.virt_mode := ctrl.msr(MSR_DR);
1358         lv.priv_mode := not ctrl.msr(MSR_PR);
1359         lv.mode_32bit := not ctrl.msr(MSR_SF);
1360         lv.is_32bit := e_in.is_32bit;
1361         lv.repeat := e_in.repeat;
1362         lv.second := e_in.second;
1363
1364         -- Outputs to FPU
1365         fv.op := e_in.insn_type;
1366         fv.nia := e_in.nia;
1367         fv.insn := e_in.insn;
1368         fv.single := e_in.is_32bit;
1369         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1370         fv.fra := a_in;
1371         fv.frb := b_in;
1372         fv.frc := c_in;
1373         fv.frt := e_in.write_reg;
1374         fv.rc := e_in.rc;
1375         fv.out_cr := e_in.output_cr;
1376
1377         -- Update registers
1378         rin <= v;
1379
1380         -- update outputs
1381         f_out <= f;
1382         l_out <= lv;
1383         e_out <= r.e;
1384         fp_out <= fv;
1385         flush_out <= f_out.redirect;
1386
1387         exception_log <= exception;
1388         irq_valid_log <= irq_valid;
1389     end process;
1390
1391     e1_log: if LOG_LENGTH > 0 generate
1392         signal log_data : std_ulogic_vector(14 downto 0);
1393     begin
1394         ex1_log : process(clk)
1395         begin
1396             if rising_edge(clk) then
1397                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1398                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1399                             exception_log &
1400                             irq_valid_log &
1401                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1402                             "000" &
1403                             r.e.write_enable &
1404                             r.e.valid &
1405                             f_out.redirect &
1406                             r.busy &
1407                             flush_out;
1408             end if;
1409         end process;
1410         log_out <= log_data;
1411     end generate;
1412 end architecture behaviour;