execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         -- Non-zero to enable log data collection
  17         LOG_LENGTH : natural := 0
  18         );
  19     port (
  20         clk   : in std_ulogic;
  21         rst   : in std_ulogic;
  22
  23         -- asynchronous
  24         flush_out : out std_ulogic;
  25         busy_out : out std_ulogic;
  26
  27         e_in  : in Decode2ToExecute1Type;
  28         l_in  : in Loadstore1ToExecute1Type;
  29
  30         ext_irq_in : std_ulogic;
  31
  32         -- asynchronous
  33         l_out : out Execute1ToLoadstore1Type;
  34         f_out : out Execute1ToFetch1Type;
  35
  36         e_out : out Execute1ToWritebackType;
  37
  38         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  39
  40         icache_inval : out std_ulogic;
  41         terminate_out : out std_ulogic;
  42
  43         log_out : out std_ulogic_vector(14 downto 0);
  44         log_rd_addr : out std_ulogic_vector(31 downto 0);
  45         log_rd_data : in std_ulogic_vector(63 downto 0);
  46         log_wr_addr : in std_ulogic_vector(31 downto 0)
  47         );
  48 end entity execute1;
  49
  50 architecture behaviour of execute1 is
  51     type reg_type is record
  52         e : Execute1ToWritebackType;
  53         f : Execute1ToFetch1Type;
  54         busy: std_ulogic;
  55         terminate: std_ulogic;
  56         trace_next : std_ulogic;
  57         prev_op : insn_type_t;
  58         lr_update : std_ulogic;
  59         next_lr : std_ulogic_vector(63 downto 0);
  60         mul_in_progress : std_ulogic;
  61         mul_finish : std_ulogic;
  62         div_in_progress : std_ulogic;
  63         cntz_in_progress : std_ulogic;
  64         slow_op_insn : insn_type_t;
  65         slow_op_dest : gpr_index_t;
  66         slow_op_rc : std_ulogic;
  67         slow_op_oe : std_ulogic;
  68         slow_op_xerc : xer_common_t;
  69         last_nia : std_ulogic_vector(63 downto 0);
  70         log_addr_spr : std_ulogic_vector(31 downto 0);
  71     end record;
  72     constant reg_type_init : reg_type :=
  73         (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
  74          busy => '0', lr_update => '0', terminate => '0', trace_next => '0', prev_op => OP_ILLEGAL,
  75          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  76          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  77          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
  78
  79     signal r, rin : reg_type;
  80
  81     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  82     signal cr_in : std_ulogic_vector(31 downto 0);
  83
  84     signal valid_in : std_ulogic;
  85     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  86     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  87     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  88     signal rot_sign_ext: std_ulogic;
  89     signal rotator_result: std_ulogic_vector(63 downto 0);
  90     signal rotator_carry: std_ulogic;
  91     signal logical_result: std_ulogic_vector(63 downto 0);
  92     signal countzero_result: std_ulogic_vector(63 downto 0);
  93
  94     -- multiply signals
  95     signal x_to_multiply: MultiplyInputType;
  96     signal multiply_to_x: MultiplyOutputType;
  97
  98     -- divider signals
  99     signal x_to_divider: Execute1ToDividerType;
 100     signal divider_to_x: DividerToExecute1Type;
 101
 102     -- random number generator signals
 103     signal random_raw  : std_ulogic_vector(63 downto 0);
 104     signal random_cond : std_ulogic_vector(63 downto 0);
 105     signal random_err  : std_ulogic;
 106
 107     -- signals for logging
 108     signal exception_log : std_ulogic;
 109     signal irq_valid_log : std_ulogic;
 110
 111     type privilege_level is (USER, SUPER);
 112     type op_privilege_array is array(insn_type_t) of privilege_level;
 113     constant op_privilege: op_privilege_array := (
 114         OP_ATTN => SUPER,
 115         OP_MFMSR => SUPER,
 116         OP_MTMSRD => SUPER,
 117         OP_RFID => SUPER,
 118         OP_TLBIE => SUPER,
 119         others => USER
 120         );
 121
 122     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 123         return boolean is
 124     begin
 125         if op_privilege(op) = SUPER then
 126             return true;
 127         elsif op = OP_MFSPR or op = OP_MTSPR then
 128             return insn(20) = '1';
 129         else
 130             return false;
 131         end if;
 132     end;
 133
 134     procedure set_carry(e: inout Execute1ToWritebackType;
 135                         carry32 : in std_ulogic;
 136                         carry : in std_ulogic) is
 137     begin
 138         e.xerc.ca32 := carry32;
 139         e.xerc.ca := carry;
 140         e.write_xerc_enable := '1';
 141     end;
 142
 143     procedure set_ov(e: inout Execute1ToWritebackType;
 144                      ov   : in std_ulogic;
 145                      ov32 : in std_ulogic) is
 146     begin
 147         e.xerc.ov32 := ov32;
 148         e.xerc.ov := ov;
 149         if ov = '1' then
 150             e.xerc.so := '1';
 151         end if;
 152         e.write_xerc_enable := '1';
 153     end;
 154
 155     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 156                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 157     begin
 158         return (ca xor msb_r) and not (msb_a xor msb_b);
 159     end;
 160
 161     function decode_input_carry(ic : carry_in_t;
 162                                 xerc : xer_common_t) return std_ulogic is
 163     begin
 164         case ic is
 165         when ZERO =>
 166             return '0';
 167         when CA =>
 168             return xerc.ca;
 169         when OV =>
 170             return xerc.ov;
 171         when ONE =>
 172             return '1';
 173         end case;
 174     end;
 175
 176     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 177         return std_ulogic_vector is
 178         variable msr_out: std_ulogic_vector(63 downto 0);
 179     begin
 180         -- ISA says this:
 181         --  Defined MSR bits are classified as either full func-
 182         --  tion or partial function. Full function MSR bits are
 183         --  saved in SRR1 or HSRR1 when an interrupt other
 184         --  than a System Call Vectored interrupt occurs and
 185         --  restored by rfscv, rfid, or hrfid, while partial func-
 186         --  tion MSR bits are not saved or restored.
 187         --  Full function MSR bits lie in the range 0:32, 37:41, and
 188         --  48:63, and partial function MSR bits lie in the range
 189         --  33:36 and 42:47. (Note this is IBM bit numbering).
 190         msr_out := (others => '0');
 191         msr_out(63 downto 31) := msr(63 downto 31);
 192         msr_out(26 downto 22) := msr(26 downto 22);
 193         msr_out(15 downto 0)  := msr(15 downto 0);
 194         return msr_out;
 195     end;
 196
 197     -- Tell vivado to keep the hierarchy for the random module so that the
 198     -- net names in the xdc file match.
 199     attribute keep_hierarchy : string;
 200     attribute keep_hierarchy of random_0 : label is "yes";
 201
 202 begin
 203
 204     rotator_0: entity work.rotator
 205         port map (
 206             rs => c_in,
 207             ra => a_in,
 208             shift => b_in(6 downto 0),
 209             insn => e_in.insn,
 210             is_32bit => e_in.is_32bit,
 211             right_shift => right_shift,
 212             arith => e_in.is_signed,
 213             clear_left => rot_clear_left,
 214             clear_right => rot_clear_right,
 215             sign_ext_rs => rot_sign_ext,
 216             result => rotator_result,
 217             carry_out => rotator_carry
 218             );
 219
 220     logical_0: entity work.logical
 221         port map (
 222             rs => c_in,
 223             rb => b_in,
 224             op => e_in.insn_type,
 225             invert_in => e_in.invert_a,
 226             invert_out => e_in.invert_out,
 227             result => logical_result,
 228             datalen => e_in.data_len
 229             );
 230
 231     countzero_0: entity work.zero_counter
 232         port map (
 233             clk => clk,
 234             rs => c_in,
 235             count_right => e_in.insn(10),
 236             is_32bit => e_in.is_32bit,
 237             result => countzero_result
 238             );
 239
 240     multiply_0: entity work.multiply
 241         port map (
 242             clk => clk,
 243             m_in => x_to_multiply,
 244             m_out => multiply_to_x
 245             );
 246
 247     divider_0: entity work.divider
 248         port map (
 249             clk => clk,
 250             rst => rst,
 251             d_in => x_to_divider,
 252             d_out => divider_to_x
 253             );
 254
 255     random_0: entity work.random
 256         port map (
 257             clk => clk,
 258             data => random_cond,
 259             raw => random_raw,
 260             err => random_err
 261             );
 262
 263     dbg_msr_out <= ctrl.msr;
 264     log_rd_addr <= r.log_addr_spr;
 265
 266     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 267     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 268     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 269
 270     busy_out <= l_in.busy or r.busy;
 271     valid_in <= e_in.valid and not busy_out;
 272
 273     terminate_out <= r.terminate;
 274
 275     execute1_0: process(clk)
 276     begin
 277         if rising_edge(clk) then
 278             if rst = '1' then
 279                 r <= reg_type_init;
 280                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 281                 ctrl.irq_state <= WRITE_SRR0;
 282             else
 283                 r <= rin;
 284                 ctrl <= ctrl_tmp;
 285                 assert not (r.lr_update = '1' and valid_in = '1')
 286                     report "LR update collision with valid in EX1"
 287                     severity failure;
 288                 if r.lr_update = '1' then
 289                     report "LR update to " & to_hstring(r.next_lr);
 290                 end if;
 291             end if;
 292         end if;
 293     end process;
 294
 295     execute1_1: process(all)
 296         variable v : reg_type;
 297         variable a_inv : std_ulogic_vector(63 downto 0);
 298         variable result : std_ulogic_vector(63 downto 0);
 299         variable newcrf : std_ulogic_vector(3 downto 0);
 300         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 301         variable result_en : std_ulogic;
 302         variable crnum : crnum_t;
 303         variable crbit : integer range 0 to 31;
 304         variable scrnum : crnum_t;
 305         variable lo, hi : integer;
 306         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 307         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 308         variable bo, bi : std_ulogic_vector(4 downto 0);
 309         variable bf, bfa : std_ulogic_vector(2 downto 0);
 310         variable cr_op : std_ulogic_vector(9 downto 0);
 311         variable cr_operands : std_ulogic_vector(1 downto 0);
 312         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 313         variable btnum, banum, bbnum : integer range 0 to 31;
 314         variable crresult : std_ulogic;
 315         variable l : std_ulogic;
 316         variable next_nia : std_ulogic_vector(63 downto 0);
 317         variable carry_32, carry_64 : std_ulogic;
 318         variable sign1, sign2 : std_ulogic;
 319         variable abs1, abs2 : signed(63 downto 0);
 320         variable overflow : std_ulogic;
 321         variable zerohi, zerolo : std_ulogic;
 322         variable msb_a, msb_b : std_ulogic;
 323         variable a_lt : std_ulogic;
 324         variable lv : Execute1ToLoadstore1Type;
 325         variable irq_valid : std_ulogic;
 326         variable exception : std_ulogic;
 327         variable exception_nextpc : std_ulogic;
 328         variable trapval : std_ulogic_vector(4 downto 0);
 329         variable illegal : std_ulogic;
 330         variable is_branch : std_ulogic;
 331         variable taken_branch : std_ulogic;
 332         variable abs_branch : std_ulogic;
 333         variable spr_val : std_ulogic_vector(63 downto 0);
 334         variable addend : std_ulogic_vector(127 downto 0);
 335         variable do_trace : std_ulogic;
 336     begin
 337         result := (others => '0');
 338         sum_with_carry := (others => '0');
 339         result_en := '0';
 340         newcrf := (others => '0');
 341         is_branch := '0';
 342         taken_branch := '0';
 343         abs_branch := '0';
 344
 345         v := r;
 346         v.e := Execute1ToWritebackInit;
 347         lv := Execute1ToLoadstore1Init;
 348         v.f.redirect := '0';
 349
 350         -- XER forwarding. To avoid having to track XER hazards, we
 351         -- use the previously latched value.
 352         --
 353         -- If the XER was modified by a multiply or a divide, those are
 354         -- single issue, we'll get the up to date value from decode2 from
 355         -- the register file.
 356         --
 357         -- If it was modified by an instruction older than the previous
 358         -- one in EX1, it will have also hit writeback and will be up
 359         -- to date in decode2.
 360         --
 361         -- That leaves us with the case where it was updated by the previous
 362         -- instruction in EX1. In that case, we can forward it back here.
 363         --
 364         -- This will break if we allow pipelining of multiply and divide,
 365         -- but ideally, those should go via EX1 anyway and run as a state
 366         -- machine from here.
 367         --
 368         -- One additional hazard to beware of is an XER:SO modifying instruction
 369         -- in EX1 followed immediately by a store conditional. Due to our
 370         -- writeback latency, the store will go down the LSU with the previous
 371         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 372         --
 373         -- We will need to handle that if we ever make stcx. not single issue
 374         --
 375         -- We always pass a valid XER value downto writeback even when
 376         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 377         -- to work for RC instructions.
 378         --
 379         if r.e.write_xerc_enable = '1' then
 380             v.e.xerc := r.e.xerc;
 381         else
 382             v.e.xerc := e_in.xerc;
 383         end if;
 384
 385         -- CR forwarding
 386         cr_in <= e_in.cr;
 387         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 388             for i in 0 to 7 loop
 389                 if r.e.write_cr_mask(i) = '1' then
 390                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 391                 end if;
 392             end loop;
 393         end if;
 394
 395         v.lr_update := '0';
 396         v.mul_in_progress := '0';
 397         v.div_in_progress := '0';
 398         v.cntz_in_progress := '0';
 399         v.mul_finish := '0';
 400
 401         -- Main adder
 402         if e_in.invert_a = '0' then
 403             a_inv := a_in;
 404         else
 405             a_inv := not a_in;
 406         end if;
 407         sum_with_carry := ppc_adde(a_inv, b_in,
 408                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 409
 410         -- signals to multiply and divide units
 411         sign1 := '0';
 412         sign2 := '0';
 413         if e_in.is_signed = '1' then
 414             if e_in.is_32bit = '1' then
 415                 sign1 := a_in(31);
 416                 sign2 := b_in(31);
 417             else
 418                 sign1 := a_in(63);
 419                 sign2 := b_in(63);
 420             end if;
 421         end if;
 422         -- take absolute values
 423         if sign1 = '0' then
 424             abs1 := signed(a_in);
 425         else
 426             abs1 := - signed(a_in);
 427         end if;
 428         if sign2 = '0' then
 429             abs2 := signed(b_in);
 430         else
 431             abs2 := - signed(b_in);
 432         end if;
 433
 434         x_to_multiply <= MultiplyInputInit;
 435         x_to_multiply.is_32bit <= e_in.is_32bit;
 436
 437         x_to_divider <= Execute1ToDividerInit;
 438         x_to_divider.is_signed <= e_in.is_signed;
 439         x_to_divider.is_32bit <= e_in.is_32bit;
 440         if e_in.insn_type = OP_MOD then
 441             x_to_divider.is_modulus <= '1';
 442         end if;
 443
 444         addend := (others => '0');
 445         if e_in.insn(26) = '0' then
 446             -- integer multiply-add, major op 4 (if it is a multiply)
 447             addend(63 downto 0) := c_in;
 448             if e_in.is_signed = '1' then
 449                 addend(127 downto 64) := (others => c_in(63));
 450             end if;
 451         end if;
 452         if (sign1 xor sign2) = '1' then
 453             addend := not addend;
 454         end if;
 455
 456         x_to_multiply.not_result <= sign1 xor sign2;
 457         x_to_multiply.addend <= addend;
 458         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 459         if e_in.is_32bit = '0' then
 460             -- 64-bit forms
 461             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 462             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 463             if e_in.insn_type = OP_DIVE then
 464                 x_to_divider.is_extended <= '1';
 465             end if;
 466             x_to_divider.dividend <= std_ulogic_vector(abs1);
 467             x_to_divider.divisor <= std_ulogic_vector(abs2);
 468         else
 469             -- 32-bit forms
 470             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 471             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 472             x_to_divider.is_extended <= '0';
 473             if e_in.insn_type = OP_DIVE then   -- extended forms
 474                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 475             else
 476                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 477             end if;
 478             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 479         end if;
 480
 481         ctrl_tmp <= ctrl;
 482         -- FIXME: run at 512MHz not core freq
 483         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 484         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 485
 486         irq_valid := '0';
 487         if ctrl.msr(MSR_EE) = '1' then
 488             if ctrl.dec(63) = '1' then
 489                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
 490                 report "IRQ valid: DEC";
 491                 irq_valid := '1';
 492             elsif ext_irq_in = '1' then
 493                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
 494                 report "IRQ valid: External";
 495                 irq_valid := '1';
 496             end if;
 497         end if;
 498
 499         v.terminate := '0';
 500         icache_inval <= '0';
 501         v.busy := '0';
 502         -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
 503         v.f.virt_mode := ctrl.msr(MSR_IR);
 504         v.f.priv_mode := not ctrl.msr(MSR_PR);
 505         v.f.big_endian := not ctrl.msr(MSR_LE);
 506         v.f.mode_32bit := not ctrl.msr(MSR_SF);
 507
 508         -- Next insn adder used in a couple of places
 509         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 510
 511         -- rotator control signals
 512         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 513         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 514         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 515         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 516
 517         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 518         ctrl_tmp.irq_state <= WRITE_SRR0;
 519         exception := '0';
 520         illegal := '0';
 521         exception_nextpc := '0';
 522         v.e.exc_write_enable := '0';
 523         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 524         v.e.exc_write_data := e_in.nia;
 525         if valid_in = '1' then
 526             v.last_nia := e_in.nia;
 527         end if;
 528
 529         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 530
 531         do_trace := valid_in and ctrl.msr(MSR_SE);
 532         if valid_in = '1' then
 533             v.prev_op := e_in.insn_type;
 534         end if;
 535
 536         if ctrl.irq_state = WRITE_SRR1 then
 537             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 538             v.e.exc_write_data := ctrl.srr1;
 539             v.e.exc_write_enable := '1';
 540             ctrl_tmp.msr(MSR_SF) <= '1';
 541             ctrl_tmp.msr(MSR_EE) <= '0';
 542             ctrl_tmp.msr(MSR_PR) <= '0';
 543             ctrl_tmp.msr(MSR_SE) <= '0';
 544             ctrl_tmp.msr(MSR_BE) <= '0';
 545             ctrl_tmp.msr(MSR_IR) <= '0';
 546             ctrl_tmp.msr(MSR_DR) <= '0';
 547             ctrl_tmp.msr(MSR_RI) <= '0';
 548             ctrl_tmp.msr(MSR_LE) <= '1';
 549             v.e.valid := '1';
 550             v.trace_next := '0';
 551             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 552
 553         elsif r.trace_next = '1' and valid_in = '1' then
 554             -- Generate a trace interrupt rather than executing the next instruction
 555             -- or taking any asynchronous interrupt
 556             v.f.redirect_nia := std_logic_vector(to_unsigned(16#d00#, 64));
 557             ctrl_tmp.srr1(63 - 33) <= '1';
 558             if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 559                 r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 560                 ctrl_tmp.srr1(63 - 35) <= '1';
 561             elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 562                 ctrl_tmp.srr1(63 - 36) <= '1';
 563             end if;
 564             exception := '1';
 565
 566         elsif irq_valid = '1' and valid_in = '1' then
 567             -- we need two cycles to write srr0 and 1
 568             -- will need more when we have to write HEIR
 569             -- Don't deliver the interrupt until we have a valid instruction
 570             -- coming in, so we have a valid NIA to put in SRR0.
 571             exception := '1';
 572
 573         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 574             instr_is_privileged(e_in.insn_type, e_in.insn) then
 575             -- generate a program interrupt
 576             exception := '1';
 577             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 578             -- set bit 45 to indicate privileged instruction type interrupt
 579             ctrl_tmp.srr1(63 - 45) <= '1';
 580             report "privileged instruction";
 581
 582         elsif valid_in = '1' and e_in.unit = ALU then
 583
 584             report "execute nia " & to_hstring(e_in.nia);
 585
 586             v.e.valid := '1';
 587             v.e.write_reg := e_in.write_reg;
 588             v.slow_op_insn := e_in.insn_type;
 589             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 590             v.slow_op_rc := e_in.rc;
 591             v.slow_op_oe := e_in.oe;
 592             v.slow_op_xerc := v.e.xerc;
 593
 594             case_0: case e_in.insn_type is
 595
 596             when OP_ILLEGAL =>
 597                 -- we need two cycles to write srr0 and 1
 598                 -- will need more when we have to write HEIR
 599                 illegal := '1';
 600             when OP_SC =>
 601                 -- check bit 1 of the instruction is 1 so we know this is sc;
 602                 -- 0 would mean scv, so generate an illegal instruction interrupt
 603                 -- we need two cycles to write srr0 and 1
 604                 if e_in.insn(1) = '1' then
 605                     exception := '1';
 606                     exception_nextpc := '1';
 607                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
 608                     report "sc";
 609                 else
 610                     illegal := '1';
 611                 end if;
 612             when OP_ATTN =>
 613                 -- check bits 1-10 of the instruction to make sure it's attn
 614                 -- if not then it is illegal
 615                 if e_in.insn(10 downto 1) = "0100000000" then
 616                     v.terminate := '1';
 617                     report "ATTN";
 618                 else
 619                     illegal := '1';
 620                 end if;
 621             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 622                 -- Do nothing
 623             when OP_ADD | OP_CMP | OP_TRAP =>
 624                 result := sum_with_carry(63 downto 0);
 625                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 626                 carry_64 := sum_with_carry(64);
 627                 if e_in.insn_type = OP_ADD then
 628                     if e_in.output_carry = '1' then
 629                         if e_in.input_carry /= OV then
 630                             set_carry(v.e, carry_32, carry_64);
 631                         else
 632                             v.e.xerc.ov := carry_64;
 633                             v.e.xerc.ov32 := carry_32;
 634                             v.e.write_xerc_enable := '1';
 635                         end if;
 636                     end if;
 637                     if e_in.oe = '1' then
 638                         set_ov(v.e,
 639                                calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 640                                calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 641                     end if;
 642                     result_en := '1';
 643                 else
 644                     -- trap, CMP and CMPL instructions
 645                     -- Note, we have done RB - RA, not RA - RB
 646                     if e_in.insn_type = OP_CMP then
 647                         l := insn_l(e_in.insn);
 648                     else
 649                         l := not e_in.is_32bit;
 650                     end if;
 651                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 652                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 653                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 654                         -- values are equal
 655                         trapval := "00100";
 656                     else
 657                         if l = '1' then
 658                             -- 64-bit comparison
 659                             msb_a := a_in(63);
 660                             msb_b := b_in(63);
 661                         else
 662                             -- 32-bit comparison
 663                             msb_a := a_in(31);
 664                             msb_b := b_in(31);
 665                         end if;
 666                         if msb_a /= msb_b then
 667                             -- Subtraction might overflow, but
 668                             -- comparison is clear from MSB difference.
 669                             -- for signed, 0 is greater; for unsigned, 1 is greater
 670                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 671                         else
 672                             -- Subtraction cannot overflow since MSBs are equal.
 673                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 674                             a_lt := (not l and carry_32) or (l and carry_64);
 675                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 676                         end if;
 677                     end if;
 678                     if e_in.insn_type = OP_CMP then
 679                         if e_in.is_signed = '1' then
 680                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 681                         else
 682                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 683                         end if;
 684                         bf := insn_bf(e_in.insn);
 685                         crnum := to_integer(unsigned(bf));
 686                         v.e.write_cr_enable := '1';
 687                         v.e.write_cr_mask := num_to_fxm(crnum);
 688                         for i in 0 to 7 loop
 689                             lo := i*4;
 690                             hi := lo + 3;
 691                             v.e.write_cr_data(hi downto lo) := newcrf;
 692                         end loop;
 693                     else
 694                         -- trap instructions (tw, twi, td, tdi)
 695                         v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 696                         -- set bit 46 to say trap occurred
 697                         ctrl_tmp.srr1(63 - 46) <= '1';
 698                         if or (trapval and insn_to(e_in.insn)) = '1' then
 699                             -- generate trap-type program interrupt
 700                             exception := '1';
 701                             report "trap";
 702                         end if;
 703                     end if;
 704                 end if;
 705             when OP_ADDG6S =>
 706                 result := (others => '0');
 707                 for i in 0 to 14 loop
 708                     lo := i * 4;
 709                     hi := (i + 1) * 4;
 710                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 711                         result(lo + 3 downto lo) := "0110";
 712                     end if;
 713                 end loop;
 714                 if sum_with_carry(64) = '0' then
 715                     result(63 downto 60) := "0110";
 716                 end if;
 717                 result_en := '1';
 718             when OP_CMPRB =>
 719                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 720                 bf := insn_bf(e_in.insn);
 721                 crnum := to_integer(unsigned(bf));
 722                 v.e.write_cr_enable := '1';
 723                 v.e.write_cr_mask := num_to_fxm(crnum);
 724                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 725                                      newcrf & newcrf & newcrf & newcrf;
 726             when OP_CMPEQB =>
 727                 newcrf := ppc_cmpeqb(a_in, b_in);
 728                 bf := insn_bf(e_in.insn);
 729                 crnum := to_integer(unsigned(bf));
 730                 v.e.write_cr_enable := '1';
 731                 v.e.write_cr_mask := num_to_fxm(crnum);
 732                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 733                                      newcrf & newcrf & newcrf & newcrf;
 734             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 735                     OP_BPERM | OP_BCD =>
 736                 result := logical_result;
 737                 result_en := '1';
 738             when OP_B =>
 739                 is_branch := '1';
 740                 taken_branch := '1';
 741                 abs_branch := insn_aa(e_in.insn);
 742                 if ctrl.msr(MSR_BE) = '1' then
 743                     do_trace := '1';
 744                 end if;
 745             when OP_BC =>
 746                 -- read_data1 is CTR
 747                 bo := insn_bo(e_in.insn);
 748                 bi := insn_bi(e_in.insn);
 749                 if bo(4-2) = '0' then
 750                     result := std_ulogic_vector(unsigned(a_in) - 1);
 751                     result_en := '1';
 752                     v.e.write_reg := fast_spr_num(SPR_CTR);
 753                 end if;
 754                 is_branch := '1';
 755                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 756                 abs_branch := insn_aa(e_in.insn);
 757                 if ctrl.msr(MSR_BE) = '1' then
 758                     do_trace := '1';
 759                 end if;
 760             when OP_BCREG =>
 761                 -- read_data1 is CTR
 762                 -- read_data2 is target register (CTR, LR or TAR)
 763                 bo := insn_bo(e_in.insn);
 764                 bi := insn_bi(e_in.insn);
 765                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 766                     result := std_ulogic_vector(unsigned(a_in) - 1);
 767                     result_en := '1';
 768                     v.e.write_reg := fast_spr_num(SPR_CTR);
 769                 end if;
 770                 is_branch := '1';
 771                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 772                 abs_branch := '1';
 773                 if ctrl.msr(MSR_BE) = '1' then
 774                     do_trace := '1';
 775                 end if;
 776
 777             when OP_RFID =>
 778                 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
 779                 v.f.priv_mode := not a_in(MSR_PR);
 780                 v.f.big_endian := not a_in(MSR_LE);
 781                 v.f.mode_32bit := not a_in(MSR_SF);
 782                 -- Can't use msr_copy here because the partial function MSR
 783                 -- bits should be left unchanged, not zeroed.
 784                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 785                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 786                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 787                 if a_in(MSR_PR) = '1' then
 788                     ctrl_tmp.msr(MSR_EE) <= '1';
 789                     ctrl_tmp.msr(MSR_IR) <= '1';
 790                     ctrl_tmp.msr(MSR_DR) <= '1';
 791                 end if;
 792                 -- mark this as a branch so CFAR gets updated
 793                 is_branch := '1';
 794                 taken_branch := '1';
 795                 abs_branch := '1';
 796                 do_trace := '0';
 797
 798             when OP_CNTZ =>
 799                 v.e.valid := '0';
 800                 v.cntz_in_progress := '1';
 801                 v.busy := '1';
 802             when OP_ISEL =>
 803                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 804                 if cr_in(31-crbit) = '1' then
 805                     result := a_in;
 806                 else
 807                     result := b_in;
 808                 end if;
 809                 result_en := '1';
 810             when OP_CROP =>
 811                 cr_op := insn_cr(e_in.insn);
 812                 report "CR OP " & to_hstring(cr_op);
 813                 if cr_op(0) = '0' then -- MCRF
 814                     bf := insn_bf(e_in.insn);
 815                     bfa := insn_bfa(e_in.insn);
 816                     v.e.write_cr_enable := '1';
 817                     crnum := to_integer(unsigned(bf));
 818                     scrnum := to_integer(unsigned(bfa));
 819                     v.e.write_cr_mask := num_to_fxm(crnum);
 820                     for i in 0 to 7 loop
 821                         lo := (7-i)*4;
 822                         hi := lo + 3;
 823                         if i = scrnum then
 824                             newcrf := cr_in(hi downto lo);
 825                         end if;
 826                     end loop;
 827                     for i in 0 to 7 loop
 828                         lo := i*4;
 829                         hi := lo + 3;
 830                         v.e.write_cr_data(hi downto lo) := newcrf;
 831                     end loop;
 832                 else
 833                     v.e.write_cr_enable := '1';
 834                     bt := insn_bt(e_in.insn);
 835                     ba := insn_ba(e_in.insn);
 836                     bb := insn_bb(e_in.insn);
 837                     btnum := 31 - to_integer(unsigned(bt));
 838                     banum := 31 - to_integer(unsigned(ba));
 839                     bbnum := 31 - to_integer(unsigned(bb));
 840                     -- Bits 5-8 of cr_op give the truth table of the requested
 841                     -- logical operation
 842                     cr_operands := cr_in(banum) & cr_in(bbnum);
 843                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 844                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 845                     for i in 0 to 31 loop
 846                         if i = btnum then
 847                             v.e.write_cr_data(i) := crresult;
 848                         else
 849                             v.e.write_cr_data(i) := cr_in(i);
 850                         end if;
 851                     end loop;
 852                 end if;
 853             when OP_MCRXRX =>
 854                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 855                 bf := insn_bf(e_in.insn);
 856                 crnum := to_integer(unsigned(bf));
 857                 v.e.write_cr_enable := '1';
 858                 v.e.write_cr_mask := num_to_fxm(crnum);
 859                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 860                                      newcrf & newcrf & newcrf & newcrf;
 861             when OP_DARN =>
 862                 if random_err = '0' then
 863                     case e_in.insn(17 downto 16) is
 864                         when "00" =>
 865                             result := x"00000000" & random_cond(31 downto 0);
 866                         when "10" =>
 867                             result := random_raw;
 868                         when others =>
 869                             result := random_cond;
 870                     end case;
 871                 else
 872                     result := (others => '1');
 873                 end if;
 874                 result_en := '1';
 875             when OP_MFMSR =>
 876                 result := ctrl.msr;
 877                 result_en := '1';
 878             when OP_MFSPR =>
 879                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 880                     "=" & to_hstring(a_in);
 881                 result_en := '1';
 882                 if is_fast_spr(e_in.read_reg1) then
 883                     result := a_in;
 884                     if decode_spr_num(e_in.insn) = SPR_XER then
 885                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 886                         result(63 downto 32) := (others => '0');
 887                         result(63-32) := v.e.xerc.so;
 888                         result(63-33) := v.e.xerc.ov;
 889                         result(63-34) := v.e.xerc.ca;
 890                         result(63-35 downto 63-43) := "000000000";
 891                         result(63-44) := v.e.xerc.ov32;
 892                         result(63-45) := v.e.xerc.ca32;
 893                     end if;
 894                 else
 895                     spr_val := c_in;
 896                     case decode_spr_num(e_in.insn) is
 897                     when SPR_TB =>
 898                         spr_val := ctrl.tb;
 899                     when SPR_TBU =>
 900                         spr_val(63 downto 32) := (others => '0');
 901                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 902                     when SPR_DEC =>
 903                         spr_val := ctrl.dec;
 904                     when SPR_CFAR =>
 905                         spr_val := ctrl.cfar;
 906                     when SPR_PVR =>
 907                         spr_val(63 downto 32) := (others => '0');
 908                         spr_val(31 downto 0) := PVR_MICROWATT;
 909                     when 724 =>     -- LOG_ADDR SPR
 910                         spr_val := log_wr_addr & r.log_addr_spr;
 911                     when 725 =>     -- LOG_DATA SPR
 912                         spr_val := log_rd_data;
 913                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 914                     when others =>
 915                         -- mfspr from unimplemented SPRs should be a nop in
 916                         -- supervisor mode and a program interrupt for user mode
 917                         if ctrl.msr(MSR_PR) = '1' then
 918                             illegal := '1';
 919                         end if;
 920                     end case;
 921                     result := spr_val;
 922                 end if;
 923             when OP_MFCR =>
 924                 if e_in.insn(20) = '0' then
 925                     -- mfcr
 926                     result := x"00000000" & cr_in;
 927                 else
 928                     -- mfocrf
 929                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 930                     result := (others => '0');
 931                     for i in 0 to 7 loop
 932                         lo := (7-i)*4;
 933                         hi := lo + 3;
 934                         if crnum = i then
 935                             result(hi downto lo) := cr_in(hi downto lo);
 936                         end if;
 937                     end loop;
 938                 end if;
 939                 result_en := '1';
 940             when OP_MTCRF =>
 941                 v.e.write_cr_enable := '1';
 942                 if e_in.insn(20) = '0' then
 943                     -- mtcrf
 944                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 945                 else
 946                     -- mtocrf: We require one hot priority encoding here
 947                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 948                     v.e.write_cr_mask := num_to_fxm(crnum);
 949                 end if;
 950                 v.e.write_cr_data := c_in(31 downto 0);
 951             when OP_MTMSRD =>
 952                 if e_in.insn(16) = '1' then
 953                     -- just update EE and RI
 954                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 955                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 956                 else
 957                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 958                     -- and 63 (LE) (IBM bit numbering)
 959                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 960                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 961                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 962                     if c_in(MSR_PR) = '1' then
 963                         ctrl_tmp.msr(MSR_EE) <= '1';
 964                         ctrl_tmp.msr(MSR_IR) <= '1';
 965                         ctrl_tmp.msr(MSR_DR) <= '1';
 966                     end if;
 967                 end if;
 968             when OP_MTSPR =>
 969                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 970                     "=" & to_hstring(c_in);
 971                 if is_fast_spr(e_in.write_reg) then
 972                     result := c_in;
 973                     result_en := '1';
 974                     if decode_spr_num(e_in.insn) = SPR_XER then
 975                         v.e.xerc.so := c_in(63-32);
 976                         v.e.xerc.ov := c_in(63-33);
 977                         v.e.xerc.ca := c_in(63-34);
 978                         v.e.xerc.ov32 := c_in(63-44);
 979                         v.e.xerc.ca32 := c_in(63-45);
 980                         v.e.write_xerc_enable := '1';
 981                     end if;
 982                 else
 983                     -- slow spr
 984                     case decode_spr_num(e_in.insn) is
 985                     when SPR_DEC =>
 986                         ctrl_tmp.dec <= c_in;
 987                     when 724 =>     -- LOG_ADDR SPR
 988                         v.log_addr_spr := c_in(31 downto 0);
 989                     when others =>
 990                         -- mtspr to unimplemented SPRs should be a nop in
 991                         -- supervisor mode and a program interrupt for user mode
 992                         if ctrl.msr(MSR_PR) = '1' then
 993                             illegal := '1';
 994                         end if;
 995                     end case;
 996                 end if;
 997             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
 998                 result := rotator_result;
 999                 if e_in.output_carry = '1' then
1000                     set_carry(v.e, rotator_carry, rotator_carry);
1001                 end if;
1002                 result_en := '1';
1003             when OP_SETB =>
1004                 bfa := insn_bfa(e_in.insn);
1005                 crbit := to_integer(unsigned(bfa)) * 4;
1006                 result := (others => '0');
1007                 if cr_in(31 - crbit) = '1' then
1008                     result := (others => '1');
1009                 elsif cr_in(30 - crbit) = '1' then
1010                     result(0) := '1';
1011                 end if;
1012
1013             when OP_ISYNC =>
1014                 v.f.redirect := '1';
1015                 v.f.redirect_nia := next_nia;
1016
1017             when OP_ICBI =>
1018                 icache_inval <= '1';
1019
1020             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1021                 v.e.valid := '0';
1022                 v.mul_in_progress := '1';
1023                 v.busy := '1';
1024                 x_to_multiply.valid <= '1';
1025
1026             when OP_DIV | OP_DIVE | OP_MOD =>
1027                 v.e.valid := '0';
1028                 v.div_in_progress := '1';
1029                 v.busy := '1';
1030                 x_to_divider.valid <= '1';
1031
1032             when others =>
1033                 v.terminate := '1';
1034                 report "illegal";
1035             end case;
1036
1037             v.e.rc := e_in.rc and valid_in;
1038
1039             -- Mispredicted branches cause a redirect
1040             if is_branch = '1' then
1041                 if taken_branch = '1' then
1042                     ctrl_tmp.cfar <= e_in.nia;
1043                 end if;
1044                 if e_in.br_pred = '0' then
1045                     if abs_branch = '1' then
1046                         v.f.redirect_nia := b_in;
1047                     else
1048                         v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
1049                     end if;
1050                 else
1051                     v.f.redirect_nia := next_nia;
1052                 end if;
1053                 if taken_branch /= e_in.br_pred then
1054                     v.f.redirect := '1';
1055                 end if;
1056             end if;
1057
1058             -- Update LR on the next cycle after a branch link
1059             -- If we're not writing back anything else, we can write back LR
1060             -- this cycle, otherwise we take an extra cycle.  We use the
1061             -- exc_write path since next_nia is written through that path
1062             -- in other places.
1063             if e_in.lr = '1' then
1064                 if result_en = '0' then
1065                     v.e.exc_write_enable := '1';
1066                     v.e.exc_write_data := next_nia;
1067                     v.e.exc_write_reg := fast_spr_num(SPR_LR);
1068                 else
1069                     v.lr_update := '1';
1070                     v.next_lr := next_nia;
1071                     v.e.valid := '0';
1072                     report "Delayed LR update to " & to_hstring(next_nia);
1073                     v.busy := '1';
1074                 end if;
1075             end if;
1076
1077         elsif valid_in = '1' then
1078             -- instruction for other units, i.e. LDST
1079             if e_in.unit = LDST then
1080                 lv.valid := '1';
1081             elsif e_in.unit = NONE then
1082                 illegal := '1';
1083             end if;
1084
1085         elsif r.f.redirect = '1' then
1086             v.e.valid := '1';
1087         elsif r.lr_update = '1' then
1088             v.e.exc_write_enable := '1';
1089             v.e.exc_write_data := r.next_lr;
1090             v.e.exc_write_reg := fast_spr_num(SPR_LR);
1091             v.e.valid := '1';
1092         elsif r.cntz_in_progress = '1' then
1093             -- cnt[lt]z always takes two cycles
1094             result := countzero_result;
1095             result_en := '1';
1096             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1097             v.e.rc := r.slow_op_rc;
1098             v.e.xerc := r.slow_op_xerc;
1099             v.e.valid := '1';
1100         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1101             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1102                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1103                 if r.mul_in_progress = '1' then
1104                     overflow := '0';
1105                     case r.slow_op_insn is
1106                         when OP_MUL_H32 =>
1107                             result := multiply_to_x.result(63 downto 32) &
1108                                       multiply_to_x.result(63 downto 32);
1109                         when OP_MUL_H64 =>
1110                             result := multiply_to_x.result(127 downto 64);
1111                         when others =>
1112                             -- i.e. OP_MUL_L64
1113                             result := multiply_to_x.result(63 downto 0);
1114                     end case;
1115                 else
1116                     result := divider_to_x.write_reg_data;
1117                     overflow := divider_to_x.overflow;
1118                 end if;
1119                 if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
1120                     -- have to wait until next cycle for overflow indication
1121                     v.mul_finish := '1';
1122                     v.busy := '1';
1123                 else
1124                     result_en := '1';
1125                     v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1126                     v.e.rc := r.slow_op_rc;
1127                     v.e.xerc := r.slow_op_xerc;
1128                     v.e.write_xerc_enable := r.slow_op_oe;
1129                     -- We must test oe because the RC update code in writeback
1130                     -- will use the xerc value to set CR0:SO so we must not clobber
1131                     -- xerc if OE wasn't set.
1132                     if r.slow_op_oe = '1' then
1133                         v.e.xerc.ov := overflow;
1134                         v.e.xerc.ov32 := overflow;
1135                         v.e.xerc.so := r.slow_op_xerc.so or overflow;
1136                     end if;
1137                     v.e.valid := '1';
1138                 end if;
1139             else
1140                 v.busy := '1';
1141                 v.mul_in_progress := r.mul_in_progress;
1142                 v.div_in_progress := r.div_in_progress;
1143             end if;
1144         elsif r.mul_finish = '1' then
1145             result := r.e.write_data;
1146             result_en := '1';
1147             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1148             v.e.rc := r.slow_op_rc;
1149             v.e.xerc := r.slow_op_xerc;
1150             v.e.write_xerc_enable := r.slow_op_oe;
1151             v.e.xerc.ov := multiply_to_x.overflow;
1152             v.e.xerc.ov32 := multiply_to_x.overflow;
1153             v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
1154             v.e.valid := '1';
1155         end if;
1156
1157         if illegal = '1' then
1158             exception := '1';
1159             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1160             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1161             -- set bit 44 to indicate we have an illegal
1162             ctrl_tmp.srr1(63 - 44) <= '1';
1163             report "illegal";
1164         end if;
1165         if exception = '1' then
1166             v.e.exc_write_enable := '1';
1167             if exception_nextpc = '1' then
1168                 v.e.exc_write_data := next_nia;
1169             end if;
1170         end if;
1171
1172         if do_trace = '1' then
1173             v.trace_next := '1';
1174         end if;
1175
1176         v.e.write_data := result;
1177         v.e.write_enable := result_en and not exception;
1178
1179         -- generate DSI or DSegI for load/store exceptions
1180         -- or ISI or ISegI for instruction fetch exceptions
1181         if l_in.exception = '1' then
1182             if l_in.alignment = '1' then
1183                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#600#, 64));
1184             elsif l_in.instr_fault = '0' then
1185                 if l_in.segment_fault = '0' then
1186                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1187                 else
1188                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1189                 end if;
1190             else
1191                 if l_in.segment_fault = '0' then
1192                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1193                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1194                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1195                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1196                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1197                 else
1198                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1199                 end if;
1200             end if;
1201             v.e.exc_write_enable := '1';
1202             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1203             v.e.exc_write_data := r.last_nia;
1204             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1205         end if;
1206
1207         if exception = '1' or l_in.exception = '1' then
1208             ctrl_tmp.irq_state <= WRITE_SRR1;
1209             v.f.redirect := '1';
1210             v.f.virt_mode := '0';
1211             v.f.priv_mode := '1';
1212             -- XXX need an interrupt LE bit here, e.g. from LPCR
1213             v.f.big_endian := '0';
1214             v.f.mode_32bit := '0';
1215         end if;
1216
1217         if v.f.redirect = '1' then
1218             v.busy := '1';
1219             v.e.valid := '0';
1220         end if;
1221
1222         -- Outputs to loadstore1 (async)
1223         lv.op := e_in.insn_type;
1224         lv.nia := e_in.nia;
1225         lv.addr1 := a_in;
1226         lv.addr2 := b_in;
1227         lv.data := c_in;
1228         lv.write_reg := gspr_to_gpr(e_in.write_reg);
1229         lv.length := e_in.data_len;
1230         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1231         lv.sign_extend := e_in.sign_extend;
1232         lv.update := e_in.update;
1233         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1234         lv.xerc := v.e.xerc;
1235         lv.reserve := e_in.reserve;
1236         lv.rc := e_in.rc;
1237         lv.insn := e_in.insn;
1238         -- decode l*cix and st*cix instructions here
1239         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1240             e_in.insn(5 downto 1) = "10101" then
1241             lv.ci := '1';
1242         end if;
1243         lv.virt_mode := ctrl.msr(MSR_DR);
1244         lv.priv_mode := not ctrl.msr(MSR_PR);
1245         lv.mode_32bit := not ctrl.msr(MSR_SF);
1246
1247         -- Update registers
1248         rin <= v;
1249
1250         -- update outputs
1251         f_out <= r.f;
1252         l_out <= lv;
1253         e_out <= r.e;
1254         flush_out <= f_out.redirect;
1255
1256         exception_log <= exception;
1257         irq_valid_log <= irq_valid;
1258     end process;
1259
1260     e1_log: if LOG_LENGTH > 0 generate
1261         signal log_data : std_ulogic_vector(14 downto 0);
1262     begin
1263         ex1_log : process(clk)
1264         begin
1265             if rising_edge(clk) then
1266                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1267                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1268                             exception_log &
1269                             irq_valid_log &
1270                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1271                             "000" &
1272                             r.e.write_enable &
1273                             r.e.valid &
1274                             f_out.redirect &
1275                             r.busy &
1276                             flush_out;
1277             end if;
1278         end process;
1279         log_out <= log_data;
1280     end generate;
1281 end architecture behaviour;