execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true
  16         );
  17     port (
  18         clk   : in std_ulogic;
  19         rst   : in std_ulogic;
  20
  21         -- asynchronous
  22         flush_out : out std_ulogic;
  23         busy_out : out std_ulogic;
  24
  25         e_in  : in Decode2ToExecute1Type;
  26         l_in  : in Loadstore1ToExecute1Type;
  27
  28         ext_irq_in : std_ulogic;
  29
  30         -- asynchronous
  31         l_out : out Execute1ToLoadstore1Type;
  32         f_out : out Execute1ToFetch1Type;
  33
  34         e_out : out Execute1ToWritebackType;
  35
  36         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  37
  38         icache_inval : out std_ulogic;
  39         terminate_out : out std_ulogic;
  40
  41         log_out : out std_ulogic_vector(14 downto 0);
  42         log_rd_addr : out std_ulogic_vector(31 downto 0);
  43         log_rd_data : in std_ulogic_vector(63 downto 0);
  44         log_wr_addr : in std_ulogic_vector(31 downto 0)
  45         );
  46 end entity execute1;
  47
  48 architecture behaviour of execute1 is
  49     type reg_type is record
  50         e : Execute1ToWritebackType;
  51         busy: std_ulogic;
  52         terminate: std_ulogic;
  53         lr_update : std_ulogic;
  54         next_lr : std_ulogic_vector(63 downto 0);
  55         mul_in_progress : std_ulogic;
  56         div_in_progress : std_ulogic;
  57         cntz_in_progress : std_ulogic;
  58         slow_op_insn : insn_type_t;
  59         slow_op_dest : gpr_index_t;
  60         slow_op_rc : std_ulogic;
  61         slow_op_oe : std_ulogic;
  62         slow_op_xerc : xer_common_t;
  63         last_nia : std_ulogic_vector(63 downto 0);
  64         log_addr_spr : std_ulogic_vector(31 downto 0);
  65     end record;
  66     constant reg_type_init : reg_type :=
  67         (e => Execute1ToWritebackInit, busy => '0', lr_update => '0', terminate => '0',
  68          mul_in_progress => '0', div_in_progress => '0', cntz_in_progress => '0',
  69          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  70          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
  71
  72     signal r, rin : reg_type;
  73
  74     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  75
  76     signal valid_in : std_ulogic;
  77     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  78     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  79     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  80     signal rot_sign_ext: std_ulogic;
  81     signal rotator_result: std_ulogic_vector(63 downto 0);
  82     signal rotator_carry: std_ulogic;
  83     signal logical_result: std_ulogic_vector(63 downto 0);
  84     signal countzero_result: std_ulogic_vector(63 downto 0);
  85     signal popcnt_result: std_ulogic_vector(63 downto 0);
  86     signal parity_result: std_ulogic_vector(63 downto 0);
  87
  88     -- multiply signals
  89     signal x_to_multiply: Execute1ToMultiplyType;
  90     signal multiply_to_x: MultiplyToExecute1Type;
  91
  92     -- divider signals
  93     signal x_to_divider: Execute1ToDividerType;
  94     signal divider_to_x: DividerToExecute1Type;
  95
  96     -- signals for logging
  97     signal exception_log : std_ulogic;
  98     signal irq_valid_log : std_ulogic;
  99     signal log_data : std_ulogic_vector(14 downto 0);
 100
 101     type privilege_level is (USER, SUPER);
 102     type op_privilege_array is array(insn_type_t) of privilege_level;
 103     constant op_privilege: op_privilege_array := (
 104         OP_ATTN => SUPER,
 105         OP_MFMSR => SUPER,
 106         OP_MTMSRD => SUPER,
 107         OP_RFID => SUPER,
 108         OP_TLBIE => SUPER,
 109         others => USER
 110         );
 111
 112     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 113         return boolean is
 114     begin
 115         if op_privilege(op) = SUPER then
 116             return true;
 117         elsif op = OP_MFSPR or op = OP_MTSPR then
 118             return insn(20) = '1';
 119         else
 120             return false;
 121         end if;
 122     end;
 123
 124     procedure set_carry(e: inout Execute1ToWritebackType;
 125                         carry32 : in std_ulogic;
 126                         carry : in std_ulogic) is
 127     begin
 128         e.xerc.ca32 := carry32;
 129         e.xerc.ca := carry;
 130         e.write_xerc_enable := '1';
 131     end;
 132
 133     procedure set_ov(e: inout Execute1ToWritebackType;
 134                      ov   : in std_ulogic;
 135                      ov32 : in std_ulogic) is
 136     begin
 137         e.xerc.ov32 := ov32;
 138         e.xerc.ov := ov;
 139         if ov = '1' then
 140             e.xerc.so := '1';
 141         end if;
 142         e.write_xerc_enable := '1';
 143     end;
 144
 145     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 146                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 147     begin
 148         return (ca xor msb_r) and not (msb_a xor msb_b);
 149     end;
 150
 151     function decode_input_carry(ic : carry_in_t;
 152                                 xerc : xer_common_t) return std_ulogic is
 153     begin
 154         case ic is
 155         when ZERO =>
 156             return '0';
 157         when CA =>
 158             return xerc.ca;
 159         when ONE =>
 160             return '1';
 161         end case;
 162     end;
 163
 164     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 165         return std_ulogic_vector is
 166         variable msr_out: std_ulogic_vector(63 downto 0);
 167     begin
 168         -- ISA says this:
 169         --  Defined MSR bits are classified as either full func-
 170         --  tion or partial function. Full function MSR bits are
 171         --  saved in SRR1 or HSRR1 when an interrupt other
 172         --  than a System Call Vectored interrupt occurs and
 173         --  restored by rfscv, rfid, or hrfid, while partial func-
 174         --  tion MSR bits are not saved or restored.
 175         --  Full function MSR bits lie in the range 0:32, 37:41, and
 176         --  48:63, and partial function MSR bits lie in the range
 177         --  33:36 and 42:47. (Note this is IBM bit numbering).
 178         msr_out := (others => '0');
 179         msr_out(63 downto 31) := msr(63 downto 31);
 180         msr_out(26 downto 22) := msr(26 downto 22);
 181         msr_out(15 downto 0)  := msr(15 downto 0);
 182         return msr_out;
 183     end;
 184
 185 begin
 186
 187     rotator_0: entity work.rotator
 188         port map (
 189             rs => c_in,
 190             ra => a_in,
 191             shift => b_in(6 downto 0),
 192             insn => e_in.insn,
 193             is_32bit => e_in.is_32bit,
 194             right_shift => right_shift,
 195             arith => e_in.is_signed,
 196             clear_left => rot_clear_left,
 197             clear_right => rot_clear_right,
 198             sign_ext_rs => rot_sign_ext,
 199             result => rotator_result,
 200             carry_out => rotator_carry
 201             );
 202
 203     logical_0: entity work.logical
 204         port map (
 205             rs => c_in,
 206             rb => b_in,
 207             op => e_in.insn_type,
 208             invert_in => e_in.invert_a,
 209             invert_out => e_in.invert_out,
 210             result => logical_result,
 211             datalen => e_in.data_len,
 212             popcnt => popcnt_result,
 213             parity => parity_result
 214             );
 215
 216     countzero_0: entity work.zero_counter
 217         port map (
 218             clk => clk,
 219             rs => c_in,
 220             count_right => e_in.insn(10),
 221             is_32bit => e_in.is_32bit,
 222             result => countzero_result
 223             );
 224
 225     multiply_0: entity work.multiply
 226         port map (
 227             clk => clk,
 228             m_in => x_to_multiply,
 229             m_out => multiply_to_x
 230             );
 231
 232     divider_0: entity work.divider
 233         port map (
 234             clk => clk,
 235             rst => rst,
 236             d_in => x_to_divider,
 237             d_out => divider_to_x
 238             );
 239
 240     dbg_msr_out <= ctrl.msr;
 241     log_rd_addr <= r.log_addr_spr;
 242
 243     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 244     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 245     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 246
 247     busy_out <= l_in.busy or r.busy;
 248     valid_in <= e_in.valid and not busy_out;
 249
 250     terminate_out <= r.terminate;
 251
 252     execute1_0: process(clk)
 253     begin
 254         if rising_edge(clk) then
 255             if rst = '1' then
 256                 r <= reg_type_init;
 257                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 258                 ctrl.irq_state <= WRITE_SRR0;
 259             else
 260                 r <= rin;
 261                 ctrl <= ctrl_tmp;
 262                 assert not (r.lr_update = '1' and valid_in = '1')
 263                     report "LR update collision with valid in EX1"
 264                     severity failure;
 265                 if r.lr_update = '1' then
 266                     report "LR update to " & to_hstring(r.next_lr);
 267                 end if;
 268             end if;
 269         end if;
 270     end process;
 271
 272     execute1_1: process(all)
 273         variable v : reg_type;
 274         variable a_inv : std_ulogic_vector(63 downto 0);
 275         variable result : std_ulogic_vector(63 downto 0);
 276         variable newcrf : std_ulogic_vector(3 downto 0);
 277         variable result_with_carry : std_ulogic_vector(64 downto 0);
 278         variable result_en : std_ulogic;
 279         variable crnum : crnum_t;
 280         variable crbit : integer range 0 to 31;
 281         variable scrnum : crnum_t;
 282         variable lo, hi : integer;
 283         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 284         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 285         variable bo, bi : std_ulogic_vector(4 downto 0);
 286         variable bf, bfa : std_ulogic_vector(2 downto 0);
 287         variable cr_op : std_ulogic_vector(9 downto 0);
 288         variable cr_operands : std_ulogic_vector(1 downto 0);
 289         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 290         variable btnum, banum, bbnum : integer range 0 to 31;
 291         variable crresult : std_ulogic;
 292         variable l : std_ulogic;
 293         variable next_nia : std_ulogic_vector(63 downto 0);
 294         variable carry_32, carry_64 : std_ulogic;
 295         variable sign1, sign2 : std_ulogic;
 296         variable abs1, abs2 : signed(63 downto 0);
 297         variable overflow : std_ulogic;
 298         variable negative : std_ulogic;
 299         variable zerohi, zerolo : std_ulogic;
 300         variable msb_a, msb_b : std_ulogic;
 301         variable a_lt : std_ulogic;
 302         variable lv : Execute1ToLoadstore1Type;
 303         variable irq_valid : std_ulogic;
 304         variable exception : std_ulogic;
 305         variable exception_nextpc : std_ulogic;
 306         variable trapval : std_ulogic_vector(4 downto 0);
 307         variable illegal : std_ulogic;
 308     begin
 309         result := (others => '0');
 310         result_with_carry := (others => '0');
 311         result_en := '0';
 312         newcrf := (others => '0');
 313
 314         v := r;
 315         v.e := Execute1ToWritebackInit;
 316         lv := Execute1ToLoadstore1Init;
 317
 318         -- XER forwarding. To avoid having to track XER hazards, we
 319         -- use the previously latched value.
 320         --
 321         -- If the XER was modified by a multiply or a divide, those are
 322         -- single issue, we'll get the up to date value from decode2 from
 323         -- the register file.
 324         --
 325         -- If it was modified by an instruction older than the previous
 326         -- one in EX1, it will have also hit writeback and will be up
 327         -- to date in decode2.
 328         --
 329         -- That leaves us with the case where it was updated by the previous
 330         -- instruction in EX1. In that case, we can forward it back here.
 331         --
 332         -- This will break if we allow pipelining of multiply and divide,
 333         -- but ideally, those should go via EX1 anyway and run as a state
 334         -- machine from here.
 335         --
 336         -- One additional hazard to beware of is an XER:SO modifying instruction
 337         -- in EX1 followed immediately by a store conditional. Due to our
 338         -- writeback latency, the store will go down the LSU with the previous
 339         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 340         --
 341         -- We will need to handle that if we ever make stcx. not single issue
 342         --
 343         -- We always pass a valid XER value downto writeback even when
 344         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 345         -- to work for RC instructions.
 346         --
 347         if r.e.write_xerc_enable = '1' then
 348             v.e.xerc := r.e.xerc;
 349         else
 350             v.e.xerc := e_in.xerc;
 351         end if;
 352
 353         v.lr_update := '0';
 354         v.mul_in_progress := '0';
 355         v.div_in_progress := '0';
 356         v.cntz_in_progress := '0';
 357
 358         -- signals to multiply and divide units
 359         sign1 := '0';
 360         sign2 := '0';
 361         if e_in.is_signed = '1' then
 362             if e_in.is_32bit = '1' then
 363                 sign1 := a_in(31);
 364                 sign2 := b_in(31);
 365             else
 366                 sign1 := a_in(63);
 367                 sign2 := b_in(63);
 368             end if;
 369         end if;
 370         -- take absolute values
 371         if sign1 = '0' then
 372             abs1 := signed(a_in);
 373         else
 374             abs1 := - signed(a_in);
 375         end if;
 376         if sign2 = '0' then
 377             abs2 := signed(b_in);
 378         else
 379             abs2 := - signed(b_in);
 380         end if;
 381
 382         x_to_multiply <= Execute1ToMultiplyInit;
 383         x_to_multiply.is_32bit <= e_in.is_32bit;
 384
 385         x_to_divider <= Execute1ToDividerInit;
 386         x_to_divider.is_signed <= e_in.is_signed;
 387         x_to_divider.is_32bit <= e_in.is_32bit;
 388         if e_in.insn_type = OP_MOD then
 389             x_to_divider.is_modulus <= '1';
 390         end if;
 391
 392         x_to_multiply.neg_result <= sign1 xor sign2;
 393         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 394         if e_in.is_32bit = '0' then
 395             -- 64-bit forms
 396             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 397             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 398             if e_in.insn_type = OP_DIVE then
 399                 x_to_divider.is_extended <= '1';
 400             end if;
 401             x_to_divider.dividend <= std_ulogic_vector(abs1);
 402             x_to_divider.divisor <= std_ulogic_vector(abs2);
 403         else
 404             -- 32-bit forms
 405             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 406             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 407             x_to_divider.is_extended <= '0';
 408             if e_in.insn_type = OP_DIVE then   -- extended forms
 409                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 410             else
 411                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 412             end if;
 413             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 414         end if;
 415
 416         ctrl_tmp <= ctrl;
 417         -- FIXME: run at 512MHz not core freq
 418         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 419         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 420
 421         irq_valid := '0';
 422         if ctrl.msr(MSR_EE) = '1' then
 423             if ctrl.dec(63) = '1' then
 424                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#900#, 64));
 425                 report "IRQ valid: DEC";
 426                 irq_valid := '1';
 427             elsif ext_irq_in = '1' then
 428                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#500#, 64));
 429                 report "IRQ valid: External";
 430                 irq_valid := '1';
 431             end if;
 432         end if;
 433
 434         v.terminate := '0';
 435         icache_inval <= '0';
 436         v.busy := '0';
 437         f_out <= Execute1ToFetch1TypeInit;
 438         -- send MSR[IR] and ~MSR[PR] up to fetch1
 439         f_out.virt_mode <= ctrl.msr(MSR_IR);
 440         f_out.priv_mode <= not ctrl.msr(MSR_PR);
 441
 442         -- Next insn adder used in a couple of places
 443         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 444
 445         -- rotator control signals
 446         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 447         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 448         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 449         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 450
 451         ctrl_tmp.irq_state <= WRITE_SRR0;
 452         exception := '0';
 453         illegal := '0';
 454         exception_nextpc := '0';
 455         v.e.exc_write_enable := '0';
 456         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 457         v.e.exc_write_data := e_in.nia;
 458         if valid_in = '1' then
 459             v.last_nia := e_in.nia;
 460         end if;
 461
 462         if ctrl.irq_state = WRITE_SRR1 then
 463             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 464             v.e.exc_write_data := ctrl.srr1;
 465             v.e.exc_write_enable := '1';
 466             ctrl_tmp.msr(MSR_SF) <= '1';
 467             ctrl_tmp.msr(MSR_EE) <= '0';
 468             ctrl_tmp.msr(MSR_PR) <= '0';
 469             ctrl_tmp.msr(MSR_IR) <= '0';
 470             ctrl_tmp.msr(MSR_DR) <= '0';
 471             ctrl_tmp.msr(MSR_RI) <= '0';
 472             ctrl_tmp.msr(MSR_LE) <= '1';
 473             f_out.redirect <= '1';
 474             f_out.virt_mode <= '0';
 475             f_out.priv_mode <= '1';
 476             f_out.redirect_nia <= ctrl.irq_nia;
 477             v.e.valid := '1';
 478             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 479
 480         elsif irq_valid = '1' and valid_in = '1' then
 481             -- we need two cycles to write srr0 and 1
 482             -- will need more when we have to write HEIR
 483             -- Don't deliver the interrupt until we have a valid instruction
 484             -- coming in, so we have a valid NIA to put in SRR0.
 485             exception := '1';
 486             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 487
 488         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 489             instr_is_privileged(e_in.insn_type, e_in.insn) then
 490             -- generate a program interrupt
 491             exception := '1';
 492             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 493             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 494             -- set bit 45 to indicate privileged instruction type interrupt
 495             ctrl_tmp.srr1(63 - 45) <= '1';
 496             report "privileged instruction";
 497
 498         elsif valid_in = '1' and e_in.unit = ALU then
 499
 500             report "execute nia " & to_hstring(e_in.nia);
 501
 502             v.e.valid := '1';
 503             v.e.write_reg := e_in.write_reg;
 504             v.slow_op_insn := e_in.insn_type;
 505             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 506             v.slow_op_rc := e_in.rc;
 507             v.slow_op_oe := e_in.oe;
 508             v.slow_op_xerc := v.e.xerc;
 509
 510             case_0: case e_in.insn_type is
 511
 512             when OP_ILLEGAL =>
 513                 -- we need two cycles to write srr0 and 1
 514                 -- will need more when we have to write HEIR
 515                 illegal := '1';
 516             when OP_SC =>
 517                 -- check bit 1 of the instruction is 1 so we know this is sc;
 518                 -- 0 would mean scv, so generate an illegal instruction interrupt
 519                 -- we need two cycles to write srr0 and 1
 520                 if e_in.insn(1) = '1' then
 521                     exception := '1';
 522                     exception_nextpc := '1';
 523                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
 524                     ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 525                     report "sc";
 526                 else
 527                     illegal := '1';
 528                 end if;
 529             when OP_ATTN =>
 530                 -- check bits 1-10 of the instruction to make sure it's attn
 531                 -- if not then it is illegal
 532                 if e_in.insn(10 downto 1) = "0100000000" then
 533                     v.terminate := '1';
 534                     report "ATTN";
 535                 else
 536                     illegal := '1';
 537                 end if;
 538             when OP_NOP =>
 539                 -- Do nothing
 540             when OP_ADD | OP_CMP | OP_TRAP =>
 541                 if e_in.invert_a = '0' then
 542                     a_inv := a_in;
 543                 else
 544                     a_inv := not a_in;
 545                 end if;
 546                 result_with_carry := ppc_adde(a_inv, b_in,
 547                                               decode_input_carry(e_in.input_carry, v.e.xerc));
 548                 result := result_with_carry(63 downto 0);
 549                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 550                 carry_64 := result_with_carry(64);
 551                 if e_in.insn_type = OP_ADD then
 552                     if e_in.output_carry = '1' then
 553                         set_carry(v.e, carry_32, carry_64);
 554                     end if;
 555                     if e_in.oe = '1' then
 556                         set_ov(v.e,
 557                                calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
 558                                calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
 559                     end if;
 560                     result_en := '1';
 561                 else
 562                     -- trap, CMP and CMPL instructions
 563                     -- Note, we have done RB - RA, not RA - RB
 564                     if e_in.insn_type = OP_CMP then
 565                         l := insn_l(e_in.insn);
 566                     else
 567                         l := not e_in.is_32bit;
 568                     end if;
 569                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 570                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 571                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 572                         -- values are equal
 573                         trapval := "00100";
 574                     else
 575                         if l = '1' then
 576                             -- 64-bit comparison
 577                             msb_a := a_in(63);
 578                             msb_b := b_in(63);
 579                         else
 580                             -- 32-bit comparison
 581                             msb_a := a_in(31);
 582                             msb_b := b_in(31);
 583                         end if;
 584                         if msb_a /= msb_b then
 585                             -- Subtraction might overflow, but
 586                             -- comparison is clear from MSB difference.
 587                             -- for signed, 0 is greater; for unsigned, 1 is greater
 588                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 589                         else
 590                             -- Subtraction cannot overflow since MSBs are equal.
 591                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 592                             a_lt := (not l and carry_32) or (l and carry_64);
 593                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 594                         end if;
 595                     end if;
 596                     if e_in.insn_type = OP_CMP then
 597                         if e_in.is_signed = '1' then
 598                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 599                         else
 600                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 601                         end if;
 602                         bf := insn_bf(e_in.insn);
 603                         crnum := to_integer(unsigned(bf));
 604                         v.e.write_cr_enable := '1';
 605                         v.e.write_cr_mask := num_to_fxm(crnum);
 606                         for i in 0 to 7 loop
 607                             lo := i*4;
 608                             hi := lo + 3;
 609                             v.e.write_cr_data(hi downto lo) := newcrf;
 610                         end loop;
 611                     else
 612                         -- trap instructions (tw, twi, td, tdi)
 613                         if or (trapval and insn_to(e_in.insn)) = '1' then
 614                             -- generate trap-type program interrupt
 615                             exception := '1';
 616                             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 617                             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 618                             -- set bit 46 to say trap occurred
 619                             ctrl_tmp.srr1(63 - 46) <= '1';
 620                             report "trap";
 621                         end if;
 622                     end if;
 623                 end if;
 624             when OP_AND | OP_OR | OP_XOR =>
 625                 result := logical_result;
 626                 result_en := '1';
 627             when OP_B =>
 628                 f_out.redirect <= '1';
 629                 if (insn_aa(e_in.insn)) then
 630                     f_out.redirect_nia <= b_in;
 631                 else
 632                     f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 633                 end if;
 634             when OP_BC =>
 635                 -- read_data1 is CTR
 636                 bo := insn_bo(e_in.insn);
 637                 bi := insn_bi(e_in.insn);
 638                 if bo(4-2) = '0' then
 639                     result := std_ulogic_vector(unsigned(a_in) - 1);
 640                     result_en := '1';
 641                     v.e.write_reg := fast_spr_num(SPR_CTR);
 642                 end if;
 643                 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
 644                     f_out.redirect <= '1';
 645                     if (insn_aa(e_in.insn)) then
 646                         f_out.redirect_nia <= b_in;
 647                     else
 648                         f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 649                     end if;
 650                 end if;
 651             when OP_BCREG =>
 652                 -- read_data1 is CTR
 653                 -- read_data2 is target register (CTR, LR or TAR)
 654                 bo := insn_bo(e_in.insn);
 655                 bi := insn_bi(e_in.insn);
 656                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 657                     result := std_ulogic_vector(unsigned(a_in) - 1);
 658                     result_en := '1';
 659                     v.e.write_reg := fast_spr_num(SPR_CTR);
 660                 end if;
 661                 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
 662                     f_out.redirect <= '1';
 663                     f_out.redirect_nia <= b_in(63 downto 2) & "00";
 664                 end if;
 665
 666             when OP_RFID =>
 667                 f_out.redirect <= '1';
 668                 f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
 669                 f_out.priv_mode <= not b_in(MSR_PR);
 670                 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
 671                 -- Can't use msr_copy here because the partial function MSR
 672                 -- bits should be left unchanged, not zeroed.
 673                 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
 674                 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
 675                 ctrl_tmp.msr(15 downto 0)  <= b_in(15 downto 0);
 676                 if b_in(MSR_PR) = '1' then
 677                     ctrl_tmp.msr(MSR_EE) <= '1';
 678                     ctrl_tmp.msr(MSR_IR) <= '1';
 679                     ctrl_tmp.msr(MSR_DR) <= '1';
 680                 end if;
 681
 682             when OP_CMPB =>
 683                 result := ppc_cmpb(c_in, b_in);
 684                 result_en := '1';
 685             when OP_CNTZ =>
 686                 v.e.valid := '0';
 687                 v.cntz_in_progress := '1';
 688                 v.busy := '1';
 689             when OP_EXTS =>
 690                 -- note data_len is a 1-hot encoding
 691                 negative := (e_in.data_len(0) and c_in(7)) or
 692                             (e_in.data_len(1) and c_in(15)) or
 693                             (e_in.data_len(2) and c_in(31));
 694                 result := (others => negative);
 695                 if e_in.data_len(2) = '1' then
 696                     result(31 downto 16) := c_in(31 downto 16);
 697                 end if;
 698                 if e_in.data_len(2) = '1' or e_in.data_len(1) = '1' then
 699                     result(15 downto 8) := c_in(15 downto 8);
 700                 end if;
 701                 result(7 downto 0) := c_in(7 downto 0);
 702                 result_en := '1';
 703             when OP_ISEL =>
 704                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 705                 if e_in.cr(31-crbit) = '1' then
 706                     result := a_in;
 707                 else
 708                     result := b_in;
 709                 end if;
 710                 result_en := '1';
 711             when OP_CROP =>
 712                 cr_op := insn_cr(e_in.insn);
 713                 report "CR OP " & to_hstring(cr_op);
 714                 if cr_op(0) = '0' then -- MCRF
 715                     bf := insn_bf(e_in.insn);
 716                     bfa := insn_bfa(e_in.insn);
 717                     v.e.write_cr_enable := '1';
 718                     crnum := to_integer(unsigned(bf));
 719                     scrnum := to_integer(unsigned(bfa));
 720                     v.e.write_cr_mask := num_to_fxm(crnum);
 721                     for i in 0 to 7 loop
 722                         lo := (7-i)*4;
 723                         hi := lo + 3;
 724                         if i = scrnum then
 725                             newcrf := e_in.cr(hi downto lo);
 726                         end if;
 727                     end loop;
 728                     for i in 0 to 7 loop
 729                         lo := i*4;
 730                         hi := lo + 3;
 731                         v.e.write_cr_data(hi downto lo) := newcrf;
 732                     end loop;
 733                 else
 734                     v.e.write_cr_enable := '1';
 735                     bt := insn_bt(e_in.insn);
 736                     ba := insn_ba(e_in.insn);
 737                     bb := insn_bb(e_in.insn);
 738                     btnum := 31 - to_integer(unsigned(bt));
 739                     banum := 31 - to_integer(unsigned(ba));
 740                     bbnum := 31 - to_integer(unsigned(bb));
 741                     -- Bits 5-8 of cr_op give the truth table of the requested
 742                     -- logical operation
 743                     cr_operands := e_in.cr(banum) & e_in.cr(bbnum);
 744                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 745                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 746                     for i in 0 to 31 loop
 747                         if i = btnum then
 748                             v.e.write_cr_data(i) := crresult;
 749                         else
 750                             v.e.write_cr_data(i) := e_in.cr(i);
 751                         end if;
 752                     end loop;
 753                 end if;
 754             when OP_MFMSR =>
 755                 result := ctrl.msr;
 756                 result_en := '1';
 757             when OP_MFSPR =>
 758                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 759                     "=" & to_hstring(a_in);
 760                 result_en := '1';
 761                 if is_fast_spr(e_in.read_reg1) then
 762                     result := a_in;
 763                     if decode_spr_num(e_in.insn) = SPR_XER then
 764                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 765                         result(63 downto 32) := (others => '0');
 766                         result(63-32) := v.e.xerc.so;
 767                         result(63-33) := v.e.xerc.ov;
 768                         result(63-34) := v.e.xerc.ca;
 769                         result(63-35 downto 63-43) := "000000000";
 770                         result(63-44) := v.e.xerc.ov32;
 771                         result(63-45) := v.e.xerc.ca32;
 772                     end if;
 773                 else
 774                     case decode_spr_num(e_in.insn) is
 775                     when SPR_TB =>
 776                         result := ctrl.tb;
 777                     when SPR_DEC =>
 778                         result := ctrl.dec;
 779                     when 724 =>     -- LOG_ADDR SPR
 780                         result := log_wr_addr & r.log_addr_spr;
 781                     when 725 =>     -- LOG_DATA SPR
 782                         result := log_rd_data;
 783                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 784                     when others =>
 785                         -- mfspr from unimplemented SPRs should be a nop in
 786                         -- supervisor mode and a program interrupt for user mode
 787                         result := c_in;
 788                         if ctrl.msr(MSR_PR) = '1' then
 789                             illegal := '1';
 790                         end if;
 791                     end case;
 792                 end if;
 793             when OP_MFCR =>
 794                 if e_in.insn(20) = '0' then
 795                     -- mfcr
 796                     result := x"00000000" & e_in.cr;
 797                 else
 798                     -- mfocrf
 799                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 800                     result := (others => '0');
 801                     for i in 0 to 7 loop
 802                         lo := (7-i)*4;
 803                         hi := lo + 3;
 804                         if crnum = i then
 805                             result(hi downto lo) := e_in.cr(hi downto lo);
 806                         end if;
 807                     end loop;
 808                 end if;
 809                 result_en := '1';
 810             when OP_MTCRF =>
 811                 v.e.write_cr_enable := '1';
 812                 if e_in.insn(20) = '0' then
 813                     -- mtcrf
 814                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 815                 else
 816                     -- mtocrf: We require one hot priority encoding here
 817                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 818                     v.e.write_cr_mask := num_to_fxm(crnum);
 819                 end if;
 820                 v.e.write_cr_data := c_in(31 downto 0);
 821             when OP_MTMSRD =>
 822                 if e_in.insn(16) = '1' then
 823                     -- just update EE and RI
 824                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 825                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 826                 else
 827                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 828                     -- and 63 (LE) (IBM bit numbering)
 829                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 830                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 831                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 832                     if c_in(MSR_PR) = '1' then
 833                         ctrl_tmp.msr(MSR_EE) <= '1';
 834                         ctrl_tmp.msr(MSR_IR) <= '1';
 835                         ctrl_tmp.msr(MSR_DR) <= '1';
 836                     end if;
 837                 end if;
 838             when OP_MTSPR =>
 839                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 840                     "=" & to_hstring(c_in);
 841                 if is_fast_spr(e_in.write_reg) then
 842                     result := c_in;
 843                     result_en := '1';
 844                     if decode_spr_num(e_in.insn) = SPR_XER then
 845                         v.e.xerc.so := c_in(63-32);
 846                         v.e.xerc.ov := c_in(63-33);
 847                         v.e.xerc.ca := c_in(63-34);
 848                         v.e.xerc.ov32 := c_in(63-44);
 849                         v.e.xerc.ca32 := c_in(63-45);
 850                         v.e.write_xerc_enable := '1';
 851                     end if;
 852                 else
 853                     -- slow spr
 854                     case decode_spr_num(e_in.insn) is
 855                     when SPR_DEC =>
 856                         ctrl_tmp.dec <= c_in;
 857                     when 724 =>     -- LOG_ADDR SPR
 858                         v.log_addr_spr := c_in(31 downto 0);
 859                     when others =>
 860                         -- mtspr to unimplemented SPRs should be a nop in
 861                         -- supervisor mode and a program interrupt for user mode
 862                         if ctrl.msr(MSR_PR) = '1' then
 863                             illegal := '1';
 864                         end if;
 865                     end case;
 866                 end if;
 867             when OP_POPCNT =>
 868                 result := popcnt_result;
 869                 result_en := '1';
 870             when OP_PRTY =>
 871                 result := parity_result;
 872                 result_en := '1';
 873             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
 874                 result := rotator_result;
 875                 if e_in.output_carry = '1' then
 876                     set_carry(v.e, rotator_carry, rotator_carry);
 877                 end if;
 878                 result_en := '1';
 879
 880             when OP_ISYNC =>
 881                 f_out.redirect <= '1';
 882                 f_out.redirect_nia <= next_nia;
 883
 884             when OP_ICBI =>
 885                 icache_inval <= '1';
 886
 887             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
 888                 v.e.valid := '0';
 889                 v.mul_in_progress := '1';
 890                 v.busy := '1';
 891                 x_to_multiply.valid <= '1';
 892
 893             when OP_DIV | OP_DIVE | OP_MOD =>
 894                 v.e.valid := '0';
 895                 v.div_in_progress := '1';
 896                 v.busy := '1';
 897                 x_to_divider.valid <= '1';
 898
 899             when others =>
 900                 v.terminate := '1';
 901                 report "illegal";
 902             end case;
 903
 904             v.e.rc := e_in.rc and valid_in;
 905
 906             -- Update LR on the next cycle after a branch link
 907             --
 908             -- WARNING: The LR update isn't tracked by our hazard tracker. This
 909             --          will work (well I hope) because it only happens on branches
 910             --          which will flush all decoded instructions. By the time
 911             --          fetch catches up, we'll have the new LR. This will
 912             --          *not* work properly however if we have a branch predictor,
 913             --          in which case the solution would probably be to keep a
 914             --          local cache of the updated LR in execute1 (flushed on
 915             --          exceptions) that is used instead of the value from
 916             --          decode when its content is valid.
 917             if e_in.lr = '1' then
 918                 v.lr_update := '1';
 919                 v.next_lr := next_nia;
 920                 v.e.valid := '0';
 921                 report "Delayed LR update to " & to_hstring(next_nia);
 922                 v.busy := '1';
 923             end if;
 924
 925         elsif valid_in = '1' then
 926             -- instruction for other units, i.e. LDST
 927             if e_in.unit = LDST then
 928                 lv.valid := '1';
 929             end if;
 930
 931         elsif r.lr_update = '1' then
 932             result_en := '1';
 933             result := r.next_lr;
 934             v.e.write_reg := fast_spr_num(SPR_LR);
 935             v.e.valid := '1';
 936         elsif r.cntz_in_progress = '1' then
 937             -- cnt[lt]z always takes two cycles
 938             result := countzero_result;
 939             result_en := '1';
 940             v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 941             v.e.rc := v.slow_op_rc;
 942             v.e.xerc := v.slow_op_xerc;
 943             v.e.valid := '1';
 944         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
 945             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
 946                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
 947                 if r.mul_in_progress = '1' then
 948                     overflow := '0';
 949                     case r.slow_op_insn is
 950                         when OP_MUL_H32 =>
 951                             result := multiply_to_x.result(63 downto 32) &
 952                                       multiply_to_x.result(63 downto 32);
 953                         when OP_MUL_H64 =>
 954                             result := multiply_to_x.result(127 downto 64);
 955                         when others =>
 956                             -- i.e. OP_MUL_L64
 957                             result := multiply_to_x.result(63 downto 0);
 958                             overflow := multiply_to_x.overflow;
 959                     end case;
 960                 else
 961                     result := divider_to_x.write_reg_data;
 962                     overflow := divider_to_x.overflow;
 963                 end if;
 964                 result_en := '1';
 965                 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 966                 v.e.rc := v.slow_op_rc;
 967                 v.e.xerc := v.slow_op_xerc;
 968                 v.e.write_xerc_enable := v.slow_op_oe;
 969                 -- We must test oe because the RC update code in writeback
 970                 -- will use the xerc value to set CR0:SO so we must not clobber
 971                 -- xerc if OE wasn't set.
 972                 if v.slow_op_oe = '1' then
 973                     v.e.xerc.ov := overflow;
 974                     v.e.xerc.ov32 := overflow;
 975                     v.e.xerc.so := v.slow_op_xerc.so or overflow;
 976                 end if;
 977                 v.e.valid := '1';
 978             else
 979                 v.busy := '1';
 980                 v.mul_in_progress := r.mul_in_progress;
 981                 v.div_in_progress := r.div_in_progress;
 982             end if;
 983         end if;
 984
 985         if illegal = '1' then
 986             exception := '1';
 987             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 988             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 989             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
 990             -- set bit 44 to indicate we have an illegal
 991             ctrl_tmp.srr1(63 - 44) <= '1';
 992             report "illegal";
 993         end if;
 994         if exception = '1' then
 995             v.e.exc_write_enable := '1';
 996             if exception_nextpc = '1' then
 997                 v.e.exc_write_data := next_nia;
 998             end if;
 999             ctrl_tmp.irq_state <= WRITE_SRR1;
1000             v.busy := '1';
1001             v.e.valid := '0';
1002         end if;
1003
1004         v.e.write_data := result;
1005         v.e.write_enable := result_en;
1006
1007         -- generate DSI or DSegI for load/store exceptions
1008         -- or ISI or ISegI for instruction fetch exceptions
1009         if l_in.exception = '1' then
1010             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
1011             if l_in.instr_fault = '0' then
1012                 if l_in.segment_fault = '0' then
1013                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#300#, 64));
1014                 else
1015                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#380#, 64));
1016                 end if;
1017             else
1018                 if l_in.segment_fault = '0' then
1019                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1020                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1021                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1022                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1023                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#400#, 64));
1024                 else
1025                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#480#, 64));
1026                 end if;
1027             end if;
1028             v.e.exc_write_enable := '1';
1029             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1030             v.e.exc_write_data := r.last_nia;
1031             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1032             ctrl_tmp.irq_state <= WRITE_SRR1;
1033         end if;
1034
1035         -- Outputs to loadstore1 (async)
1036         lv.op := e_in.insn_type;
1037         lv.nia := e_in.nia;
1038         lv.addr1 := a_in;
1039         lv.addr2 := b_in;
1040         lv.data := c_in;
1041         lv.write_reg := gspr_to_gpr(e_in.write_reg);
1042         lv.length := e_in.data_len;
1043         lv.byte_reverse := e_in.byte_reverse;
1044         lv.sign_extend := e_in.sign_extend;
1045         lv.update := e_in.update;
1046         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1047         lv.xerc := v.e.xerc;
1048         lv.reserve := e_in.reserve;
1049         lv.rc := e_in.rc;
1050         lv.insn := e_in.insn;
1051         -- decode l*cix and st*cix instructions here
1052         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1053             e_in.insn(5 downto 1) = "10101" then
1054             lv.ci := '1';
1055         end if;
1056         lv.virt_mode := ctrl.msr(MSR_DR);
1057         lv.priv_mode := not ctrl.msr(MSR_PR);
1058
1059         -- Update registers
1060         rin <= v;
1061
1062         -- update outputs
1063         --f_out <= r.f;
1064         l_out <= lv;
1065         e_out <= r.e;
1066         flush_out <= f_out.redirect;
1067
1068         exception_log <= exception;
1069         irq_valid_log <= irq_valid;
1070     end process;
1071
1072     ex1_log : process(clk)
1073     begin
1074         if rising_edge(clk) then
1075             log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1076                         ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1077                         exception_log &
1078                         irq_valid_log &
1079                         std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1080                         "000" &
1081                         r.e.write_enable &
1082                         r.e.valid &
1083                         f_out.redirect &
1084                         r.busy &
1085                         flush_out;
1086         end if;
1087     end process;
1088     log_out <= log_data;
1089 end architecture behaviour;