execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         -- Non-zero to enable log data collection
  17         LOG_LENGTH : natural := 0
  18         );
  19     port (
  20         clk   : in std_ulogic;
  21         rst   : in std_ulogic;
  22
  23         -- asynchronous
  24         flush_out : out std_ulogic;
  25         busy_out : out std_ulogic;
  26
  27         e_in  : in Decode2ToExecute1Type;
  28         l_in  : in Loadstore1ToExecute1Type;
  29
  30         ext_irq_in : std_ulogic;
  31
  32         -- asynchronous
  33         l_out : out Execute1ToLoadstore1Type;
  34         f_out : out Execute1ToFetch1Type;
  35
  36         e_out : out Execute1ToWritebackType;
  37
  38         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  39
  40         icache_inval : out std_ulogic;
  41         terminate_out : out std_ulogic;
  42
  43         log_out : out std_ulogic_vector(14 downto 0);
  44         log_rd_addr : out std_ulogic_vector(31 downto 0);
  45         log_rd_data : in std_ulogic_vector(63 downto 0);
  46         log_wr_addr : in std_ulogic_vector(31 downto 0)
  47         );
  48 end entity execute1;
  49
  50 architecture behaviour of execute1 is
  51     type reg_type is record
  52         e : Execute1ToWritebackType;
  53         f : Execute1ToFetch1Type;
  54         busy: std_ulogic;
  55         terminate: std_ulogic;
  56         lr_update : std_ulogic;
  57         next_lr : std_ulogic_vector(63 downto 0);
  58         mul_in_progress : std_ulogic;
  59         mul_finish : std_ulogic;
  60         div_in_progress : std_ulogic;
  61         cntz_in_progress : std_ulogic;
  62         slow_op_insn : insn_type_t;
  63         slow_op_dest : gpr_index_t;
  64         slow_op_rc : std_ulogic;
  65         slow_op_oe : std_ulogic;
  66         slow_op_xerc : xer_common_t;
  67         last_nia : std_ulogic_vector(63 downto 0);
  68         log_addr_spr : std_ulogic_vector(31 downto 0);
  69     end record;
  70     constant reg_type_init : reg_type :=
  71         (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
  72          busy => '0', lr_update => '0', terminate => '0',
  73          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  74          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  75          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
  76
  77     signal r, rin : reg_type;
  78
  79     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  80     signal cr_in : std_ulogic_vector(31 downto 0);
  81
  82     signal valid_in : std_ulogic;
  83     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  84     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  85     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  86     signal rot_sign_ext: std_ulogic;
  87     signal rotator_result: std_ulogic_vector(63 downto 0);
  88     signal rotator_carry: std_ulogic;
  89     signal logical_result: std_ulogic_vector(63 downto 0);
  90     signal countzero_result: std_ulogic_vector(63 downto 0);
  91
  92     -- multiply signals
  93     signal x_to_multiply: MultiplyInputType;
  94     signal multiply_to_x: MultiplyOutputType;
  95
  96     -- divider signals
  97     signal x_to_divider: Execute1ToDividerType;
  98     signal divider_to_x: DividerToExecute1Type;
  99
 100     -- random number generator signals
 101     signal random_raw  : std_ulogic_vector(63 downto 0);
 102     signal random_cond : std_ulogic_vector(63 downto 0);
 103     signal random_err  : std_ulogic;
 104
 105     -- signals for logging
 106     signal exception_log : std_ulogic;
 107     signal irq_valid_log : std_ulogic;
 108
 109     type privilege_level is (USER, SUPER);
 110     type op_privilege_array is array(insn_type_t) of privilege_level;
 111     constant op_privilege: op_privilege_array := (
 112         OP_ATTN => SUPER,
 113         OP_MFMSR => SUPER,
 114         OP_MTMSRD => SUPER,
 115         OP_RFID => SUPER,
 116         OP_TLBIE => SUPER,
 117         others => USER
 118         );
 119
 120     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 121         return boolean is
 122     begin
 123         if op_privilege(op) = SUPER then
 124             return true;
 125         elsif op = OP_MFSPR or op = OP_MTSPR then
 126             return insn(20) = '1';
 127         else
 128             return false;
 129         end if;
 130     end;
 131
 132     procedure set_carry(e: inout Execute1ToWritebackType;
 133                         carry32 : in std_ulogic;
 134                         carry : in std_ulogic) is
 135     begin
 136         e.xerc.ca32 := carry32;
 137         e.xerc.ca := carry;
 138         e.write_xerc_enable := '1';
 139     end;
 140
 141     procedure set_ov(e: inout Execute1ToWritebackType;
 142                      ov   : in std_ulogic;
 143                      ov32 : in std_ulogic) is
 144     begin
 145         e.xerc.ov32 := ov32;
 146         e.xerc.ov := ov;
 147         if ov = '1' then
 148             e.xerc.so := '1';
 149         end if;
 150         e.write_xerc_enable := '1';
 151     end;
 152
 153     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 154                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 155     begin
 156         return (ca xor msb_r) and not (msb_a xor msb_b);
 157     end;
 158
 159     function decode_input_carry(ic : carry_in_t;
 160                                 xerc : xer_common_t) return std_ulogic is
 161     begin
 162         case ic is
 163         when ZERO =>
 164             return '0';
 165         when CA =>
 166             return xerc.ca;
 167         when OV =>
 168             return xerc.ov;
 169         when ONE =>
 170             return '1';
 171         end case;
 172     end;
 173
 174     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 175         return std_ulogic_vector is
 176         variable msr_out: std_ulogic_vector(63 downto 0);
 177     begin
 178         -- ISA says this:
 179         --  Defined MSR bits are classified as either full func-
 180         --  tion or partial function. Full function MSR bits are
 181         --  saved in SRR1 or HSRR1 when an interrupt other
 182         --  than a System Call Vectored interrupt occurs and
 183         --  restored by rfscv, rfid, or hrfid, while partial func-
 184         --  tion MSR bits are not saved or restored.
 185         --  Full function MSR bits lie in the range 0:32, 37:41, and
 186         --  48:63, and partial function MSR bits lie in the range
 187         --  33:36 and 42:47. (Note this is IBM bit numbering).
 188         msr_out := (others => '0');
 189         msr_out(63 downto 31) := msr(63 downto 31);
 190         msr_out(26 downto 22) := msr(26 downto 22);
 191         msr_out(15 downto 0)  := msr(15 downto 0);
 192         return msr_out;
 193     end;
 194
 195     -- Tell vivado to keep the hierarchy for the random module so that the
 196     -- net names in the xdc file match.
 197     attribute keep_hierarchy : string;
 198     attribute keep_hierarchy of random_0 : label is "yes";
 199
 200 begin
 201
 202     rotator_0: entity work.rotator
 203         port map (
 204             rs => c_in,
 205             ra => a_in,
 206             shift => b_in(6 downto 0),
 207             insn => e_in.insn,
 208             is_32bit => e_in.is_32bit,
 209             right_shift => right_shift,
 210             arith => e_in.is_signed,
 211             clear_left => rot_clear_left,
 212             clear_right => rot_clear_right,
 213             sign_ext_rs => rot_sign_ext,
 214             result => rotator_result,
 215             carry_out => rotator_carry
 216             );
 217
 218     logical_0: entity work.logical
 219         port map (
 220             rs => c_in,
 221             rb => b_in,
 222             op => e_in.insn_type,
 223             invert_in => e_in.invert_a,
 224             invert_out => e_in.invert_out,
 225             result => logical_result,
 226             datalen => e_in.data_len
 227             );
 228
 229     countzero_0: entity work.zero_counter
 230         port map (
 231             clk => clk,
 232             rs => c_in,
 233             count_right => e_in.insn(10),
 234             is_32bit => e_in.is_32bit,
 235             result => countzero_result
 236             );
 237
 238     multiply_0: entity work.multiply
 239         port map (
 240             clk => clk,
 241             m_in => x_to_multiply,
 242             m_out => multiply_to_x
 243             );
 244
 245     divider_0: entity work.divider
 246         port map (
 247             clk => clk,
 248             rst => rst,
 249             d_in => x_to_divider,
 250             d_out => divider_to_x
 251             );
 252
 253     random_0: entity work.random
 254         port map (
 255             clk => clk,
 256             data => random_cond,
 257             raw => random_raw,
 258             err => random_err
 259             );
 260
 261     dbg_msr_out <= ctrl.msr;
 262     log_rd_addr <= r.log_addr_spr;
 263
 264     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 265     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 266     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 267
 268     busy_out <= l_in.busy or r.busy;
 269     valid_in <= e_in.valid and not busy_out;
 270
 271     terminate_out <= r.terminate;
 272
 273     execute1_0: process(clk)
 274     begin
 275         if rising_edge(clk) then
 276             if rst = '1' then
 277                 r <= reg_type_init;
 278                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 279                 ctrl.irq_state <= WRITE_SRR0;
 280             else
 281                 r <= rin;
 282                 ctrl <= ctrl_tmp;
 283                 assert not (r.lr_update = '1' and valid_in = '1')
 284                     report "LR update collision with valid in EX1"
 285                     severity failure;
 286                 if r.lr_update = '1' then
 287                     report "LR update to " & to_hstring(r.next_lr);
 288                 end if;
 289             end if;
 290         end if;
 291     end process;
 292
 293     execute1_1: process(all)
 294         variable v : reg_type;
 295         variable a_inv : std_ulogic_vector(63 downto 0);
 296         variable result : std_ulogic_vector(63 downto 0);
 297         variable newcrf : std_ulogic_vector(3 downto 0);
 298         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 299         variable result_en : std_ulogic;
 300         variable crnum : crnum_t;
 301         variable crbit : integer range 0 to 31;
 302         variable scrnum : crnum_t;
 303         variable lo, hi : integer;
 304         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 305         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 306         variable bo, bi : std_ulogic_vector(4 downto 0);
 307         variable bf, bfa : std_ulogic_vector(2 downto 0);
 308         variable cr_op : std_ulogic_vector(9 downto 0);
 309         variable cr_operands : std_ulogic_vector(1 downto 0);
 310         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 311         variable btnum, banum, bbnum : integer range 0 to 31;
 312         variable crresult : std_ulogic;
 313         variable l : std_ulogic;
 314         variable next_nia : std_ulogic_vector(63 downto 0);
 315         variable carry_32, carry_64 : std_ulogic;
 316         variable sign1, sign2 : std_ulogic;
 317         variable abs1, abs2 : signed(63 downto 0);
 318         variable overflow : std_ulogic;
 319         variable zerohi, zerolo : std_ulogic;
 320         variable msb_a, msb_b : std_ulogic;
 321         variable a_lt : std_ulogic;
 322         variable lv : Execute1ToLoadstore1Type;
 323         variable irq_valid : std_ulogic;
 324         variable exception : std_ulogic;
 325         variable exception_nextpc : std_ulogic;
 326         variable trapval : std_ulogic_vector(4 downto 0);
 327         variable illegal : std_ulogic;
 328         variable is_branch : std_ulogic;
 329         variable taken_branch : std_ulogic;
 330         variable abs_branch : std_ulogic;
 331         variable spr_val : std_ulogic_vector(63 downto 0);
 332         variable addend : std_ulogic_vector(127 downto 0);
 333     begin
 334         result := (others => '0');
 335         sum_with_carry := (others => '0');
 336         result_en := '0';
 337         newcrf := (others => '0');
 338         is_branch := '0';
 339         taken_branch := '0';
 340         abs_branch := '0';
 341
 342         v := r;
 343         v.e := Execute1ToWritebackInit;
 344         lv := Execute1ToLoadstore1Init;
 345         v.f.redirect := '0';
 346
 347         -- XER forwarding. To avoid having to track XER hazards, we
 348         -- use the previously latched value.
 349         --
 350         -- If the XER was modified by a multiply or a divide, those are
 351         -- single issue, we'll get the up to date value from decode2 from
 352         -- the register file.
 353         --
 354         -- If it was modified by an instruction older than the previous
 355         -- one in EX1, it will have also hit writeback and will be up
 356         -- to date in decode2.
 357         --
 358         -- That leaves us with the case where it was updated by the previous
 359         -- instruction in EX1. In that case, we can forward it back here.
 360         --
 361         -- This will break if we allow pipelining of multiply and divide,
 362         -- but ideally, those should go via EX1 anyway and run as a state
 363         -- machine from here.
 364         --
 365         -- One additional hazard to beware of is an XER:SO modifying instruction
 366         -- in EX1 followed immediately by a store conditional. Due to our
 367         -- writeback latency, the store will go down the LSU with the previous
 368         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 369         --
 370         -- We will need to handle that if we ever make stcx. not single issue
 371         --
 372         -- We always pass a valid XER value downto writeback even when
 373         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 374         -- to work for RC instructions.
 375         --
 376         if r.e.write_xerc_enable = '1' then
 377             v.e.xerc := r.e.xerc;
 378         else
 379             v.e.xerc := e_in.xerc;
 380         end if;
 381
 382         -- CR forwarding
 383         cr_in <= e_in.cr;
 384         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 385             for i in 0 to 7 loop
 386                 if r.e.write_cr_mask(i) = '1' then
 387                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 388                 end if;
 389             end loop;
 390         end if;
 391
 392         v.lr_update := '0';
 393         v.mul_in_progress := '0';
 394         v.div_in_progress := '0';
 395         v.cntz_in_progress := '0';
 396         v.mul_finish := '0';
 397
 398         -- Main adder
 399         if e_in.invert_a = '0' then
 400             a_inv := a_in;
 401         else
 402             a_inv := not a_in;
 403         end if;
 404         sum_with_carry := ppc_adde(a_inv, b_in,
 405                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 406
 407         -- signals to multiply and divide units
 408         sign1 := '0';
 409         sign2 := '0';
 410         if e_in.is_signed = '1' then
 411             if e_in.is_32bit = '1' then
 412                 sign1 := a_in(31);
 413                 sign2 := b_in(31);
 414             else
 415                 sign1 := a_in(63);
 416                 sign2 := b_in(63);
 417             end if;
 418         end if;
 419         -- take absolute values
 420         if sign1 = '0' then
 421             abs1 := signed(a_in);
 422         else
 423             abs1 := - signed(a_in);
 424         end if;
 425         if sign2 = '0' then
 426             abs2 := signed(b_in);
 427         else
 428             abs2 := - signed(b_in);
 429         end if;
 430
 431         x_to_multiply <= MultiplyInputInit;
 432         x_to_multiply.is_32bit <= e_in.is_32bit;
 433
 434         x_to_divider <= Execute1ToDividerInit;
 435         x_to_divider.is_signed <= e_in.is_signed;
 436         x_to_divider.is_32bit <= e_in.is_32bit;
 437         if e_in.insn_type = OP_MOD then
 438             x_to_divider.is_modulus <= '1';
 439         end if;
 440
 441         addend := (others => '0');
 442         if e_in.insn(26) = '0' then
 443             -- integer multiply-add, major op 4 (if it is a multiply)
 444             addend(63 downto 0) := c_in;
 445             if e_in.is_signed = '1' then
 446                 addend(127 downto 64) := (others => c_in(63));
 447             end if;
 448         end if;
 449         if (sign1 xor sign2) = '1' then
 450             addend := not addend;
 451         end if;
 452
 453         x_to_multiply.not_result <= sign1 xor sign2;
 454         x_to_multiply.addend <= addend;
 455         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 456         if e_in.is_32bit = '0' then
 457             -- 64-bit forms
 458             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 459             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 460             if e_in.insn_type = OP_DIVE then
 461                 x_to_divider.is_extended <= '1';
 462             end if;
 463             x_to_divider.dividend <= std_ulogic_vector(abs1);
 464             x_to_divider.divisor <= std_ulogic_vector(abs2);
 465         else
 466             -- 32-bit forms
 467             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 468             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 469             x_to_divider.is_extended <= '0';
 470             if e_in.insn_type = OP_DIVE then   -- extended forms
 471                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 472             else
 473                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 474             end if;
 475             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 476         end if;
 477
 478         ctrl_tmp <= ctrl;
 479         -- FIXME: run at 512MHz not core freq
 480         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 481         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 482
 483         irq_valid := '0';
 484         if ctrl.msr(MSR_EE) = '1' then
 485             if ctrl.dec(63) = '1' then
 486                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
 487                 report "IRQ valid: DEC";
 488                 irq_valid := '1';
 489             elsif ext_irq_in = '1' then
 490                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
 491                 report "IRQ valid: External";
 492                 irq_valid := '1';
 493             end if;
 494         end if;
 495
 496         v.terminate := '0';
 497         icache_inval <= '0';
 498         v.busy := '0';
 499         -- send MSR[IR], ~MSR[PR] and ~MSR[LE] up to fetch1
 500         v.f.virt_mode := ctrl.msr(MSR_IR);
 501         v.f.priv_mode := not ctrl.msr(MSR_PR);
 502         v.f.big_endian := not ctrl.msr(MSR_LE);
 503
 504         -- Next insn adder used in a couple of places
 505         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 506
 507         -- rotator control signals
 508         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 509         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 510         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 511         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 512
 513         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 514         ctrl_tmp.irq_state <= WRITE_SRR0;
 515         exception := '0';
 516         illegal := '0';
 517         exception_nextpc := '0';
 518         v.e.exc_write_enable := '0';
 519         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 520         v.e.exc_write_data := e_in.nia;
 521         if valid_in = '1' then
 522             v.last_nia := e_in.nia;
 523         end if;
 524
 525         if ctrl.irq_state = WRITE_SRR1 then
 526             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 527             v.e.exc_write_data := ctrl.srr1;
 528             v.e.exc_write_enable := '1';
 529             ctrl_tmp.msr(MSR_SF) <= '1';
 530             ctrl_tmp.msr(MSR_EE) <= '0';
 531             ctrl_tmp.msr(MSR_PR) <= '0';
 532             ctrl_tmp.msr(MSR_IR) <= '0';
 533             ctrl_tmp.msr(MSR_DR) <= '0';
 534             ctrl_tmp.msr(MSR_RI) <= '0';
 535             ctrl_tmp.msr(MSR_LE) <= '1';
 536             v.e.valid := '1';
 537             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 538
 539         elsif irq_valid = '1' and valid_in = '1' then
 540             -- we need two cycles to write srr0 and 1
 541             -- will need more when we have to write HEIR
 542             -- Don't deliver the interrupt until we have a valid instruction
 543             -- coming in, so we have a valid NIA to put in SRR0.
 544             exception := '1';
 545
 546         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 547             instr_is_privileged(e_in.insn_type, e_in.insn) then
 548             -- generate a program interrupt
 549             exception := '1';
 550             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 551             -- set bit 45 to indicate privileged instruction type interrupt
 552             ctrl_tmp.srr1(63 - 45) <= '1';
 553             report "privileged instruction";
 554
 555         elsif valid_in = '1' and e_in.unit = ALU then
 556
 557             report "execute nia " & to_hstring(e_in.nia);
 558
 559             v.e.valid := '1';
 560             v.e.write_reg := e_in.write_reg;
 561             v.slow_op_insn := e_in.insn_type;
 562             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 563             v.slow_op_rc := e_in.rc;
 564             v.slow_op_oe := e_in.oe;
 565             v.slow_op_xerc := v.e.xerc;
 566
 567             case_0: case e_in.insn_type is
 568
 569             when OP_ILLEGAL =>
 570                 -- we need two cycles to write srr0 and 1
 571                 -- will need more when we have to write HEIR
 572                 illegal := '1';
 573             when OP_SC =>
 574                 -- check bit 1 of the instruction is 1 so we know this is sc;
 575                 -- 0 would mean scv, so generate an illegal instruction interrupt
 576                 -- we need two cycles to write srr0 and 1
 577                 if e_in.insn(1) = '1' then
 578                     exception := '1';
 579                     exception_nextpc := '1';
 580                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
 581                     report "sc";
 582                 else
 583                     illegal := '1';
 584                 end if;
 585             when OP_ATTN =>
 586                 -- check bits 1-10 of the instruction to make sure it's attn
 587                 -- if not then it is illegal
 588                 if e_in.insn(10 downto 1) = "0100000000" then
 589                     v.terminate := '1';
 590                     report "ATTN";
 591                 else
 592                     illegal := '1';
 593                 end if;
 594             when OP_NOP =>
 595                 -- Do nothing
 596             when OP_ADD | OP_CMP | OP_TRAP =>
 597                 result := sum_with_carry(63 downto 0);
 598                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 599                 carry_64 := sum_with_carry(64);
 600                 if e_in.insn_type = OP_ADD then
 601                     if e_in.output_carry = '1' then
 602                         if e_in.input_carry /= OV then
 603                             set_carry(v.e, carry_32, carry_64);
 604                         else
 605                             v.e.xerc.ov := carry_64;
 606                             v.e.xerc.ov32 := carry_32;
 607                             v.e.write_xerc_enable := '1';
 608                         end if;
 609                     end if;
 610                     if e_in.oe = '1' then
 611                         set_ov(v.e,
 612                                calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 613                                calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 614                     end if;
 615                     result_en := '1';
 616                 else
 617                     -- trap, CMP and CMPL instructions
 618                     -- Note, we have done RB - RA, not RA - RB
 619                     if e_in.insn_type = OP_CMP then
 620                         l := insn_l(e_in.insn);
 621                     else
 622                         l := not e_in.is_32bit;
 623                     end if;
 624                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 625                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 626                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 627                         -- values are equal
 628                         trapval := "00100";
 629                     else
 630                         if l = '1' then
 631                             -- 64-bit comparison
 632                             msb_a := a_in(63);
 633                             msb_b := b_in(63);
 634                         else
 635                             -- 32-bit comparison
 636                             msb_a := a_in(31);
 637                             msb_b := b_in(31);
 638                         end if;
 639                         if msb_a /= msb_b then
 640                             -- Subtraction might overflow, but
 641                             -- comparison is clear from MSB difference.
 642                             -- for signed, 0 is greater; for unsigned, 1 is greater
 643                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 644                         else
 645                             -- Subtraction cannot overflow since MSBs are equal.
 646                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 647                             a_lt := (not l and carry_32) or (l and carry_64);
 648                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 649                         end if;
 650                     end if;
 651                     if e_in.insn_type = OP_CMP then
 652                         if e_in.is_signed = '1' then
 653                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 654                         else
 655                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 656                         end if;
 657                         bf := insn_bf(e_in.insn);
 658                         crnum := to_integer(unsigned(bf));
 659                         v.e.write_cr_enable := '1';
 660                         v.e.write_cr_mask := num_to_fxm(crnum);
 661                         for i in 0 to 7 loop
 662                             lo := i*4;
 663                             hi := lo + 3;
 664                             v.e.write_cr_data(hi downto lo) := newcrf;
 665                         end loop;
 666                     else
 667                         -- trap instructions (tw, twi, td, tdi)
 668                         v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 669                         -- set bit 46 to say trap occurred
 670                         ctrl_tmp.srr1(63 - 46) <= '1';
 671                         if or (trapval and insn_to(e_in.insn)) = '1' then
 672                             -- generate trap-type program interrupt
 673                             exception := '1';
 674                             report "trap";
 675                         end if;
 676                     end if;
 677                 end if;
 678             when OP_ADDG6S =>
 679                 result := (others => '0');
 680                 for i in 0 to 14 loop
 681                     lo := i * 4;
 682                     hi := (i + 1) * 4;
 683                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 684                         result(lo + 3 downto lo) := "0110";
 685                     end if;
 686                 end loop;
 687                 if sum_with_carry(64) = '0' then
 688                     result(63 downto 60) := "0110";
 689                 end if;
 690                 result_en := '1';
 691             when OP_CMPRB =>
 692                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 693                 bf := insn_bf(e_in.insn);
 694                 crnum := to_integer(unsigned(bf));
 695                 v.e.write_cr_enable := '1';
 696                 v.e.write_cr_mask := num_to_fxm(crnum);
 697                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 698                                      newcrf & newcrf & newcrf & newcrf;
 699             when OP_CMPEQB =>
 700                 newcrf := ppc_cmpeqb(a_in, b_in);
 701                 bf := insn_bf(e_in.insn);
 702                 crnum := to_integer(unsigned(bf));
 703                 v.e.write_cr_enable := '1';
 704                 v.e.write_cr_mask := num_to_fxm(crnum);
 705                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 706                                      newcrf & newcrf & newcrf & newcrf;
 707             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 708                     OP_BPERM | OP_BCD =>
 709                 result := logical_result;
 710                 result_en := '1';
 711             when OP_B =>
 712                 is_branch := '1';
 713                 taken_branch := '1';
 714                 abs_branch := insn_aa(e_in.insn);
 715             when OP_BC =>
 716                 -- read_data1 is CTR
 717                 bo := insn_bo(e_in.insn);
 718                 bi := insn_bi(e_in.insn);
 719                 if bo(4-2) = '0' then
 720                     result := std_ulogic_vector(unsigned(a_in) - 1);
 721                     result_en := '1';
 722                     v.e.write_reg := fast_spr_num(SPR_CTR);
 723                 end if;
 724                 is_branch := '1';
 725                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 726                 abs_branch := insn_aa(e_in.insn);
 727             when OP_BCREG =>
 728                 -- read_data1 is CTR
 729                 -- read_data2 is target register (CTR, LR or TAR)
 730                 bo := insn_bo(e_in.insn);
 731                 bi := insn_bi(e_in.insn);
 732                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 733                     result := std_ulogic_vector(unsigned(a_in) - 1);
 734                     result_en := '1';
 735                     v.e.write_reg := fast_spr_num(SPR_CTR);
 736                 end if;
 737                 is_branch := '1';
 738                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 739                 abs_branch := '1';
 740
 741             when OP_RFID =>
 742                 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
 743                 v.f.priv_mode := not a_in(MSR_PR);
 744                 v.f.big_endian := not a_in(MSR_LE);
 745                 -- Can't use msr_copy here because the partial function MSR
 746                 -- bits should be left unchanged, not zeroed.
 747                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 748                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 749                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 750                 if a_in(MSR_PR) = '1' then
 751                     ctrl_tmp.msr(MSR_EE) <= '1';
 752                     ctrl_tmp.msr(MSR_IR) <= '1';
 753                     ctrl_tmp.msr(MSR_DR) <= '1';
 754                 end if;
 755                 -- mark this as a branch so CFAR gets updated
 756                 is_branch := '1';
 757                 taken_branch := '1';
 758                 abs_branch := '1';
 759
 760             when OP_CNTZ =>
 761                 v.e.valid := '0';
 762                 v.cntz_in_progress := '1';
 763                 v.busy := '1';
 764             when OP_ISEL =>
 765                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 766                 if cr_in(31-crbit) = '1' then
 767                     result := a_in;
 768                 else
 769                     result := b_in;
 770                 end if;
 771                 result_en := '1';
 772             when OP_CROP =>
 773                 cr_op := insn_cr(e_in.insn);
 774                 report "CR OP " & to_hstring(cr_op);
 775                 if cr_op(0) = '0' then -- MCRF
 776                     bf := insn_bf(e_in.insn);
 777                     bfa := insn_bfa(e_in.insn);
 778                     v.e.write_cr_enable := '1';
 779                     crnum := to_integer(unsigned(bf));
 780                     scrnum := to_integer(unsigned(bfa));
 781                     v.e.write_cr_mask := num_to_fxm(crnum);
 782                     for i in 0 to 7 loop
 783                         lo := (7-i)*4;
 784                         hi := lo + 3;
 785                         if i = scrnum then
 786                             newcrf := cr_in(hi downto lo);
 787                         end if;
 788                     end loop;
 789                     for i in 0 to 7 loop
 790                         lo := i*4;
 791                         hi := lo + 3;
 792                         v.e.write_cr_data(hi downto lo) := newcrf;
 793                     end loop;
 794                 else
 795                     v.e.write_cr_enable := '1';
 796                     bt := insn_bt(e_in.insn);
 797                     ba := insn_ba(e_in.insn);
 798                     bb := insn_bb(e_in.insn);
 799                     btnum := 31 - to_integer(unsigned(bt));
 800                     banum := 31 - to_integer(unsigned(ba));
 801                     bbnum := 31 - to_integer(unsigned(bb));
 802                     -- Bits 5-8 of cr_op give the truth table of the requested
 803                     -- logical operation
 804                     cr_operands := cr_in(banum) & cr_in(bbnum);
 805                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 806                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 807                     for i in 0 to 31 loop
 808                         if i = btnum then
 809                             v.e.write_cr_data(i) := crresult;
 810                         else
 811                             v.e.write_cr_data(i) := cr_in(i);
 812                         end if;
 813                     end loop;
 814                 end if;
 815             when OP_MCRXRX =>
 816                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 817                 bf := insn_bf(e_in.insn);
 818                 crnum := to_integer(unsigned(bf));
 819                 v.e.write_cr_enable := '1';
 820                 v.e.write_cr_mask := num_to_fxm(crnum);
 821                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 822                                      newcrf & newcrf & newcrf & newcrf;
 823             when OP_DARN =>
 824                 if random_err = '0' then
 825                     case e_in.insn(17 downto 16) is
 826                         when "00" =>
 827                             result := x"00000000" & random_cond(31 downto 0);
 828                         when "10" =>
 829                             result := random_raw;
 830                         when others =>
 831                             result := random_cond;
 832                     end case;
 833                 else
 834                     result := (others => '1');
 835                 end if;
 836                 result_en := '1';
 837             when OP_MFMSR =>
 838                 result := ctrl.msr;
 839                 result_en := '1';
 840             when OP_MFSPR =>
 841                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 842                     "=" & to_hstring(a_in);
 843                 result_en := '1';
 844                 if is_fast_spr(e_in.read_reg1) then
 845                     result := a_in;
 846                     if decode_spr_num(e_in.insn) = SPR_XER then
 847                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 848                         result(63 downto 32) := (others => '0');
 849                         result(63-32) := v.e.xerc.so;
 850                         result(63-33) := v.e.xerc.ov;
 851                         result(63-34) := v.e.xerc.ca;
 852                         result(63-35 downto 63-43) := "000000000";
 853                         result(63-44) := v.e.xerc.ov32;
 854                         result(63-45) := v.e.xerc.ca32;
 855                     end if;
 856                 else
 857                     spr_val := c_in;
 858                     case decode_spr_num(e_in.insn) is
 859                     when SPR_TB =>
 860                         spr_val := ctrl.tb;
 861                     when SPR_TBU =>
 862                         spr_val(63 downto 32) := (others => '0');
 863                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 864                     when SPR_DEC =>
 865                         spr_val := ctrl.dec;
 866                     when SPR_CFAR =>
 867                         spr_val := ctrl.cfar;
 868                     when SPR_PVR =>
 869                         spr_val(63 downto 32) := (others => '0');
 870                         spr_val(31 downto 0) := PVR_MICROWATT;
 871                     when 724 =>     -- LOG_ADDR SPR
 872                         spr_val := log_wr_addr & r.log_addr_spr;
 873                     when 725 =>     -- LOG_DATA SPR
 874                         spr_val := log_rd_data;
 875                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 876                     when others =>
 877                         -- mfspr from unimplemented SPRs should be a nop in
 878                         -- supervisor mode and a program interrupt for user mode
 879                         if ctrl.msr(MSR_PR) = '1' then
 880                             illegal := '1';
 881                         end if;
 882                     end case;
 883                     result := spr_val;
 884                 end if;
 885             when OP_MFCR =>
 886                 if e_in.insn(20) = '0' then
 887                     -- mfcr
 888                     result := x"00000000" & cr_in;
 889                 else
 890                     -- mfocrf
 891                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 892                     result := (others => '0');
 893                     for i in 0 to 7 loop
 894                         lo := (7-i)*4;
 895                         hi := lo + 3;
 896                         if crnum = i then
 897                             result(hi downto lo) := cr_in(hi downto lo);
 898                         end if;
 899                     end loop;
 900                 end if;
 901                 result_en := '1';
 902             when OP_MTCRF =>
 903                 v.e.write_cr_enable := '1';
 904                 if e_in.insn(20) = '0' then
 905                     -- mtcrf
 906                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 907                 else
 908                     -- mtocrf: We require one hot priority encoding here
 909                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 910                     v.e.write_cr_mask := num_to_fxm(crnum);
 911                 end if;
 912                 v.e.write_cr_data := c_in(31 downto 0);
 913             when OP_MTMSRD =>
 914                 if e_in.insn(16) = '1' then
 915                     -- just update EE and RI
 916                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 917                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 918                 else
 919                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 920                     -- and 63 (LE) (IBM bit numbering)
 921                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 922                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 923                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 924                     if c_in(MSR_PR) = '1' then
 925                         ctrl_tmp.msr(MSR_EE) <= '1';
 926                         ctrl_tmp.msr(MSR_IR) <= '1';
 927                         ctrl_tmp.msr(MSR_DR) <= '1';
 928                     end if;
 929                 end if;
 930             when OP_MTSPR =>
 931                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 932                     "=" & to_hstring(c_in);
 933                 if is_fast_spr(e_in.write_reg) then
 934                     result := c_in;
 935                     result_en := '1';
 936                     if decode_spr_num(e_in.insn) = SPR_XER then
 937                         v.e.xerc.so := c_in(63-32);
 938                         v.e.xerc.ov := c_in(63-33);
 939                         v.e.xerc.ca := c_in(63-34);
 940                         v.e.xerc.ov32 := c_in(63-44);
 941                         v.e.xerc.ca32 := c_in(63-45);
 942                         v.e.write_xerc_enable := '1';
 943                     end if;
 944                 else
 945                     -- slow spr
 946                     case decode_spr_num(e_in.insn) is
 947                     when SPR_DEC =>
 948                         ctrl_tmp.dec <= c_in;
 949                     when 724 =>     -- LOG_ADDR SPR
 950                         v.log_addr_spr := c_in(31 downto 0);
 951                     when others =>
 952                         -- mtspr to unimplemented SPRs should be a nop in
 953                         -- supervisor mode and a program interrupt for user mode
 954                         if ctrl.msr(MSR_PR) = '1' then
 955                             illegal := '1';
 956                         end if;
 957                     end case;
 958                 end if;
 959             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
 960                 result := rotator_result;
 961                 if e_in.output_carry = '1' then
 962                     set_carry(v.e, rotator_carry, rotator_carry);
 963                 end if;
 964                 result_en := '1';
 965             when OP_SETB =>
 966                 bfa := insn_bfa(e_in.insn);
 967                 crbit := to_integer(unsigned(bfa)) * 4;
 968                 result := (others => '0');
 969                 if cr_in(31 - crbit) = '1' then
 970                     result := (others => '1');
 971                 elsif cr_in(30 - crbit) = '1' then
 972                     result(0) := '1';
 973                 end if;
 974
 975             when OP_ISYNC =>
 976                 v.f.redirect := '1';
 977                 v.f.redirect_nia := next_nia;
 978
 979             when OP_ICBI =>
 980                 icache_inval <= '1';
 981
 982             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
 983                 v.e.valid := '0';
 984                 v.mul_in_progress := '1';
 985                 v.busy := '1';
 986                 x_to_multiply.valid <= '1';
 987
 988             when OP_DIV | OP_DIVE | OP_MOD =>
 989                 v.e.valid := '0';
 990                 v.div_in_progress := '1';
 991                 v.busy := '1';
 992                 x_to_divider.valid <= '1';
 993
 994             when others =>
 995                 v.terminate := '1';
 996                 report "illegal";
 997             end case;
 998
 999             v.e.rc := e_in.rc and valid_in;
1000
1001             -- Mispredicted branches cause a redirect
1002             if is_branch = '1' then
1003                 if taken_branch = '1' then
1004                     ctrl_tmp.cfar <= e_in.nia;
1005                 end if;
1006                 if e_in.br_pred = '0' then
1007                     if abs_branch = '1' then
1008                         v.f.redirect_nia := b_in;
1009                     else
1010                         v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
1011                     end if;
1012                 else
1013                     v.f.redirect_nia := next_nia;
1014                 end if;
1015                 if taken_branch /= e_in.br_pred then
1016                     v.f.redirect := '1';
1017                 end if;
1018             end if;
1019
1020             -- Update LR on the next cycle after a branch link
1021             -- If we're not writing back anything else, we can write back LR
1022             -- this cycle, otherwise we take an extra cycle.  We use the
1023             -- exc_write path since next_nia is written through that path
1024             -- in other places.
1025             if e_in.lr = '1' then
1026                 if result_en = '0' then
1027                     v.e.exc_write_enable := '1';
1028                     v.e.exc_write_data := next_nia;
1029                     v.e.exc_write_reg := fast_spr_num(SPR_LR);
1030                 else
1031                     v.lr_update := '1';
1032                     v.next_lr := next_nia;
1033                     v.e.valid := '0';
1034                     report "Delayed LR update to " & to_hstring(next_nia);
1035                     v.busy := '1';
1036                 end if;
1037             end if;
1038
1039         elsif valid_in = '1' then
1040             -- instruction for other units, i.e. LDST
1041             if e_in.unit = LDST then
1042                 lv.valid := '1';
1043             end if;
1044
1045         elsif r.f.redirect = '1' then
1046             v.e.valid := '1';
1047         elsif r.lr_update = '1' then
1048             v.e.exc_write_enable := '1';
1049             v.e.exc_write_data := r.next_lr;
1050             v.e.exc_write_reg := fast_spr_num(SPR_LR);
1051             v.e.valid := '1';
1052         elsif r.cntz_in_progress = '1' then
1053             -- cnt[lt]z always takes two cycles
1054             result := countzero_result;
1055             result_en := '1';
1056             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1057             v.e.rc := r.slow_op_rc;
1058             v.e.xerc := r.slow_op_xerc;
1059             v.e.valid := '1';
1060         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1061             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1062                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1063                 if r.mul_in_progress = '1' then
1064                     overflow := '0';
1065                     case r.slow_op_insn is
1066                         when OP_MUL_H32 =>
1067                             result := multiply_to_x.result(63 downto 32) &
1068                                       multiply_to_x.result(63 downto 32);
1069                         when OP_MUL_H64 =>
1070                             result := multiply_to_x.result(127 downto 64);
1071                         when others =>
1072                             -- i.e. OP_MUL_L64
1073                             result := multiply_to_x.result(63 downto 0);
1074                     end case;
1075                 else
1076                     result := divider_to_x.write_reg_data;
1077                     overflow := divider_to_x.overflow;
1078                 end if;
1079                 if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
1080                     -- have to wait until next cycle for overflow indication
1081                     v.mul_finish := '1';
1082                     v.busy := '1';
1083                 else
1084                     result_en := '1';
1085                     v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1086                     v.e.rc := r.slow_op_rc;
1087                     v.e.xerc := r.slow_op_xerc;
1088                     v.e.write_xerc_enable := r.slow_op_oe;
1089                     -- We must test oe because the RC update code in writeback
1090                     -- will use the xerc value to set CR0:SO so we must not clobber
1091                     -- xerc if OE wasn't set.
1092                     if r.slow_op_oe = '1' then
1093                         v.e.xerc.ov := overflow;
1094                         v.e.xerc.ov32 := overflow;
1095                         v.e.xerc.so := r.slow_op_xerc.so or overflow;
1096                     end if;
1097                     v.e.valid := '1';
1098                 end if;
1099             else
1100                 v.busy := '1';
1101                 v.mul_in_progress := r.mul_in_progress;
1102                 v.div_in_progress := r.div_in_progress;
1103             end if;
1104         elsif r.mul_finish = '1' then
1105             result := r.e.write_data;
1106             result_en := '1';
1107             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1108             v.e.rc := r.slow_op_rc;
1109             v.e.xerc := r.slow_op_xerc;
1110             v.e.write_xerc_enable := r.slow_op_oe;
1111             v.e.xerc.ov := multiply_to_x.overflow;
1112             v.e.xerc.ov32 := multiply_to_x.overflow;
1113             v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
1114             v.e.valid := '1';
1115         end if;
1116
1117         if illegal = '1' then
1118             exception := '1';
1119             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1120             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1121             -- set bit 44 to indicate we have an illegal
1122             ctrl_tmp.srr1(63 - 44) <= '1';
1123             report "illegal";
1124         end if;
1125         if exception = '1' then
1126             v.e.exc_write_enable := '1';
1127             if exception_nextpc = '1' then
1128                 v.e.exc_write_data := next_nia;
1129             end if;
1130         end if;
1131
1132         v.e.write_data := result;
1133         v.e.write_enable := result_en and not exception;
1134
1135         -- generate DSI or DSegI for load/store exceptions
1136         -- or ISI or ISegI for instruction fetch exceptions
1137         if l_in.exception = '1' then
1138             if l_in.instr_fault = '0' then
1139                 if l_in.segment_fault = '0' then
1140                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1141                 else
1142                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1143                 end if;
1144             else
1145                 if l_in.segment_fault = '0' then
1146                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1147                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1148                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1149                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1150                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1151                 else
1152                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1153                 end if;
1154             end if;
1155             v.e.exc_write_enable := '1';
1156             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1157             v.e.exc_write_data := r.last_nia;
1158             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1159         end if;
1160
1161         if exception = '1' or l_in.exception = '1' then
1162             ctrl_tmp.irq_state <= WRITE_SRR1;
1163             v.f.redirect := '1';
1164             v.f.virt_mode := '0';
1165             v.f.priv_mode := '1';
1166             -- XXX need an interrupt LE bit here, e.g. from LPCR
1167             v.f.big_endian := '0';
1168         end if;
1169
1170         if v.f.redirect = '1' then
1171             v.busy := '1';
1172             v.e.valid := '0';
1173         end if;
1174
1175         -- Outputs to loadstore1 (async)
1176         lv.op := e_in.insn_type;
1177         lv.nia := e_in.nia;
1178         lv.addr1 := a_in;
1179         lv.addr2 := b_in;
1180         lv.data := c_in;
1181         lv.write_reg := gspr_to_gpr(e_in.write_reg);
1182         lv.length := e_in.data_len;
1183         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1184         lv.sign_extend := e_in.sign_extend;
1185         lv.update := e_in.update;
1186         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1187         lv.xerc := v.e.xerc;
1188         lv.reserve := e_in.reserve;
1189         lv.rc := e_in.rc;
1190         lv.insn := e_in.insn;
1191         -- decode l*cix and st*cix instructions here
1192         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1193             e_in.insn(5 downto 1) = "10101" then
1194             lv.ci := '1';
1195         end if;
1196         lv.virt_mode := ctrl.msr(MSR_DR);
1197         lv.priv_mode := not ctrl.msr(MSR_PR);
1198
1199         -- Update registers
1200         rin <= v;
1201
1202         -- update outputs
1203         f_out <= r.f;
1204         l_out <= lv;
1205         e_out <= r.e;
1206         flush_out <= f_out.redirect;
1207
1208         exception_log <= exception;
1209         irq_valid_log <= irq_valid;
1210     end process;
1211
1212     e1_log: if LOG_LENGTH > 0 generate
1213         signal log_data : std_ulogic_vector(14 downto 0);
1214     begin
1215         ex1_log : process(clk)
1216         begin
1217             if rising_edge(clk) then
1218                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1219                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1220                             exception_log &
1221                             irq_valid_log &
1222                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1223                             "000" &
1224                             r.e.write_enable &
1225                             r.e.valid &
1226                             f_out.redirect &
1227                             r.busy &
1228                             flush_out;
1229             end if;
1230         end process;
1231         log_out <= log_data;
1232     end generate;
1233 end architecture behaviour;