execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true
  16         );
  17     port (
  18         clk   : in std_ulogic;
  19         rst   : in std_ulogic;
  20
  21         -- asynchronous
  22         flush_out : out std_ulogic;
  23         stall_out : out std_ulogic;
  24
  25         e_in  : in Decode2ToExecute1Type;
  26         l_in  : in Loadstore1ToExecute1Type;
  27
  28         ext_irq_in : std_ulogic;
  29
  30         -- asynchronous
  31         l_out : out Execute1ToLoadstore1Type;
  32         f_out : out Execute1ToFetch1Type;
  33
  34         e_out : out Execute1ToWritebackType;
  35
  36         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  37
  38         icache_inval : out std_ulogic;
  39         terminate_out : out std_ulogic;
  40
  41         log_out : out std_ulogic_vector(14 downto 0);
  42         log_rd_addr : out std_ulogic_vector(31 downto 0);
  43         log_rd_data : in std_ulogic_vector(63 downto 0);
  44         log_wr_addr : in std_ulogic_vector(31 downto 0)
  45         );
  46 end entity execute1;
  47
  48 architecture behaviour of execute1 is
  49     type reg_type is record
  50         e : Execute1ToWritebackType;
  51         lr_update : std_ulogic;
  52         next_lr : std_ulogic_vector(63 downto 0);
  53         mul_in_progress : std_ulogic;
  54         div_in_progress : std_ulogic;
  55         cntz_in_progress : std_ulogic;
  56         slow_op_dest : gpr_index_t;
  57         slow_op_rc : std_ulogic;
  58         slow_op_oe : std_ulogic;
  59         slow_op_xerc : xer_common_t;
  60         ldst_nia : std_ulogic_vector(63 downto 0);
  61         log_addr_spr : std_ulogic_vector(31 downto 0);
  62     end record;
  63     constant reg_type_init : reg_type :=
  64         (e => Execute1ToWritebackInit, lr_update => '0',
  65          mul_in_progress => '0', div_in_progress => '0', cntz_in_progress => '0',
  66          slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  67          next_lr => (others => '0'), ldst_nia => (others => '0'), others => (others => '0'));
  68
  69     signal r, rin : reg_type;
  70
  71     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  72
  73     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  74     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  75     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  76     signal rot_sign_ext: std_ulogic;
  77     signal rotator_result: std_ulogic_vector(63 downto 0);
  78     signal rotator_carry: std_ulogic;
  79     signal logical_result: std_ulogic_vector(63 downto 0);
  80     signal countzero_result: std_ulogic_vector(63 downto 0);
  81     signal popcnt_result: std_ulogic_vector(63 downto 0);
  82     signal parity_result: std_ulogic_vector(63 downto 0);
  83
  84     -- multiply signals
  85     signal x_to_multiply: Execute1ToMultiplyType;
  86     signal multiply_to_x: MultiplyToExecute1Type;
  87
  88     -- divider signals
  89     signal x_to_divider: Execute1ToDividerType;
  90     signal divider_to_x: DividerToExecute1Type;
  91
  92     -- signals for logging
  93     signal exception_log : std_ulogic;
  94     signal irq_valid_log : std_ulogic;
  95     signal log_data : std_ulogic_vector(14 downto 0);
  96
  97     type privilege_level is (USER, SUPER);
  98     type op_privilege_array is array(insn_type_t) of privilege_level;
  99     constant op_privilege: op_privilege_array := (
 100         OP_ATTN => SUPER,
 101         OP_MFMSR => SUPER,
 102         OP_MTMSRD => SUPER,
 103         OP_RFID => SUPER,
 104         OP_TLBIE => SUPER,
 105         others => USER
 106         );
 107
 108     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 109         return boolean is
 110     begin
 111         if op_privilege(op) = SUPER then
 112             return true;
 113         elsif op = OP_MFSPR or op = OP_MTSPR then
 114             return insn(20) = '1';
 115         else
 116             return false;
 117         end if;
 118     end;
 119
 120     procedure set_carry(e: inout Execute1ToWritebackType;
 121                         carry32 : in std_ulogic;
 122                         carry : in std_ulogic) is
 123     begin
 124         e.xerc.ca32 := carry32;
 125         e.xerc.ca := carry;
 126         e.write_xerc_enable := '1';
 127     end;
 128
 129     procedure set_ov(e: inout Execute1ToWritebackType;
 130                      ov   : in std_ulogic;
 131                      ov32 : in std_ulogic) is
 132     begin
 133         e.xerc.ov32 := ov32;
 134         e.xerc.ov := ov;
 135         if ov = '1' then
 136             e.xerc.so := '1';
 137         end if;
 138         e.write_xerc_enable := '1';
 139     end;
 140
 141     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 142                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 143     begin
 144         return (ca xor msb_r) and not (msb_a xor msb_b);
 145     end;
 146
 147     function decode_input_carry(ic : carry_in_t;
 148                                 xerc : xer_common_t) return std_ulogic is
 149     begin
 150         case ic is
 151         when ZERO =>
 152             return '0';
 153         when CA =>
 154             return xerc.ca;
 155         when ONE =>
 156             return '1';
 157         end case;
 158     end;
 159
 160     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 161         return std_ulogic_vector is
 162         variable msr_out: std_ulogic_vector(63 downto 0);
 163     begin
 164         -- ISA says this:
 165         --  Defined MSR bits are classified as either full func-
 166         --  tion or partial function. Full function MSR bits are
 167         --  saved in SRR1 or HSRR1 when an interrupt other
 168         --  than a System Call Vectored interrupt occurs and
 169         --  restored by rfscv, rfid, or hrfid, while partial func-
 170         --  tion MSR bits are not saved or restored.
 171         --  Full function MSR bits lie in the range 0:32, 37:41, and
 172         --  48:63, and partial function MSR bits lie in the range
 173         --  33:36 and 42:47. (Note this is IBM bit numbering).
 174         msr_out := (others => '0');
 175         msr_out(63 downto 31) := msr(63 downto 31);
 176         msr_out(26 downto 22) := msr(26 downto 22);
 177         msr_out(15 downto 0)  := msr(15 downto 0);
 178         return msr_out;
 179     end;
 180
 181 begin
 182
 183     rotator_0: entity work.rotator
 184         port map (
 185             rs => c_in,
 186             ra => a_in,
 187             shift => b_in(6 downto 0),
 188             insn => e_in.insn,
 189             is_32bit => e_in.is_32bit,
 190             right_shift => right_shift,
 191             arith => e_in.is_signed,
 192             clear_left => rot_clear_left,
 193             clear_right => rot_clear_right,
 194             sign_ext_rs => rot_sign_ext,
 195             result => rotator_result,
 196             carry_out => rotator_carry
 197             );
 198
 199     logical_0: entity work.logical
 200         port map (
 201             rs => c_in,
 202             rb => b_in,
 203             op => e_in.insn_type,
 204             invert_in => e_in.invert_a,
 205             invert_out => e_in.invert_out,
 206             result => logical_result,
 207             datalen => e_in.data_len,
 208             popcnt => popcnt_result,
 209             parity => parity_result
 210             );
 211
 212     countzero_0: entity work.zero_counter
 213         port map (
 214             clk => clk,
 215             rs => c_in,
 216             count_right => e_in.insn(10),
 217             is_32bit => e_in.is_32bit,
 218             result => countzero_result
 219             );
 220
 221     multiply_0: entity work.multiply
 222         port map (
 223             clk => clk,
 224             m_in => x_to_multiply,
 225             m_out => multiply_to_x
 226             );
 227
 228     divider_0: entity work.divider
 229         port map (
 230             clk => clk,
 231             rst => rst,
 232             d_in => x_to_divider,
 233             d_out => divider_to_x
 234             );
 235
 236     dbg_msr_out <= ctrl.msr;
 237     log_rd_addr <= r.log_addr_spr;
 238
 239     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 240     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 241     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 242
 243     execute1_0: process(clk)
 244     begin
 245         if rising_edge(clk) then
 246             if rst = '1' then
 247                 r <= reg_type_init;
 248                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 249                 ctrl.irq_state <= WRITE_SRR0;
 250             else
 251                 r <= rin;
 252                 ctrl <= ctrl_tmp;
 253                 assert not (r.lr_update = '1' and e_in.valid = '1')
 254                     report "LR update collision with valid in EX1"
 255                     severity failure;
 256                 if r.lr_update = '1' then
 257                     report "LR update to " & to_hstring(r.next_lr);
 258                 end if;
 259             end if;
 260         end if;
 261     end process;
 262
 263     execute1_1: process(all)
 264         variable v : reg_type;
 265         variable a_inv : std_ulogic_vector(63 downto 0);
 266         variable result : std_ulogic_vector(63 downto 0);
 267         variable newcrf : std_ulogic_vector(3 downto 0);
 268         variable result_with_carry : std_ulogic_vector(64 downto 0);
 269         variable result_en : std_ulogic;
 270         variable crnum : crnum_t;
 271         variable crbit : integer range 0 to 31;
 272         variable scrnum : crnum_t;
 273         variable lo, hi : integer;
 274         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 275         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 276         variable bo, bi : std_ulogic_vector(4 downto 0);
 277         variable bf, bfa : std_ulogic_vector(2 downto 0);
 278         variable cr_op : std_ulogic_vector(9 downto 0);
 279         variable cr_operands : std_ulogic_vector(1 downto 0);
 280         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 281         variable btnum, banum, bbnum : integer range 0 to 31;
 282         variable crresult : std_ulogic;
 283         variable l : std_ulogic;
 284         variable next_nia : std_ulogic_vector(63 downto 0);
 285         variable carry_32, carry_64 : std_ulogic;
 286         variable sign1, sign2 : std_ulogic;
 287         variable abs1, abs2 : signed(63 downto 0);
 288         variable overflow : std_ulogic;
 289         variable negative : std_ulogic;
 290         variable zerohi, zerolo : std_ulogic;
 291         variable msb_a, msb_b : std_ulogic;
 292         variable a_lt : std_ulogic;
 293         variable lv : Execute1ToLoadstore1Type;
 294         variable irq_valid : std_ulogic;
 295         variable exception : std_ulogic;
 296         variable exception_nextpc : std_ulogic;
 297         variable trapval : std_ulogic_vector(4 downto 0);
 298         variable illegal : std_ulogic;
 299     begin
 300         result := (others => '0');
 301         result_with_carry := (others => '0');
 302         result_en := '0';
 303         newcrf := (others => '0');
 304
 305         v := r;
 306         v.e := Execute1ToWritebackInit;
 307         lv := Execute1ToLoadstore1Init;
 308
 309         -- XER forwarding. To avoid having to track XER hazards, we
 310         -- use the previously latched value.
 311         --
 312         -- If the XER was modified by a multiply or a divide, those are
 313         -- single issue, we'll get the up to date value from decode2 from
 314         -- the register file.
 315         --
 316         -- If it was modified by an instruction older than the previous
 317         -- one in EX1, it will have also hit writeback and will be up
 318         -- to date in decode2.
 319         --
 320         -- That leaves us with the case where it was updated by the previous
 321         -- instruction in EX1. In that case, we can forward it back here.
 322         --
 323         -- This will break if we allow pipelining of multiply and divide,
 324         -- but ideally, those should go via EX1 anyway and run as a state
 325         -- machine from here.
 326         --
 327         -- One additional hazard to beware of is an XER:SO modifying instruction
 328         -- in EX1 followed immediately by a store conditional. Due to our
 329         -- writeback latency, the store will go down the LSU with the previous
 330         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 331         --
 332         -- We will need to handle that if we ever make stcx. not single issue
 333         --
 334         -- We always pass a valid XER value downto writeback even when
 335         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 336         -- to work for RC instructions.
 337         --
 338         if r.e.write_xerc_enable = '1' then
 339             v.e.xerc := r.e.xerc;
 340         else
 341             v.e.xerc := e_in.xerc;
 342         end if;
 343
 344         v.lr_update := '0';
 345         v.mul_in_progress := '0';
 346         v.div_in_progress := '0';
 347         v.cntz_in_progress := '0';
 348
 349         -- signals to multiply unit
 350         x_to_multiply <= Execute1ToMultiplyInit;
 351         x_to_multiply.insn_type <= e_in.insn_type;
 352         x_to_multiply.is_32bit <= e_in.is_32bit;
 353
 354         if e_in.is_32bit = '1' then
 355             if e_in.is_signed = '1' then
 356                 x_to_multiply.data1 <= (others => a_in(31));
 357                 x_to_multiply.data1(31 downto 0) <= a_in(31 downto 0);
 358                 x_to_multiply.data2 <= (others => b_in(31));
 359                 x_to_multiply.data2(31 downto 0) <= b_in(31 downto 0);
 360             else
 361                 x_to_multiply.data1 <= '0' & x"00000000" & a_in(31 downto 0);
 362                 x_to_multiply.data2 <= '0' & x"00000000" & b_in(31 downto 0);
 363             end if;
 364         else
 365             if e_in.is_signed = '1' then
 366                 x_to_multiply.data1 <= a_in(63) & a_in;
 367                 x_to_multiply.data2 <= b_in(63) & b_in;
 368             else
 369                 x_to_multiply.data1 <= '0' & a_in;
 370                 x_to_multiply.data2 <= '0' & b_in;
 371             end if;
 372         end if;
 373
 374         -- signals to divide unit
 375         sign1 := '0';
 376         sign2 := '0';
 377         if e_in.is_signed = '1' then
 378             if e_in.is_32bit = '1' then
 379                 sign1 := a_in(31);
 380                 sign2 := b_in(31);
 381             else
 382                 sign1 := a_in(63);
 383                 sign2 := b_in(63);
 384             end if;
 385         end if;
 386         -- take absolute values
 387         if sign1 = '0' then
 388             abs1 := signed(a_in);
 389         else
 390             abs1 := - signed(a_in);
 391         end if;
 392         if sign2 = '0' then
 393             abs2 := signed(b_in);
 394         else
 395             abs2 := - signed(b_in);
 396         end if;
 397
 398         x_to_divider <= Execute1ToDividerInit;
 399         x_to_divider.is_signed <= e_in.is_signed;
 400         x_to_divider.is_32bit <= e_in.is_32bit;
 401         if e_in.insn_type = OP_MOD then
 402             x_to_divider.is_modulus <= '1';
 403         end if;
 404         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 405         if e_in.is_32bit = '0' then
 406             -- 64-bit forms
 407             if e_in.insn_type = OP_DIVE then
 408                 x_to_divider.is_extended <= '1';
 409             end if;
 410             x_to_divider.dividend <= std_ulogic_vector(abs1);
 411             x_to_divider.divisor <= std_ulogic_vector(abs2);
 412         else
 413             -- 32-bit forms
 414             x_to_divider.is_extended <= '0';
 415             if e_in.insn_type = OP_DIVE then   -- extended forms
 416                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 417             else
 418                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 419             end if;
 420             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 421         end if;
 422
 423         ctrl_tmp <= ctrl;
 424         -- FIXME: run at 512MHz not core freq
 425         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 426         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 427
 428         irq_valid := '0';
 429         if ctrl.msr(MSR_EE) = '1' then
 430             if ctrl.dec(63) = '1' then
 431                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#900#, 64));
 432                 report "IRQ valid: DEC";
 433                 irq_valid := '1';
 434             elsif ext_irq_in = '1' then
 435                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#500#, 64));
 436                 report "IRQ valid: External";
 437                 irq_valid := '1';
 438             end if;
 439         end if;
 440
 441         terminate_out <= '0';
 442         icache_inval <= '0';
 443         stall_out <= '0';
 444         f_out <= Execute1ToFetch1TypeInit;
 445         -- send MSR[IR] and ~MSR[PR] up to fetch1
 446         f_out.virt_mode <= ctrl.msr(MSR_IR);
 447         f_out.priv_mode <= not ctrl.msr(MSR_PR);
 448
 449         -- Next insn adder used in a couple of places
 450         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 451
 452         -- rotator control signals
 453         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 454         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 455         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 456         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 457
 458         ctrl_tmp.irq_state <= WRITE_SRR0;
 459         exception := '0';
 460         illegal := '0';
 461         exception_nextpc := '0';
 462         v.e.exc_write_enable := '0';
 463         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 464         v.e.exc_write_data := e_in.nia;
 465
 466         if ctrl.irq_state = WRITE_SRR1 then
 467             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 468             v.e.exc_write_data := ctrl.srr1;
 469             v.e.exc_write_enable := '1';
 470             ctrl_tmp.msr(MSR_SF) <= '1';
 471             ctrl_tmp.msr(MSR_EE) <= '0';
 472             ctrl_tmp.msr(MSR_PR) <= '0';
 473             ctrl_tmp.msr(MSR_IR) <= '0';
 474             ctrl_tmp.msr(MSR_DR) <= '0';
 475             ctrl_tmp.msr(MSR_RI) <= '0';
 476             ctrl_tmp.msr(MSR_LE) <= '1';
 477             f_out.redirect <= '1';
 478             f_out.virt_mode <= '0';
 479             f_out.priv_mode <= '1';
 480             f_out.redirect_nia <= ctrl.irq_nia;
 481             v.e.valid := e_in.valid;
 482             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 483
 484         elsif irq_valid = '1' and e_in.valid = '1' then
 485             -- we need two cycles to write srr0 and 1
 486             -- will need more when we have to write HEIR
 487             -- Don't deliver the interrupt until we have a valid instruction
 488             -- coming in, so we have a valid NIA to put in SRR0.
 489             exception := '1';
 490             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 491
 492         elsif e_in.valid = '1' and ctrl.msr(MSR_PR) = '1' and
 493             instr_is_privileged(e_in.insn_type, e_in.insn) then
 494             -- generate a program interrupt
 495             exception := '1';
 496             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 497             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 498             -- set bit 45 to indicate privileged instruction type interrupt
 499             ctrl_tmp.srr1(63 - 45) <= '1';
 500             report "privileged instruction";
 501
 502         elsif e_in.valid = '1' and e_in.unit = ALU then
 503
 504             report "execute nia " & to_hstring(e_in.nia);
 505
 506             v.e.valid := '1';
 507             v.e.write_reg := e_in.write_reg;
 508             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 509             v.slow_op_rc := e_in.rc;
 510             v.slow_op_oe := e_in.oe;
 511             v.slow_op_xerc := v.e.xerc;
 512
 513             case_0: case e_in.insn_type is
 514
 515             when OP_ILLEGAL =>
 516                 -- we need two cycles to write srr0 and 1
 517                 -- will need more when we have to write HEIR
 518                 illegal := '1';
 519             when OP_SC =>
 520                 -- check bit 1 of the instruction is 1 so we know this is sc;
 521                 -- 0 would mean scv, so generate an illegal instruction interrupt
 522                 -- we need two cycles to write srr0 and 1
 523                 if e_in.insn(1) = '1' then
 524                     exception := '1';
 525                     exception_nextpc := '1';
 526                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
 527                     ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 528                     report "sc";
 529                 else
 530                     illegal := '1';
 531                 end if;
 532             when OP_ATTN =>
 533                 -- check bits 1-10 of the instruction to make sure it's attn
 534                 -- if not then it is illegal
 535                 if e_in.insn(10 downto 1) = "0100000000" then
 536                     terminate_out <= '1';
 537                     report "ATTN";
 538                 else
 539                     illegal := '1';
 540                 end if;
 541             when OP_NOP =>
 542                 -- Do nothing
 543             when OP_ADD | OP_CMP | OP_TRAP =>
 544                 if e_in.invert_a = '0' then
 545                     a_inv := a_in;
 546                 else
 547                     a_inv := not a_in;
 548                 end if;
 549                 result_with_carry := ppc_adde(a_inv, b_in,
 550                                               decode_input_carry(e_in.input_carry, v.e.xerc));
 551                 result := result_with_carry(63 downto 0);
 552                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 553                 carry_64 := result_with_carry(64);
 554                 if e_in.insn_type = OP_ADD then
 555                     if e_in.output_carry = '1' then
 556                         set_carry(v.e, carry_32, carry_64);
 557                     end if;
 558                     if e_in.oe = '1' then
 559                         set_ov(v.e,
 560                                calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
 561                                calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
 562                     end if;
 563                     result_en := '1';
 564                 else
 565                     -- trap, CMP and CMPL instructions
 566                     -- Note, we have done RB - RA, not RA - RB
 567                     if e_in.insn_type = OP_CMP then
 568                         l := insn_l(e_in.insn);
 569                     else
 570                         l := not e_in.is_32bit;
 571                     end if;
 572                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 573                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 574                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 575                         -- values are equal
 576                         trapval := "00100";
 577                     else
 578                         if l = '1' then
 579                             -- 64-bit comparison
 580                             msb_a := a_in(63);
 581                             msb_b := b_in(63);
 582                         else
 583                             -- 32-bit comparison
 584                             msb_a := a_in(31);
 585                             msb_b := b_in(31);
 586                         end if;
 587                         if msb_a /= msb_b then
 588                             -- Subtraction might overflow, but
 589                             -- comparison is clear from MSB difference.
 590                             -- for signed, 0 is greater; for unsigned, 1 is greater
 591                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 592                         else
 593                             -- Subtraction cannot overflow since MSBs are equal.
 594                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 595                             a_lt := (not l and carry_32) or (l and carry_64);
 596                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 597                         end if;
 598                     end if;
 599                     if e_in.insn_type = OP_CMP then
 600                         if e_in.is_signed = '1' then
 601                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 602                         else
 603                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 604                         end if;
 605                         bf := insn_bf(e_in.insn);
 606                         crnum := to_integer(unsigned(bf));
 607                         v.e.write_cr_enable := '1';
 608                         v.e.write_cr_mask := num_to_fxm(crnum);
 609                         for i in 0 to 7 loop
 610                             lo := i*4;
 611                             hi := lo + 3;
 612                             v.e.write_cr_data(hi downto lo) := newcrf;
 613                         end loop;
 614                     else
 615                         -- trap instructions (tw, twi, td, tdi)
 616                         if or (trapval and insn_to(e_in.insn)) = '1' then
 617                             -- generate trap-type program interrupt
 618                             exception := '1';
 619                             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 620                             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 621                             -- set bit 46 to say trap occurred
 622                             ctrl_tmp.srr1(63 - 46) <= '1';
 623                             report "trap";
 624                         end if;
 625                     end if;
 626                 end if;
 627             when OP_AND | OP_OR | OP_XOR =>
 628                 result := logical_result;
 629                 result_en := '1';
 630             when OP_B =>
 631                 f_out.redirect <= '1';
 632                 if (insn_aa(e_in.insn)) then
 633                     f_out.redirect_nia <= b_in;
 634                 else
 635                     f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 636                 end if;
 637             when OP_BC =>
 638                 -- read_data1 is CTR
 639                 bo := insn_bo(e_in.insn);
 640                 bi := insn_bi(e_in.insn);
 641                 if bo(4-2) = '0' then
 642                     result := std_ulogic_vector(unsigned(a_in) - 1);
 643                     result_en := '1';
 644                     v.e.write_reg := fast_spr_num(SPR_CTR);
 645                 end if;
 646                 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
 647                     f_out.redirect <= '1';
 648                     if (insn_aa(e_in.insn)) then
 649                         f_out.redirect_nia <= b_in;
 650                     else
 651                         f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 652                     end if;
 653                 end if;
 654             when OP_BCREG =>
 655                 -- read_data1 is CTR
 656                 -- read_data2 is target register (CTR, LR or TAR)
 657                 bo := insn_bo(e_in.insn);
 658                 bi := insn_bi(e_in.insn);
 659                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 660                     result := std_ulogic_vector(unsigned(a_in) - 1);
 661                     result_en := '1';
 662                     v.e.write_reg := fast_spr_num(SPR_CTR);
 663                 end if;
 664                 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
 665                     f_out.redirect <= '1';
 666                     f_out.redirect_nia <= b_in(63 downto 2) & "00";
 667                 end if;
 668
 669             when OP_RFID =>
 670                 f_out.redirect <= '1';
 671                 f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
 672                 f_out.priv_mode <= not b_in(MSR_PR);
 673                 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
 674                 -- Can't use msr_copy here because the partial function MSR
 675                 -- bits should be left unchanged, not zeroed.
 676                 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
 677                 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
 678                 ctrl_tmp.msr(15 downto 0)  <= b_in(15 downto 0);
 679                 if b_in(MSR_PR) = '1' then
 680                     ctrl_tmp.msr(MSR_EE) <= '1';
 681                     ctrl_tmp.msr(MSR_IR) <= '1';
 682                     ctrl_tmp.msr(MSR_DR) <= '1';
 683                 end if;
 684
 685             when OP_CMPB =>
 686                 result := ppc_cmpb(c_in, b_in);
 687                 result_en := '1';
 688             when OP_CNTZ =>
 689                 v.e.valid := '0';
 690                 v.cntz_in_progress := '1';
 691                 stall_out <= '1';
 692             when OP_EXTS =>
 693                 -- note data_len is a 1-hot encoding
 694                 negative := (e_in.data_len(0) and c_in(7)) or
 695                             (e_in.data_len(1) and c_in(15)) or
 696                             (e_in.data_len(2) and c_in(31));
 697                 result := (others => negative);
 698                 if e_in.data_len(2) = '1' then
 699                     result(31 downto 16) := c_in(31 downto 16);
 700                 end if;
 701                 if e_in.data_len(2) = '1' or e_in.data_len(1) = '1' then
 702                     result(15 downto 8) := c_in(15 downto 8);
 703                 end if;
 704                 result(7 downto 0) := c_in(7 downto 0);
 705                 result_en := '1';
 706             when OP_ISEL =>
 707                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 708                 if e_in.cr(31-crbit) = '1' then
 709                     result := a_in;
 710                 else
 711                     result := b_in;
 712                 end if;
 713                 result_en := '1';
 714             when OP_CROP =>
 715                 cr_op := insn_cr(e_in.insn);
 716                 report "CR OP " & to_hstring(cr_op);
 717                 if cr_op(0) = '0' then -- MCRF
 718                     bf := insn_bf(e_in.insn);
 719                     bfa := insn_bfa(e_in.insn);
 720                     v.e.write_cr_enable := '1';
 721                     crnum := to_integer(unsigned(bf));
 722                     scrnum := to_integer(unsigned(bfa));
 723                     v.e.write_cr_mask := num_to_fxm(crnum);
 724                     for i in 0 to 7 loop
 725                         lo := (7-i)*4;
 726                         hi := lo + 3;
 727                         if i = scrnum then
 728                             newcrf := e_in.cr(hi downto lo);
 729                         end if;
 730                     end loop;
 731                     for i in 0 to 7 loop
 732                         lo := i*4;
 733                         hi := lo + 3;
 734                         v.e.write_cr_data(hi downto lo) := newcrf;
 735                     end loop;
 736                 else
 737                     v.e.write_cr_enable := '1';
 738                     bt := insn_bt(e_in.insn);
 739                     ba := insn_ba(e_in.insn);
 740                     bb := insn_bb(e_in.insn);
 741                     btnum := 31 - to_integer(unsigned(bt));
 742                     banum := 31 - to_integer(unsigned(ba));
 743                     bbnum := 31 - to_integer(unsigned(bb));
 744                     -- Bits 5-8 of cr_op give the truth table of the requested
 745                     -- logical operation
 746                     cr_operands := e_in.cr(banum) & e_in.cr(bbnum);
 747                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 748                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 749                     for i in 0 to 31 loop
 750                         if i = btnum then
 751                             v.e.write_cr_data(i) := crresult;
 752                         else
 753                             v.e.write_cr_data(i) := e_in.cr(i);
 754                         end if;
 755                     end loop;
 756                 end if;
 757             when OP_MFMSR =>
 758                 result := ctrl.msr;
 759                 result_en := '1';
 760             when OP_MFSPR =>
 761                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 762                     "=" & to_hstring(a_in);
 763                 result_en := '1';
 764                 if is_fast_spr(e_in.read_reg1) then
 765                     result := a_in;
 766                     if decode_spr_num(e_in.insn) = SPR_XER then
 767                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 768                         result(63 downto 32) := (others => '0');
 769                         result(63-32) := v.e.xerc.so;
 770                         result(63-33) := v.e.xerc.ov;
 771                         result(63-34) := v.e.xerc.ca;
 772                         result(63-35 downto 63-43) := "000000000";
 773                         result(63-44) := v.e.xerc.ov32;
 774                         result(63-45) := v.e.xerc.ca32;
 775                     end if;
 776                 else
 777                     case decode_spr_num(e_in.insn) is
 778                     when SPR_TB =>
 779                         result := ctrl.tb;
 780                     when SPR_DEC =>
 781                         result := ctrl.dec;
 782                     when 724 =>     -- LOG_ADDR SPR
 783                         result := log_wr_addr & r.log_addr_spr;
 784                     when 725 =>     -- LOG_DATA SPR
 785                         result := log_rd_data;
 786                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 787                     when others =>
 788                         -- mfspr from unimplemented SPRs should be a nop in
 789                         -- supervisor mode and a program interrupt for user mode
 790                         result := c_in;
 791                         if ctrl.msr(MSR_PR) = '1' then
 792                             illegal := '1';
 793                         end if;
 794                     end case;
 795                 end if;
 796             when OP_MFCR =>
 797                 if e_in.insn(20) = '0' then
 798                     -- mfcr
 799                     result := x"00000000" & e_in.cr;
 800                 else
 801                     -- mfocrf
 802                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 803                     result := (others => '0');
 804                     for i in 0 to 7 loop
 805                         lo := (7-i)*4;
 806                         hi := lo + 3;
 807                         if crnum = i then
 808                             result(hi downto lo) := e_in.cr(hi downto lo);
 809                         end if;
 810                     end loop;
 811                 end if;
 812                 result_en := '1';
 813             when OP_MTCRF =>
 814                 v.e.write_cr_enable := '1';
 815                 if e_in.insn(20) = '0' then
 816                     -- mtcrf
 817                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 818                 else
 819                     -- mtocrf: We require one hot priority encoding here
 820                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 821                     v.e.write_cr_mask := num_to_fxm(crnum);
 822                 end if;
 823                 v.e.write_cr_data := c_in(31 downto 0);
 824             when OP_MTMSRD =>
 825                 if e_in.insn(16) = '1' then
 826                     -- just update EE and RI
 827                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 828                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 829                 else
 830                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 831                     -- and 63 (LE) (IBM bit numbering)
 832                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 833                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 834                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 835                     if c_in(MSR_PR) = '1' then
 836                         ctrl_tmp.msr(MSR_EE) <= '1';
 837                         ctrl_tmp.msr(MSR_IR) <= '1';
 838                         ctrl_tmp.msr(MSR_DR) <= '1';
 839                     end if;
 840                 end if;
 841             when OP_MTSPR =>
 842                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 843                     "=" & to_hstring(c_in);
 844                 if is_fast_spr(e_in.write_reg) then
 845                     result := c_in;
 846                     result_en := '1';
 847                     if decode_spr_num(e_in.insn) = SPR_XER then
 848                         v.e.xerc.so := c_in(63-32);
 849                         v.e.xerc.ov := c_in(63-33);
 850                         v.e.xerc.ca := c_in(63-34);
 851                         v.e.xerc.ov32 := c_in(63-44);
 852                         v.e.xerc.ca32 := c_in(63-45);
 853                         v.e.write_xerc_enable := '1';
 854                     end if;
 855                 else
 856                     -- slow spr
 857                     case decode_spr_num(e_in.insn) is
 858                     when SPR_DEC =>
 859                         ctrl_tmp.dec <= c_in;
 860                     when 724 =>     -- LOG_ADDR SPR
 861                         v.log_addr_spr := c_in(31 downto 0);
 862                     when others =>
 863                         -- mtspr to unimplemented SPRs should be a nop in
 864                         -- supervisor mode and a program interrupt for user mode
 865                         if ctrl.msr(MSR_PR) = '1' then
 866                             illegal := '1';
 867                         end if;
 868                     end case;
 869                 end if;
 870             when OP_POPCNT =>
 871                 result := popcnt_result;
 872                 result_en := '1';
 873             when OP_PRTY =>
 874                 result := parity_result;
 875                 result_en := '1';
 876             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
 877                 result := rotator_result;
 878                 if e_in.output_carry = '1' then
 879                     set_carry(v.e, rotator_carry, rotator_carry);
 880                 end if;
 881                 result_en := '1';
 882
 883             when OP_ISYNC =>
 884                 f_out.redirect <= '1';
 885                 f_out.redirect_nia <= next_nia;
 886
 887             when OP_ICBI =>
 888                 icache_inval <= '1';
 889
 890             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
 891                 v.e.valid := '0';
 892                 v.mul_in_progress := '1';
 893                 stall_out <= '1';
 894                 x_to_multiply.valid <= '1';
 895
 896             when OP_DIV | OP_DIVE | OP_MOD =>
 897                 v.e.valid := '0';
 898                 v.div_in_progress := '1';
 899                 stall_out <= '1';
 900                 x_to_divider.valid <= '1';
 901
 902             when others =>
 903                 terminate_out <= '1';
 904                 report "illegal";
 905             end case;
 906
 907             v.e.rc := e_in.rc and e_in.valid;
 908
 909             -- Update LR on the next cycle after a branch link
 910             --
 911             -- WARNING: The LR update isn't tracked by our hazard tracker. This
 912             --          will work (well I hope) because it only happens on branches
 913             --          which will flush all decoded instructions. By the time
 914             --          fetch catches up, we'll have the new LR. This will
 915             --          *not* work properly however if we have a branch predictor,
 916             --          in which case the solution would probably be to keep a
 917             --          local cache of the updated LR in execute1 (flushed on
 918             --          exceptions) that is used instead of the value from
 919             --          decode when its content is valid.
 920             if e_in.lr = '1' then
 921                 v.lr_update := '1';
 922                 v.next_lr := next_nia;
 923                 v.e.valid := '0';
 924                 report "Delayed LR update to " & to_hstring(next_nia);
 925                 stall_out <= '1';
 926             end if;
 927
 928         elsif e_in.valid = '1' then
 929             -- instruction for other units, i.e. LDST
 930             v.ldst_nia := e_in.nia;
 931             v.e.valid := '0';
 932             if e_in.unit = LDST then
 933                 lv.valid := '1';
 934             end if;
 935
 936         elsif r.lr_update = '1' then
 937             result_en := '1';
 938             result := r.next_lr;
 939             v.e.write_reg := fast_spr_num(SPR_LR);
 940             v.e.valid := '1';
 941         elsif r.cntz_in_progress = '1' then
 942             -- cnt[lt]z always takes two cycles
 943             result := countzero_result;
 944             result_en := '1';
 945             v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 946             v.e.rc := v.slow_op_rc;
 947             v.e.xerc := v.slow_op_xerc;
 948             v.e.valid := '1';
 949         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
 950             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
 951                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
 952                 if r.mul_in_progress = '1' then
 953                     result := multiply_to_x.write_reg_data;
 954                     overflow := multiply_to_x.overflow;
 955                 else
 956                     result := divider_to_x.write_reg_data;
 957                     overflow := divider_to_x.overflow;
 958                 end if;
 959                 result_en := '1';
 960                 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 961                 v.e.rc := v.slow_op_rc;
 962                 v.e.xerc := v.slow_op_xerc;
 963                 v.e.write_xerc_enable := v.slow_op_oe;
 964                 -- We must test oe because the RC update code in writeback
 965                 -- will use the xerc value to set CR0:SO so we must not clobber
 966                 -- xerc if OE wasn't set.
 967                 if v.slow_op_oe = '1' then
 968                     v.e.xerc.ov := overflow;
 969                     v.e.xerc.ov32 := overflow;
 970                     v.e.xerc.so := v.slow_op_xerc.so or overflow;
 971                 end if;
 972                 v.e.valid := '1';
 973             else
 974                 stall_out <= '1';
 975                 v.mul_in_progress := r.mul_in_progress;
 976                 v.div_in_progress := r.div_in_progress;
 977             end if;
 978         end if;
 979
 980         if illegal = '1' then
 981             exception := '1';
 982             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 983             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 984             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
 985             -- set bit 44 to indicate we have an illegal
 986             ctrl_tmp.srr1(63 - 44) <= '1';
 987             report "illegal";
 988         end if;
 989         if exception = '1' then
 990             v.e.exc_write_enable := '1';
 991             if exception_nextpc = '1' then
 992                 v.e.exc_write_data := next_nia;
 993             end if;
 994             ctrl_tmp.irq_state <= WRITE_SRR1;
 995             v.e.valid := '1';
 996         end if;
 997
 998         v.e.write_data := result;
 999         v.e.write_enable := result_en;
1000
1001         -- generate DSI or DSegI for load/store exceptions
1002         -- or ISI or ISegI for instruction fetch exceptions
1003         if l_in.exception = '1' then
1004             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
1005             if l_in.instr_fault = '0' then
1006                 if l_in.segment_fault = '0' then
1007                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#300#, 64));
1008                 else
1009                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#380#, 64));
1010                 end if;
1011             else
1012                 if l_in.segment_fault = '0' then
1013                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1014                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1015                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1016                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1017                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#400#, 64));
1018                 else
1019                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#480#, 64));
1020                 end if;
1021             end if;
1022             v.e.exc_write_enable := '1';
1023             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1024             v.e.exc_write_data := r.ldst_nia;
1025             report "ldst exception writing srr0=" & to_hstring(r.ldst_nia);
1026             ctrl_tmp.irq_state <= WRITE_SRR1;
1027             v.e.valid := '1';   -- complete the original load or store
1028         end if;
1029
1030         -- Outputs to loadstore1 (async)
1031         lv.op := e_in.insn_type;
1032         lv.nia := e_in.nia;
1033         lv.addr1 := a_in;
1034         lv.addr2 := b_in;
1035         lv.data := c_in;
1036         lv.write_reg := gspr_to_gpr(e_in.write_reg);
1037         lv.length := e_in.data_len;
1038         lv.byte_reverse := e_in.byte_reverse;
1039         lv.sign_extend := e_in.sign_extend;
1040         lv.update := e_in.update;
1041         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1042         lv.xerc := v.e.xerc;
1043         lv.reserve := e_in.reserve;
1044         lv.rc := e_in.rc;
1045         lv.insn := e_in.insn;
1046         -- decode l*cix and st*cix instructions here
1047         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1048             e_in.insn(5 downto 1) = "10101" then
1049             lv.ci := '1';
1050         end if;
1051         lv.virt_mode := ctrl.msr(MSR_DR);
1052         lv.priv_mode := not ctrl.msr(MSR_PR);
1053
1054         -- Update registers
1055         rin <= v;
1056
1057         -- update outputs
1058         --f_out <= r.f;
1059         l_out <= lv;
1060         e_out <= r.e;
1061         flush_out <= f_out.redirect;
1062
1063         exception_log <= exception;
1064         irq_valid_log <= irq_valid;
1065     end process;
1066
1067     ex1_log : process(clk)
1068     begin
1069         if rising_edge(clk) then
1070             log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1071                         ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1072                         exception_log &
1073                         irq_valid_log &
1074                         std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1075                         "000" &
1076                         r.e.write_enable &
1077                         r.e.valid &
1078                         f_out.redirect &
1079                         stall_out &
1080                         flush_out;
1081         end if;
1082     end process;
1083     log_out <= log_data;
1084 end architecture behaviour;