execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true
  16         );
  17     port (
  18         clk   : in std_ulogic;
  19         rst   : in std_ulogic;
  20
  21         -- asynchronous
  22         flush_out : out std_ulogic;
  23         stall_out : out std_ulogic;
  24
  25         e_in  : in Decode2ToExecute1Type;
  26
  27         i_in : in XicsToExecute1Type;
  28
  29         -- asynchronous
  30         l_out : out Execute1ToLoadstore1Type;
  31         f_out : out Execute1ToFetch1Type;
  32
  33         e_out : out Execute1ToWritebackType;
  34
  35         icache_inval : out std_ulogic;
  36         terminate_out : out std_ulogic
  37         );
  38 end entity execute1;
  39
  40 architecture behaviour of execute1 is
  41     type reg_type is record
  42         e : Execute1ToWritebackType;
  43         lr_update : std_ulogic;
  44         next_lr : std_ulogic_vector(63 downto 0);
  45         mul_in_progress : std_ulogic;
  46         div_in_progress : std_ulogic;
  47         cntz_in_progress : std_ulogic;
  48         slow_op_dest : gpr_index_t;
  49         slow_op_rc : std_ulogic;
  50         slow_op_oe : std_ulogic;
  51         slow_op_xerc : xer_common_t;
  52     end record;
  53     constant reg_type_init : reg_type :=
  54         (e => Execute1ToWritebackInit, lr_update => '0',
  55          mul_in_progress => '0', div_in_progress => '0', cntz_in_progress => '0',
  56          slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  57          others => (others => '0'));
  58
  59     signal r, rin : reg_type;
  60
  61     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  62
  63     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  64     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  65     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  66     signal rot_sign_ext: std_ulogic;
  67     signal rotator_result: std_ulogic_vector(63 downto 0);
  68     signal rotator_carry: std_ulogic;
  69     signal logical_result: std_ulogic_vector(63 downto 0);
  70     signal countzero_result: std_ulogic_vector(63 downto 0);
  71     signal popcnt_result: std_ulogic_vector(63 downto 0);
  72     signal parity_result: std_ulogic_vector(63 downto 0);
  73
  74     -- multiply signals
  75     signal x_to_multiply: Execute1ToMultiplyType;
  76     signal multiply_to_x: MultiplyToExecute1Type;
  77
  78     -- divider signals
  79     signal x_to_divider: Execute1ToDividerType;
  80     signal divider_to_x: DividerToExecute1Type;
  81
  82     type privilege_level is (USER, SUPER);
  83     type op_privilege_array is array(insn_type_t) of privilege_level;
  84     constant op_privilege: op_privilege_array := (
  85         OP_ATTN => SUPER,
  86         OP_MFMSR => SUPER,
  87         OP_MTMSRD => SUPER,
  88         OP_RFID => SUPER,
  89         others => USER
  90         );
  91
  92     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
  93         return boolean is
  94     begin
  95         if op_privilege(op) = SUPER then
  96             return true;
  97         elsif op = OP_MFSPR or op = OP_MTSPR then
  98             return insn(20) = '1';
  99         else
 100             return false;
 101         end if;
 102     end;
 103
 104     procedure set_carry(e: inout Execute1ToWritebackType;
 105                         carry32 : in std_ulogic;
 106                         carry : in std_ulogic) is
 107     begin
 108         e.xerc.ca32 := carry32;
 109         e.xerc.ca := carry;
 110         e.write_xerc_enable := '1';
 111     end;
 112
 113     procedure set_ov(e: inout Execute1ToWritebackType;
 114                      ov   : in std_ulogic;
 115                      ov32 : in std_ulogic) is
 116     begin
 117         e.xerc.ov32 := ov32;
 118         e.xerc.ov := ov;
 119         if ov = '1' then
 120             e.xerc.so := '1';
 121         end if;
 122         e.write_xerc_enable := '1';
 123     end;
 124
 125     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 126                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 127     begin
 128         return (ca xor msb_r) and not (msb_a xor msb_b);
 129     end;
 130
 131     function decode_input_carry(ic : carry_in_t;
 132                                 xerc : xer_common_t) return std_ulogic is
 133     begin
 134         case ic is
 135         when ZERO =>
 136             return '0';
 137         when CA =>
 138             return xerc.ca;
 139         when ONE =>
 140             return '1';
 141         end case;
 142     end;
 143
 144     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 145         return std_ulogic_vector is
 146         variable msr_out: std_ulogic_vector(63 downto 0);
 147     begin
 148         -- ISA says this:
 149         --  Defined MSR bits are classified as either full func-
 150         --  tion or partial function. Full function MSR bits are
 151         --  saved in SRR1 or HSRR1 when an interrupt other
 152         --  than a System Call Vectored interrupt occurs and
 153         --  restored by rfscv, rfid, or hrfid, while partial func-
 154         --  tion MSR bits are not saved or restored.
 155         --  Full function MSR bits lie in the range 0:32, 37:41, and
 156         --  48:63, and partial function MSR bits lie in the range
 157         --  33:36 and 42:47. (Note this is IBM bit numbering).
 158         msr_out := (others => '0');
 159         msr_out(63 downto 31) := msr(63 downto 31);
 160         msr_out(26 downto 22) := msr(26 downto 22);
 161         msr_out(15 downto 0)  := msr(15 downto 0);
 162         return msr_out;
 163     end;
 164
 165 begin
 166
 167     rotator_0: entity work.rotator
 168         port map (
 169             rs => c_in,
 170             ra => a_in,
 171             shift => b_in(6 downto 0),
 172             insn => e_in.insn,
 173             is_32bit => e_in.is_32bit,
 174             right_shift => right_shift,
 175             arith => e_in.is_signed,
 176             clear_left => rot_clear_left,
 177             clear_right => rot_clear_right,
 178             sign_ext_rs => rot_sign_ext,
 179             result => rotator_result,
 180             carry_out => rotator_carry
 181             );
 182
 183     logical_0: entity work.logical
 184         port map (
 185             rs => c_in,
 186             rb => b_in,
 187             op => e_in.insn_type,
 188             invert_in => e_in.invert_a,
 189             invert_out => e_in.invert_out,
 190             result => logical_result,
 191             datalen => e_in.data_len,
 192             popcnt => popcnt_result,
 193             parity => parity_result
 194             );
 195
 196     countzero_0: entity work.zero_counter
 197         port map (
 198             clk => clk,
 199             rs => c_in,
 200             count_right => e_in.insn(10),
 201             is_32bit => e_in.is_32bit,
 202             result => countzero_result
 203             );
 204
 205     multiply_0: entity work.multiply
 206         port map (
 207             clk => clk,
 208             m_in => x_to_multiply,
 209             m_out => multiply_to_x
 210             );
 211
 212     divider_0: entity work.divider
 213         port map (
 214             clk => clk,
 215             rst => rst,
 216             d_in => x_to_divider,
 217             d_out => divider_to_x
 218             );
 219
 220     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 221     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 222     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 223
 224     execute1_0: process(clk)
 225     begin
 226         if rising_edge(clk) then
 227             if rst = '1' then
 228                 r <= reg_type_init;
 229                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 230                 ctrl.irq_state <= WRITE_SRR0;
 231             else
 232                 r <= rin;
 233                 ctrl <= ctrl_tmp;
 234                 assert not (r.lr_update = '1' and e_in.valid = '1')
 235                     report "LR update collision with valid in EX1"
 236                     severity failure;
 237                 if r.lr_update = '1' then
 238                     report "LR update to " & to_hstring(r.next_lr);
 239                 end if;
 240             end if;
 241         end if;
 242     end process;
 243
 244     execute1_1: process(all)
 245         variable v : reg_type;
 246         variable a_inv : std_ulogic_vector(63 downto 0);
 247         variable result : std_ulogic_vector(63 downto 0);
 248         variable newcrf : std_ulogic_vector(3 downto 0);
 249         variable result_with_carry : std_ulogic_vector(64 downto 0);
 250         variable result_en : std_ulogic;
 251         variable crnum : crnum_t;
 252         variable crbit : integer range 0 to 31;
 253         variable scrnum : crnum_t;
 254         variable lo, hi : integer;
 255         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 256         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 257         variable bo, bi : std_ulogic_vector(4 downto 0);
 258         variable bf, bfa : std_ulogic_vector(2 downto 0);
 259         variable cr_op : std_ulogic_vector(9 downto 0);
 260         variable cr_operands : std_ulogic_vector(1 downto 0);
 261         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 262         variable btnum, banum, bbnum : integer range 0 to 31;
 263         variable crresult : std_ulogic;
 264         variable l : std_ulogic;
 265         variable next_nia : std_ulogic_vector(63 downto 0);
 266         variable carry_32, carry_64 : std_ulogic;
 267         variable sign1, sign2 : std_ulogic;
 268         variable abs1, abs2 : signed(63 downto 0);
 269         variable overflow : std_ulogic;
 270         variable negative : std_ulogic;
 271         variable zerohi, zerolo : std_ulogic;
 272         variable msb_a, msb_b : std_ulogic;
 273         variable a_lt : std_ulogic;
 274         variable lv : Execute1ToLoadstore1Type;
 275         variable irq_valid : std_ulogic;
 276         variable exception : std_ulogic;
 277         variable exception_nextpc : std_ulogic;
 278         variable trapval : std_ulogic_vector(4 downto 0);
 279         variable illegal : std_ulogic;
 280     begin
 281         result := (others => '0');
 282         result_with_carry := (others => '0');
 283         result_en := '0';
 284         newcrf := (others => '0');
 285
 286         v := r;
 287         v.e := Execute1ToWritebackInit;
 288         lv := Execute1ToLoadstore1Init;
 289
 290         -- XER forwarding. To avoid having to track XER hazards, we
 291         -- use the previously latched value.
 292         --
 293         -- If the XER was modified by a multiply or a divide, those are
 294         -- single issue, we'll get the up to date value from decode2 from
 295         -- the register file.
 296         --
 297         -- If it was modified by an instruction older than the previous
 298         -- one in EX1, it will have also hit writeback and will be up
 299         -- to date in decode2.
 300         --
 301         -- That leaves us with the case where it was updated by the previous
 302         -- instruction in EX1. In that case, we can forward it back here.
 303         --
 304         -- This will break if we allow pipelining of multiply and divide,
 305         -- but ideally, those should go via EX1 anyway and run as a state
 306         -- machine from here.
 307         --
 308         -- One additional hazard to beware of is an XER:SO modifying instruction
 309         -- in EX1 followed immediately by a store conditional. Due to our
 310         -- writeback latency, the store will go down the LSU with the previous
 311         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 312         --
 313         -- We will need to handle that if we ever make stcx. not single issue
 314         --
 315         -- We always pass a valid XER value downto writeback even when
 316         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 317         -- to work for RC instructions.
 318         --
 319         if r.e.write_xerc_enable = '1' then
 320             v.e.xerc := r.e.xerc;
 321         else
 322             v.e.xerc := e_in.xerc;
 323         end if;
 324
 325         v.lr_update := '0';
 326         v.mul_in_progress := '0';
 327         v.div_in_progress := '0';
 328         v.cntz_in_progress := '0';
 329
 330         -- signals to multiply unit
 331         x_to_multiply <= Execute1ToMultiplyInit;
 332         x_to_multiply.insn_type <= e_in.insn_type;
 333         x_to_multiply.is_32bit <= e_in.is_32bit;
 334
 335         if e_in.is_32bit = '1' then
 336             if e_in.is_signed = '1' then
 337                 x_to_multiply.data1 <= (others => a_in(31));
 338                 x_to_multiply.data1(31 downto 0) <= a_in(31 downto 0);
 339                 x_to_multiply.data2 <= (others => b_in(31));
 340                 x_to_multiply.data2(31 downto 0) <= b_in(31 downto 0);
 341             else
 342                 x_to_multiply.data1 <= '0' & x"00000000" & a_in(31 downto 0);
 343                 x_to_multiply.data2 <= '0' & x"00000000" & b_in(31 downto 0);
 344             end if;
 345         else
 346             if e_in.is_signed = '1' then
 347                 x_to_multiply.data1 <= a_in(63) & a_in;
 348                 x_to_multiply.data2 <= b_in(63) & b_in;
 349             else
 350                 x_to_multiply.data1 <= '0' & a_in;
 351                 x_to_multiply.data2 <= '0' & b_in;
 352             end if;
 353         end if;
 354
 355         -- signals to divide unit
 356         sign1 := '0';
 357         sign2 := '0';
 358         if e_in.is_signed = '1' then
 359             if e_in.is_32bit = '1' then
 360                 sign1 := a_in(31);
 361                 sign2 := b_in(31);
 362             else
 363                 sign1 := a_in(63);
 364                 sign2 := b_in(63);
 365             end if;
 366         end if;
 367         -- take absolute values
 368         if sign1 = '0' then
 369             abs1 := signed(a_in);
 370         else
 371             abs1 := - signed(a_in);
 372         end if;
 373         if sign2 = '0' then
 374             abs2 := signed(b_in);
 375         else
 376             abs2 := - signed(b_in);
 377         end if;
 378
 379         x_to_divider <= Execute1ToDividerInit;
 380         x_to_divider.is_signed <= e_in.is_signed;
 381         x_to_divider.is_32bit <= e_in.is_32bit;
 382         if e_in.insn_type = OP_MOD then
 383             x_to_divider.is_modulus <= '1';
 384         end if;
 385         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 386         if e_in.is_32bit = '0' then
 387             -- 64-bit forms
 388             if e_in.insn_type = OP_DIVE then
 389                 x_to_divider.is_extended <= '1';
 390             end if;
 391             x_to_divider.dividend <= std_ulogic_vector(abs1);
 392             x_to_divider.divisor <= std_ulogic_vector(abs2);
 393         else
 394             -- 32-bit forms
 395             x_to_divider.is_extended <= '0';
 396             if e_in.insn_type = OP_DIVE then   -- extended forms
 397                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 398             else
 399                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 400             end if;
 401             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 402         end if;
 403
 404         ctrl_tmp <= ctrl;
 405         -- FIXME: run at 512MHz not core freq
 406         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 407         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 408
 409         irq_valid := '0';
 410         if ctrl.msr(MSR_EE) = '1' then
 411             if ctrl.dec(63) = '1' then
 412                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#900#, 64));
 413                 report "IRQ valid: DEC";
 414                 irq_valid := '1';
 415             elsif i_in.irq = '1' then
 416                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#500#, 64));
 417                 report "IRQ valid: External";
 418                 irq_valid := '1';
 419             end if;
 420         end if;
 421
 422         terminate_out <= '0';
 423         icache_inval <= '0';
 424         stall_out <= '0';
 425         f_out <= Execute1ToFetch1TypeInit;
 426
 427         -- Next insn adder used in a couple of places
 428         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 429
 430         -- rotator control signals
 431         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 432         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 433         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 434         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 435
 436         ctrl_tmp.irq_state <= WRITE_SRR0;
 437         exception := '0';
 438         illegal := '0';
 439         exception_nextpc := '0';
 440         v.e.exc_write_enable := '0';
 441         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 442         v.e.exc_write_data := e_in.nia;
 443
 444         if ctrl.irq_state = WRITE_SRR1 then
 445             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 446             v.e.exc_write_data := ctrl.srr1;
 447             v.e.exc_write_enable := '1';
 448             ctrl_tmp.msr(MSR_SF) <= '1';
 449             ctrl_tmp.msr(MSR_EE) <= '0';
 450             ctrl_tmp.msr(MSR_PR) <= '0';
 451             ctrl_tmp.msr(MSR_IR) <= '0';
 452             ctrl_tmp.msr(MSR_DR) <= '0';
 453             ctrl_tmp.msr(MSR_RI) <= '0';
 454             ctrl_tmp.msr(MSR_LE) <= '1';
 455             f_out.redirect <= '1';
 456             f_out.redirect_nia <= ctrl.irq_nia;
 457             v.e.valid := e_in.valid;
 458             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 459
 460         elsif irq_valid = '1' and e_in.valid = '1' then
 461             -- we need two cycles to write srr0 and 1
 462             -- will need more when we have to write DSISR, DAR and HIER
 463             -- Don't deliver the interrupt until we have a valid instruction
 464             -- coming in, so we have a valid NIA to put in SRR0.
 465             exception := '1';
 466             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 467
 468         elsif e_in.valid = '1' and ctrl.msr(MSR_PR) = '1' and
 469             instr_is_privileged(e_in.insn_type, e_in.insn) then
 470             -- generate a program interrupt
 471             exception := '1';
 472             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 473             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 474             -- set bit 45 to indicate privileged instruction type interrupt
 475             ctrl_tmp.srr1(63 - 45) <= '1';
 476             report "privileged instruction";
 477
 478         elsif e_in.valid = '1' and e_in.unit = ALU then
 479
 480             report "execute nia " & to_hstring(e_in.nia);
 481
 482             v.e.valid := '1';
 483             v.e.write_reg := e_in.write_reg;
 484             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 485             v.slow_op_rc := e_in.rc;
 486             v.slow_op_oe := e_in.oe;
 487             v.slow_op_xerc := v.e.xerc;
 488
 489             case_0: case e_in.insn_type is
 490
 491             when OP_ILLEGAL =>
 492                 -- we need two cycles to write srr0 and 1
 493                 -- will need more when we have to write DSISR, DAR and HIER
 494                 illegal := '1';
 495             when OP_SC =>
 496                 -- check bit 1 of the instruction is 1 so we know this is sc;
 497                 -- 0 would mean scv, so generate an illegal instruction interrupt
 498                 -- we need two cycles to write srr0 and 1
 499                 -- will need more when we have to write DSISR, DAR and HIER
 500                 if e_in.insn(1) = '1' then
 501                     exception := '1';
 502                     exception_nextpc := '1';
 503                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
 504                     ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 505                     report "sc";
 506                 else
 507                     illegal := '1';
 508                 end if;
 509             when OP_ATTN =>
 510                 -- check bits 1-10 of the instruction to make sure it's attn
 511                 -- if not then it is illegal
 512                 if e_in.insn(10 downto 1) = "0100000000" then
 513                     terminate_out <= '1';
 514                     report "ATTN";
 515                 else
 516                     illegal := '1';
 517                 end if;
 518             when OP_NOP =>
 519                 -- Do nothing
 520             when OP_ADD | OP_CMP | OP_TRAP =>
 521                 if e_in.invert_a = '0' then
 522                     a_inv := a_in;
 523                 else
 524                     a_inv := not a_in;
 525                 end if;
 526                 result_with_carry := ppc_adde(a_inv, b_in,
 527                                               decode_input_carry(e_in.input_carry, v.e.xerc));
 528                 result := result_with_carry(63 downto 0);
 529                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 530                 carry_64 := result_with_carry(64);
 531                 if e_in.insn_type = OP_ADD then
 532                     if e_in.output_carry = '1' then
 533                         set_carry(v.e, carry_32, carry_64);
 534                     end if;
 535                     if e_in.oe = '1' then
 536                         set_ov(v.e,
 537                                calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
 538                                calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
 539                     end if;
 540                     result_en := '1';
 541                 else
 542                     -- trap, CMP and CMPL instructions
 543                     -- Note, we have done RB - RA, not RA - RB
 544                     if e_in.insn_type = OP_CMP then
 545                         l := insn_l(e_in.insn);
 546                     else
 547                         l := not e_in.is_32bit;
 548                     end if;
 549                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 550                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 551                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 552                         -- values are equal
 553                         trapval := "00100";
 554                     else
 555                         if l = '1' then
 556                             -- 64-bit comparison
 557                             msb_a := a_in(63);
 558                             msb_b := b_in(63);
 559                         else
 560                             -- 32-bit comparison
 561                             msb_a := a_in(31);
 562                             msb_b := b_in(31);
 563                         end if;
 564                         if msb_a /= msb_b then
 565                             -- Subtraction might overflow, but
 566                             -- comparison is clear from MSB difference.
 567                             -- for signed, 0 is greater; for unsigned, 1 is greater
 568                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 569                         else
 570                             -- Subtraction cannot overflow since MSBs are equal.
 571                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 572                             a_lt := (not l and carry_32) or (l and carry_64);
 573                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 574                         end if;
 575                     end if;
 576                     if e_in.insn_type = OP_CMP then
 577                         if e_in.is_signed = '1' then
 578                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 579                         else
 580                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 581                         end if;
 582                         bf := insn_bf(e_in.insn);
 583                         crnum := to_integer(unsigned(bf));
 584                         v.e.write_cr_enable := '1';
 585                         v.e.write_cr_mask := num_to_fxm(crnum);
 586                         for i in 0 to 7 loop
 587                             lo := i*4;
 588                             hi := lo + 3;
 589                             v.e.write_cr_data(hi downto lo) := newcrf;
 590                         end loop;
 591                     else
 592                         -- trap instructions (tw, twi, td, tdi)
 593                         if or (trapval and insn_to(e_in.insn)) = '1' then
 594                             -- generate trap-type program interrupt
 595                             exception := '1';
 596                             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 597                             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 598                             -- set bit 46 to say trap occurred
 599                             ctrl_tmp.srr1(63 - 46) <= '1';
 600                             report "trap";
 601                         end if;
 602                     end if;
 603                 end if;
 604             when OP_AND | OP_OR | OP_XOR =>
 605                 result := logical_result;
 606                 result_en := '1';
 607             when OP_B =>
 608                 f_out.redirect <= '1';
 609                 if (insn_aa(e_in.insn)) then
 610                     f_out.redirect_nia <= b_in;
 611                 else
 612                     f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 613                 end if;
 614             when OP_BC =>
 615                 -- read_data1 is CTR
 616                 bo := insn_bo(e_in.insn);
 617                 bi := insn_bi(e_in.insn);
 618                 if bo(4-2) = '0' then
 619                     result := std_ulogic_vector(unsigned(a_in) - 1);
 620                     result_en := '1';
 621                     v.e.write_reg := fast_spr_num(SPR_CTR);
 622                 end if;
 623                 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
 624                     f_out.redirect <= '1';
 625                     if (insn_aa(e_in.insn)) then
 626                         f_out.redirect_nia <= b_in;
 627                     else
 628                         f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 629                     end if;
 630                 end if;
 631             when OP_BCREG =>
 632                 -- read_data1 is CTR
 633                 -- read_data2 is target register (CTR, LR or TAR)
 634                 bo := insn_bo(e_in.insn);
 635                 bi := insn_bi(e_in.insn);
 636                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 637                     result := std_ulogic_vector(unsigned(a_in) - 1);
 638                     result_en := '1';
 639                     v.e.write_reg := fast_spr_num(SPR_CTR);
 640                 end if;
 641                 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
 642                     f_out.redirect <= '1';
 643                     f_out.redirect_nia <= b_in(63 downto 2) & "00";
 644                 end if;
 645
 646             when OP_RFID =>
 647                 f_out.redirect <= '1';
 648                 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
 649                 -- Can't use msr_copy here because the partial function MSR
 650                 -- bits should be left unchanged, not zeroed.
 651                 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
 652                 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
 653                 ctrl_tmp.msr(15 downto 0)  <= b_in(15 downto 0);
 654                 if b_in(MSR_PR) = '1' then
 655                     ctrl_tmp.msr(MSR_EE) <= '1';
 656                     ctrl_tmp.msr(MSR_IR) <= '1';
 657                     ctrl_tmp.msr(MSR_DR) <= '1';
 658                 end if;
 659
 660             when OP_CMPB =>
 661                 result := ppc_cmpb(c_in, b_in);
 662                 result_en := '1';
 663             when OP_CNTZ =>
 664                 v.e.valid := '0';
 665                 v.cntz_in_progress := '1';
 666                 stall_out <= '1';
 667             when OP_EXTS =>
 668                 -- note data_len is a 1-hot encoding
 669                 negative := (e_in.data_len(0) and c_in(7)) or
 670                             (e_in.data_len(1) and c_in(15)) or
 671                             (e_in.data_len(2) and c_in(31));
 672                 result := (others => negative);
 673                 if e_in.data_len(2) = '1' then
 674                     result(31 downto 16) := c_in(31 downto 16);
 675                 end if;
 676                 if e_in.data_len(2) = '1' or e_in.data_len(1) = '1' then
 677                     result(15 downto 8) := c_in(15 downto 8);
 678                 end if;
 679                 result(7 downto 0) := c_in(7 downto 0);
 680                 result_en := '1';
 681             when OP_ISEL =>
 682                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 683                 if e_in.cr(31-crbit) = '1' then
 684                     result := a_in;
 685                 else
 686                     result := b_in;
 687                 end if;
 688                 result_en := '1';
 689             when OP_CROP =>
 690                 cr_op := insn_cr(e_in.insn);
 691                 report "CR OP " & to_hstring(cr_op);
 692                 if cr_op(0) = '0' then -- MCRF
 693                     bf := insn_bf(e_in.insn);
 694                     bfa := insn_bfa(e_in.insn);
 695                     v.e.write_cr_enable := '1';
 696                     crnum := to_integer(unsigned(bf));
 697                     scrnum := to_integer(unsigned(bfa));
 698                     v.e.write_cr_mask := num_to_fxm(crnum);
 699                     for i in 0 to 7 loop
 700                         lo := (7-i)*4;
 701                         hi := lo + 3;
 702                         if i = scrnum then
 703                             newcrf := e_in.cr(hi downto lo);
 704                         end if;
 705                     end loop;
 706                     for i in 0 to 7 loop
 707                         lo := i*4;
 708                         hi := lo + 3;
 709                         v.e.write_cr_data(hi downto lo) := newcrf;
 710                     end loop;
 711                 else
 712                     v.e.write_cr_enable := '1';
 713                     bt := insn_bt(e_in.insn);
 714                     ba := insn_ba(e_in.insn);
 715                     bb := insn_bb(e_in.insn);
 716                     btnum := 31 - to_integer(unsigned(bt));
 717                     banum := 31 - to_integer(unsigned(ba));
 718                     bbnum := 31 - to_integer(unsigned(bb));
 719                     -- Bits 5-8 of cr_op give the truth table of the requested
 720                     -- logical operation
 721                     cr_operands := e_in.cr(banum) & e_in.cr(bbnum);
 722                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 723                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 724                     for i in 0 to 31 loop
 725                         if i = btnum then
 726                             v.e.write_cr_data(i) := crresult;
 727                         else
 728                             v.e.write_cr_data(i) := e_in.cr(i);
 729                         end if;
 730                     end loop;
 731                 end if;
 732             when OP_MFMSR =>
 733                 result := ctrl.msr;
 734                 result_en := '1';
 735             when OP_MFSPR =>
 736                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 737                     "=" & to_hstring(a_in);
 738                 result_en := '1';
 739                 if is_fast_spr(e_in.read_reg1) then
 740                     result := a_in;
 741                     if decode_spr_num(e_in.insn) = SPR_XER then
 742                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 743                         result(63 downto 32) := (others => '0');
 744                         result(63-32) := v.e.xerc.so;
 745                         result(63-33) := v.e.xerc.ov;
 746                         result(63-34) := v.e.xerc.ca;
 747                         result(63-35 downto 63-43) := "000000000";
 748                         result(63-44) := v.e.xerc.ov32;
 749                         result(63-45) := v.e.xerc.ca32;
 750                     end if;
 751                 else
 752                     case decode_spr_num(e_in.insn) is
 753                     when SPR_TB =>
 754                         result := ctrl.tb;
 755                     when SPR_DEC =>
 756                         result := ctrl.dec;
 757                     when others =>
 758                         -- mfspr from unimplemented SPRs should be a nop in
 759                         -- supervisor mode and a program interrupt for user mode
 760                         result := c_in;
 761                         if ctrl.msr(MSR_PR) = '1' then
 762                             illegal := '1';
 763                         end if;
 764                     end case;
 765                 end if;
 766             when OP_MFCR =>
 767                 if e_in.insn(20) = '0' then
 768                     -- mfcr
 769                     result := x"00000000" & e_in.cr;
 770                 else
 771                     -- mfocrf
 772                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 773                     result := (others => '0');
 774                     for i in 0 to 7 loop
 775                         lo := (7-i)*4;
 776                         hi := lo + 3;
 777                         if crnum = i then
 778                             result(hi downto lo) := e_in.cr(hi downto lo);
 779                         end if;
 780                     end loop;
 781                 end if;
 782                 result_en := '1';
 783             when OP_MTCRF =>
 784                 v.e.write_cr_enable := '1';
 785                 if e_in.insn(20) = '0' then
 786                     -- mtcrf
 787                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 788                 else
 789                     -- mtocrf: We require one hot priority encoding here
 790                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 791                     v.e.write_cr_mask := num_to_fxm(crnum);
 792                 end if;
 793                 v.e.write_cr_data := c_in(31 downto 0);
 794             when OP_MTMSRD =>
 795                 if e_in.insn(16) = '1' then
 796                     -- just update EE and RI
 797                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 798                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 799                 else
 800                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 801                     -- and 63 (LE) (IBM bit numbering)
 802                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 803                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 804                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 805                     if c_in(MSR_PR) = '1' then
 806                         ctrl_tmp.msr(MSR_EE) <= '1';
 807                         ctrl_tmp.msr(MSR_IR) <= '1';
 808                         ctrl_tmp.msr(MSR_DR) <= '1';
 809                     end if;
 810                 end if;
 811             when OP_MTSPR =>
 812                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 813                     "=" & to_hstring(c_in);
 814                 if is_fast_spr(e_in.write_reg) then
 815                     result := c_in;
 816                     result_en := '1';
 817                     if decode_spr_num(e_in.insn) = SPR_XER then
 818                         v.e.xerc.so := c_in(63-32);
 819                         v.e.xerc.ov := c_in(63-33);
 820                         v.e.xerc.ca := c_in(63-34);
 821                         v.e.xerc.ov32 := c_in(63-44);
 822                         v.e.xerc.ca32 := c_in(63-45);
 823                         v.e.write_xerc_enable := '1';
 824                     end if;
 825                 else
 826                     -- slow spr
 827                     case decode_spr_num(e_in.insn) is
 828                     when SPR_DEC =>
 829                         ctrl_tmp.dec <= c_in;
 830                     when others =>
 831                         -- mtspr to unimplemented SPRs should be a nop in
 832                         -- supervisor mode and a program interrupt for user mode
 833                         if ctrl.msr(MSR_PR) = '1' then
 834                             illegal := '1';
 835                         end if;
 836                     end case;
 837                 end if;
 838             when OP_POPCNT =>
 839                 result := popcnt_result;
 840                 result_en := '1';
 841             when OP_PRTY =>
 842                 result := parity_result;
 843                 result_en := '1';
 844             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
 845                 result := rotator_result;
 846                 if e_in.output_carry = '1' then
 847                     set_carry(v.e, rotator_carry, rotator_carry);
 848                 end if;
 849                 result_en := '1';
 850
 851             when OP_ISYNC =>
 852                 f_out.redirect <= '1';
 853                 f_out.redirect_nia <= next_nia;
 854
 855             when OP_ICBI =>
 856                 icache_inval <= '1';
 857
 858             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
 859                 v.e.valid := '0';
 860                 v.mul_in_progress := '1';
 861                 stall_out <= '1';
 862                 x_to_multiply.valid <= '1';
 863
 864             when OP_DIV | OP_DIVE | OP_MOD =>
 865                 v.e.valid := '0';
 866                 v.div_in_progress := '1';
 867                 stall_out <= '1';
 868                 x_to_divider.valid <= '1';
 869
 870             when others =>
 871                 terminate_out <= '1';
 872                 report "illegal";
 873             end case;
 874
 875             v.e.rc := e_in.rc and e_in.valid;
 876
 877             -- Update LR on the next cycle after a branch link
 878             --
 879             -- WARNING: The LR update isn't tracked by our hazard tracker. This
 880             --          will work (well I hope) because it only happens on branches
 881             --          which will flush all decoded instructions. By the time
 882             --          fetch catches up, we'll have the new LR. This will
 883             --          *not* work properly however if we have a branch predictor,
 884             --          in which case the solution would probably be to keep a
 885             --          local cache of the updated LR in execute1 (flushed on
 886             --          exceptions) that is used instead of the value from
 887             --          decode when its content is valid.
 888             if e_in.lr = '1' then
 889                 v.lr_update := '1';
 890                 v.next_lr := next_nia;
 891                 v.e.valid := '0';
 892                 report "Delayed LR update to " & to_hstring(next_nia);
 893                 stall_out <= '1';
 894             end if;
 895
 896         elsif e_in.valid = '1' then
 897             -- instruction for other units, i.e. LDST
 898             v.e.valid := '0';
 899             if e_in.unit = LDST then
 900                 lv.valid := '1';
 901             end if;
 902
 903         elsif r.lr_update = '1' then
 904             result_en := '1';
 905             result := r.next_lr;
 906             v.e.write_reg := fast_spr_num(SPR_LR);
 907             v.e.valid := '1';
 908         elsif r.cntz_in_progress = '1' then
 909             -- cnt[lt]z always takes two cycles
 910             result := countzero_result;
 911             result_en := '1';
 912             v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 913             v.e.rc := v.slow_op_rc;
 914             v.e.xerc := v.slow_op_xerc;
 915             v.e.valid := '1';
 916         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
 917             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
 918                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
 919                 if r.mul_in_progress = '1' then
 920                     result := multiply_to_x.write_reg_data;
 921                     overflow := multiply_to_x.overflow;
 922                 else
 923                     result := divider_to_x.write_reg_data;
 924                     overflow := divider_to_x.overflow;
 925                 end if;
 926                 result_en := '1';
 927                 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 928                 v.e.rc := v.slow_op_rc;
 929                 v.e.xerc := v.slow_op_xerc;
 930                 v.e.write_xerc_enable := v.slow_op_oe;
 931                 -- We must test oe because the RC update code in writeback
 932                 -- will use the xerc value to set CR0:SO so we must not clobber
 933                 -- xerc if OE wasn't set.
 934                 if v.slow_op_oe = '1' then
 935                     v.e.xerc.ov := overflow;
 936                     v.e.xerc.ov32 := overflow;
 937                     v.e.xerc.so := v.slow_op_xerc.so or overflow;
 938                 end if;
 939                 v.e.valid := '1';
 940             else
 941                 stall_out <= '1';
 942                 v.mul_in_progress := r.mul_in_progress;
 943                 v.div_in_progress := r.div_in_progress;
 944             end if;
 945         end if;
 946
 947         if illegal = '1' then
 948             exception := '1';
 949             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 950             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 951             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
 952             -- set bit 44 to indicate we have an illegal
 953             ctrl_tmp.srr1(63 - 44) <= '1';
 954             report "illegal";
 955         end if;
 956         if exception = '1' then
 957             v.e.exc_write_enable := '1';
 958             if exception_nextpc = '1' then
 959                 v.e.exc_write_data := next_nia;
 960             end if;
 961             ctrl_tmp.irq_state <= WRITE_SRR1;
 962             v.e.valid := '1';
 963         end if;
 964
 965         v.e.write_data := result;
 966         v.e.write_enable := result_en;
 967
 968         -- Outputs to loadstore1 (async)
 969         lv.op := e_in.insn_type;
 970         lv.addr1 := a_in;
 971         lv.addr2 := b_in;
 972         lv.data := c_in;
 973         lv.write_reg := gspr_to_gpr(e_in.write_reg);
 974         lv.length := e_in.data_len;
 975         lv.byte_reverse := e_in.byte_reverse;
 976         lv.sign_extend := e_in.sign_extend;
 977         lv.update := e_in.update;
 978         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
 979         lv.xerc := v.e.xerc;
 980         lv.reserve := e_in.reserve;
 981         lv.rc := e_in.rc;
 982         -- decode l*cix and st*cix instructions here
 983         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
 984             e_in.insn(5 downto 1) = "10101" then
 985             lv.ci := '1';
 986         end if;
 987
 988         -- Update registers
 989         rin <= v;
 990
 991         -- update outputs
 992         --f_out <= r.f;
 993         l_out <= lv;
 994         e_out <= r.e;
 995         flush_out <= f_out.redirect;
 996     end process;
 997 end architecture behaviour;