execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30
  31         ext_irq_in : std_ulogic;
  32
  33         -- asynchronous
  34         l_out : out Execute1ToLoadstore1Type;
  35         f_out : out Execute1ToFetch1Type;
  36
  37         e_out : out Execute1ToWritebackType;
  38
  39         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  40
  41         icache_inval : out std_ulogic;
  42         terminate_out : out std_ulogic;
  43
  44         log_out : out std_ulogic_vector(14 downto 0);
  45         log_rd_addr : out std_ulogic_vector(31 downto 0);
  46         log_rd_data : in std_ulogic_vector(63 downto 0);
  47         log_wr_addr : in std_ulogic_vector(31 downto 0)
  48         );
  49 end entity execute1;
  50
  51 architecture behaviour of execute1 is
  52     type reg_type is record
  53         e : Execute1ToWritebackType;
  54         f : Execute1ToFetch1Type;
  55         busy: std_ulogic;
  56         terminate: std_ulogic;
  57         trace_next : std_ulogic;
  58         prev_op : insn_type_t;
  59         lr_update : std_ulogic;
  60         next_lr : std_ulogic_vector(63 downto 0);
  61         mul_in_progress : std_ulogic;
  62         mul_finish : std_ulogic;
  63         div_in_progress : std_ulogic;
  64         cntz_in_progress : std_ulogic;
  65         slow_op_insn : insn_type_t;
  66         slow_op_dest : gpr_index_t;
  67         slow_op_rc : std_ulogic;
  68         slow_op_oe : std_ulogic;
  69         slow_op_xerc : xer_common_t;
  70         last_nia : std_ulogic_vector(63 downto 0);
  71         log_addr_spr : std_ulogic_vector(31 downto 0);
  72     end record;
  73     constant reg_type_init : reg_type :=
  74         (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
  75          busy => '0', lr_update => '0', terminate => '0', trace_next => '0', prev_op => OP_ILLEGAL,
  76          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  77          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  78          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
  79
  80     signal r, rin : reg_type;
  81
  82     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  83     signal cr_in : std_ulogic_vector(31 downto 0);
  84
  85     signal valid_in : std_ulogic;
  86     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  87     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  88     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  89     signal rot_sign_ext: std_ulogic;
  90     signal rotator_result: std_ulogic_vector(63 downto 0);
  91     signal rotator_carry: std_ulogic;
  92     signal logical_result: std_ulogic_vector(63 downto 0);
  93     signal countzero_result: std_ulogic_vector(63 downto 0);
  94
  95     -- multiply signals
  96     signal x_to_multiply: MultiplyInputType;
  97     signal multiply_to_x: MultiplyOutputType;
  98
  99     -- divider signals
 100     signal x_to_divider: Execute1ToDividerType;
 101     signal divider_to_x: DividerToExecute1Type;
 102
 103     -- random number generator signals
 104     signal random_raw  : std_ulogic_vector(63 downto 0);
 105     signal random_cond : std_ulogic_vector(63 downto 0);
 106     signal random_err  : std_ulogic;
 107
 108     -- signals for logging
 109     signal exception_log : std_ulogic;
 110     signal irq_valid_log : std_ulogic;
 111
 112     type privilege_level is (USER, SUPER);
 113     type op_privilege_array is array(insn_type_t) of privilege_level;
 114     constant op_privilege: op_privilege_array := (
 115         OP_ATTN => SUPER,
 116         OP_MFMSR => SUPER,
 117         OP_MTMSRD => SUPER,
 118         OP_RFID => SUPER,
 119         OP_TLBIE => SUPER,
 120         others => USER
 121         );
 122
 123     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 124         return boolean is
 125     begin
 126         if op_privilege(op) = SUPER then
 127             return true;
 128         elsif op = OP_MFSPR or op = OP_MTSPR then
 129             return insn(20) = '1';
 130         else
 131             return false;
 132         end if;
 133     end;
 134
 135     procedure set_carry(e: inout Execute1ToWritebackType;
 136                         carry32 : in std_ulogic;
 137                         carry : in std_ulogic) is
 138     begin
 139         e.xerc.ca32 := carry32;
 140         e.xerc.ca := carry;
 141         e.write_xerc_enable := '1';
 142     end;
 143
 144     procedure set_ov(e: inout Execute1ToWritebackType;
 145                      ov   : in std_ulogic;
 146                      ov32 : in std_ulogic) is
 147     begin
 148         e.xerc.ov32 := ov32;
 149         e.xerc.ov := ov;
 150         if ov = '1' then
 151             e.xerc.so := '1';
 152         end if;
 153         e.write_xerc_enable := '1';
 154     end;
 155
 156     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 157                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 158     begin
 159         return (ca xor msb_r) and not (msb_a xor msb_b);
 160     end;
 161
 162     function decode_input_carry(ic : carry_in_t;
 163                                 xerc : xer_common_t) return std_ulogic is
 164     begin
 165         case ic is
 166         when ZERO =>
 167             return '0';
 168         when CA =>
 169             return xerc.ca;
 170         when OV =>
 171             return xerc.ov;
 172         when ONE =>
 173             return '1';
 174         end case;
 175     end;
 176
 177     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 178         return std_ulogic_vector is
 179         variable msr_out: std_ulogic_vector(63 downto 0);
 180     begin
 181         -- ISA says this:
 182         --  Defined MSR bits are classified as either full func-
 183         --  tion or partial function. Full function MSR bits are
 184         --  saved in SRR1 or HSRR1 when an interrupt other
 185         --  than a System Call Vectored interrupt occurs and
 186         --  restored by rfscv, rfid, or hrfid, while partial func-
 187         --  tion MSR bits are not saved or restored.
 188         --  Full function MSR bits lie in the range 0:32, 37:41, and
 189         --  48:63, and partial function MSR bits lie in the range
 190         --  33:36 and 42:47. (Note this is IBM bit numbering).
 191         msr_out := (others => '0');
 192         msr_out(63 downto 31) := msr(63 downto 31);
 193         msr_out(26 downto 22) := msr(26 downto 22);
 194         msr_out(15 downto 0)  := msr(15 downto 0);
 195         return msr_out;
 196     end;
 197
 198     -- Tell vivado to keep the hierarchy for the random module so that the
 199     -- net names in the xdc file match.
 200     attribute keep_hierarchy : string;
 201     attribute keep_hierarchy of random_0 : label is "yes";
 202
 203 begin
 204
 205     rotator_0: entity work.rotator
 206         port map (
 207             rs => c_in,
 208             ra => a_in,
 209             shift => b_in(6 downto 0),
 210             insn => e_in.insn,
 211             is_32bit => e_in.is_32bit,
 212             right_shift => right_shift,
 213             arith => e_in.is_signed,
 214             clear_left => rot_clear_left,
 215             clear_right => rot_clear_right,
 216             sign_ext_rs => rot_sign_ext,
 217             result => rotator_result,
 218             carry_out => rotator_carry
 219             );
 220
 221     logical_0: entity work.logical
 222         port map (
 223             rs => c_in,
 224             rb => b_in,
 225             op => e_in.insn_type,
 226             invert_in => e_in.invert_a,
 227             invert_out => e_in.invert_out,
 228             result => logical_result,
 229             datalen => e_in.data_len
 230             );
 231
 232     countzero_0: entity work.zero_counter
 233         port map (
 234             clk => clk,
 235             rs => c_in,
 236             count_right => e_in.insn(10),
 237             is_32bit => e_in.is_32bit,
 238             result => countzero_result
 239             );
 240
 241     multiply_0: entity work.multiply
 242         port map (
 243             clk => clk,
 244             m_in => x_to_multiply,
 245             m_out => multiply_to_x
 246             );
 247
 248     divider_0: entity work.divider
 249         port map (
 250             clk => clk,
 251             rst => rst,
 252             d_in => x_to_divider,
 253             d_out => divider_to_x
 254             );
 255
 256     random_0: entity work.random
 257         port map (
 258             clk => clk,
 259             data => random_cond,
 260             raw => random_raw,
 261             err => random_err
 262             );
 263
 264     dbg_msr_out <= ctrl.msr;
 265     log_rd_addr <= r.log_addr_spr;
 266
 267     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 268     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 269     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 270
 271     busy_out <= l_in.busy or r.busy;
 272     valid_in <= e_in.valid and not busy_out;
 273
 274     terminate_out <= r.terminate;
 275
 276     execute1_0: process(clk)
 277     begin
 278         if rising_edge(clk) then
 279             if rst = '1' then
 280                 r <= reg_type_init;
 281                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 282                 ctrl.irq_state <= WRITE_SRR0;
 283             else
 284                 r <= rin;
 285                 ctrl <= ctrl_tmp;
 286                 assert not (r.lr_update = '1' and valid_in = '1')
 287                     report "LR update collision with valid in EX1"
 288                     severity failure;
 289                 if r.lr_update = '1' then
 290                     report "LR update to " & to_hstring(r.next_lr);
 291                 end if;
 292             end if;
 293         end if;
 294     end process;
 295
 296     execute1_1: process(all)
 297         variable v : reg_type;
 298         variable a_inv : std_ulogic_vector(63 downto 0);
 299         variable result : std_ulogic_vector(63 downto 0);
 300         variable newcrf : std_ulogic_vector(3 downto 0);
 301         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 302         variable result_en : std_ulogic;
 303         variable crnum : crnum_t;
 304         variable crbit : integer range 0 to 31;
 305         variable scrnum : crnum_t;
 306         variable lo, hi : integer;
 307         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 308         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 309         variable bo, bi : std_ulogic_vector(4 downto 0);
 310         variable bf, bfa : std_ulogic_vector(2 downto 0);
 311         variable cr_op : std_ulogic_vector(9 downto 0);
 312         variable cr_operands : std_ulogic_vector(1 downto 0);
 313         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 314         variable btnum, banum, bbnum : integer range 0 to 31;
 315         variable crresult : std_ulogic;
 316         variable l : std_ulogic;
 317         variable next_nia : std_ulogic_vector(63 downto 0);
 318         variable carry_32, carry_64 : std_ulogic;
 319         variable sign1, sign2 : std_ulogic;
 320         variable abs1, abs2 : signed(63 downto 0);
 321         variable overflow : std_ulogic;
 322         variable zerohi, zerolo : std_ulogic;
 323         variable msb_a, msb_b : std_ulogic;
 324         variable a_lt : std_ulogic;
 325         variable lv : Execute1ToLoadstore1Type;
 326         variable irq_valid : std_ulogic;
 327         variable exception : std_ulogic;
 328         variable exception_nextpc : std_ulogic;
 329         variable trapval : std_ulogic_vector(4 downto 0);
 330         variable illegal : std_ulogic;
 331         variable is_branch : std_ulogic;
 332         variable taken_branch : std_ulogic;
 333         variable abs_branch : std_ulogic;
 334         variable spr_val : std_ulogic_vector(63 downto 0);
 335         variable addend : std_ulogic_vector(127 downto 0);
 336         variable do_trace : std_ulogic;
 337     begin
 338         result := (others => '0');
 339         sum_with_carry := (others => '0');
 340         result_en := '0';
 341         newcrf := (others => '0');
 342         is_branch := '0';
 343         taken_branch := '0';
 344         abs_branch := '0';
 345
 346         v := r;
 347         v.e := Execute1ToWritebackInit;
 348         lv := Execute1ToLoadstore1Init;
 349         v.f.redirect := '0';
 350
 351         -- XER forwarding. To avoid having to track XER hazards, we
 352         -- use the previously latched value.
 353         --
 354         -- If the XER was modified by a multiply or a divide, those are
 355         -- single issue, we'll get the up to date value from decode2 from
 356         -- the register file.
 357         --
 358         -- If it was modified by an instruction older than the previous
 359         -- one in EX1, it will have also hit writeback and will be up
 360         -- to date in decode2.
 361         --
 362         -- That leaves us with the case where it was updated by the previous
 363         -- instruction in EX1. In that case, we can forward it back here.
 364         --
 365         -- This will break if we allow pipelining of multiply and divide,
 366         -- but ideally, those should go via EX1 anyway and run as a state
 367         -- machine from here.
 368         --
 369         -- One additional hazard to beware of is an XER:SO modifying instruction
 370         -- in EX1 followed immediately by a store conditional. Due to our
 371         -- writeback latency, the store will go down the LSU with the previous
 372         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 373         --
 374         -- We will need to handle that if we ever make stcx. not single issue
 375         --
 376         -- We always pass a valid XER value downto writeback even when
 377         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 378         -- to work for RC instructions.
 379         --
 380         if r.e.write_xerc_enable = '1' then
 381             v.e.xerc := r.e.xerc;
 382         else
 383             v.e.xerc := e_in.xerc;
 384         end if;
 385
 386         -- CR forwarding
 387         cr_in <= e_in.cr;
 388         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 389             for i in 0 to 7 loop
 390                 if r.e.write_cr_mask(i) = '1' then
 391                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 392                 end if;
 393             end loop;
 394         end if;
 395
 396         v.lr_update := '0';
 397         v.mul_in_progress := '0';
 398         v.div_in_progress := '0';
 399         v.cntz_in_progress := '0';
 400         v.mul_finish := '0';
 401
 402         -- Main adder
 403         if e_in.invert_a = '0' then
 404             a_inv := a_in;
 405         else
 406             a_inv := not a_in;
 407         end if;
 408         sum_with_carry := ppc_adde(a_inv, b_in,
 409                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 410
 411         -- signals to multiply and divide units
 412         sign1 := '0';
 413         sign2 := '0';
 414         if e_in.is_signed = '1' then
 415             if e_in.is_32bit = '1' then
 416                 sign1 := a_in(31);
 417                 sign2 := b_in(31);
 418             else
 419                 sign1 := a_in(63);
 420                 sign2 := b_in(63);
 421             end if;
 422         end if;
 423         -- take absolute values
 424         if sign1 = '0' then
 425             abs1 := signed(a_in);
 426         else
 427             abs1 := - signed(a_in);
 428         end if;
 429         if sign2 = '0' then
 430             abs2 := signed(b_in);
 431         else
 432             abs2 := - signed(b_in);
 433         end if;
 434
 435         x_to_multiply <= MultiplyInputInit;
 436         x_to_multiply.is_32bit <= e_in.is_32bit;
 437
 438         x_to_divider <= Execute1ToDividerInit;
 439         x_to_divider.is_signed <= e_in.is_signed;
 440         x_to_divider.is_32bit <= e_in.is_32bit;
 441         if e_in.insn_type = OP_MOD then
 442             x_to_divider.is_modulus <= '1';
 443         end if;
 444
 445         addend := (others => '0');
 446         if e_in.insn(26) = '0' then
 447             -- integer multiply-add, major op 4 (if it is a multiply)
 448             addend(63 downto 0) := c_in;
 449             if e_in.is_signed = '1' then
 450                 addend(127 downto 64) := (others => c_in(63));
 451             end if;
 452         end if;
 453         if (sign1 xor sign2) = '1' then
 454             addend := not addend;
 455         end if;
 456
 457         x_to_multiply.not_result <= sign1 xor sign2;
 458         x_to_multiply.addend <= addend;
 459         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 460         if e_in.is_32bit = '0' then
 461             -- 64-bit forms
 462             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 463             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 464             if e_in.insn_type = OP_DIVE then
 465                 x_to_divider.is_extended <= '1';
 466             end if;
 467             x_to_divider.dividend <= std_ulogic_vector(abs1);
 468             x_to_divider.divisor <= std_ulogic_vector(abs2);
 469         else
 470             -- 32-bit forms
 471             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 472             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 473             x_to_divider.is_extended <= '0';
 474             if e_in.insn_type = OP_DIVE then   -- extended forms
 475                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 476             else
 477                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 478             end if;
 479             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 480         end if;
 481
 482         ctrl_tmp <= ctrl;
 483         -- FIXME: run at 512MHz not core freq
 484         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 485         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 486
 487         irq_valid := '0';
 488         if ctrl.msr(MSR_EE) = '1' then
 489             if ctrl.dec(63) = '1' then
 490                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
 491                 report "IRQ valid: DEC";
 492                 irq_valid := '1';
 493             elsif ext_irq_in = '1' then
 494                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
 495                 report "IRQ valid: External";
 496                 irq_valid := '1';
 497             end if;
 498         end if;
 499
 500         v.terminate := '0';
 501         icache_inval <= '0';
 502         v.busy := '0';
 503         -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
 504         v.f.virt_mode := ctrl.msr(MSR_IR);
 505         v.f.priv_mode := not ctrl.msr(MSR_PR);
 506         v.f.big_endian := not ctrl.msr(MSR_LE);
 507         v.f.mode_32bit := not ctrl.msr(MSR_SF);
 508
 509         -- Next insn adder used in a couple of places
 510         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 511
 512         -- rotator control signals
 513         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 514         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 515         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 516         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 517
 518         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 519         ctrl_tmp.irq_state <= WRITE_SRR0;
 520         exception := '0';
 521         illegal := '0';
 522         exception_nextpc := '0';
 523         v.e.exc_write_enable := '0';
 524         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 525         v.e.exc_write_data := e_in.nia;
 526         if valid_in = '1' then
 527             v.last_nia := e_in.nia;
 528         end if;
 529
 530         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 531
 532         do_trace := valid_in and ctrl.msr(MSR_SE);
 533         if valid_in = '1' then
 534             v.prev_op := e_in.insn_type;
 535         end if;
 536
 537         if ctrl.irq_state = WRITE_SRR1 then
 538             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 539             v.e.exc_write_data := ctrl.srr1;
 540             v.e.exc_write_enable := '1';
 541             ctrl_tmp.msr(MSR_SF) <= '1';
 542             ctrl_tmp.msr(MSR_EE) <= '0';
 543             ctrl_tmp.msr(MSR_PR) <= '0';
 544             ctrl_tmp.msr(MSR_SE) <= '0';
 545             ctrl_tmp.msr(MSR_BE) <= '0';
 546             ctrl_tmp.msr(MSR_FP) <= '0';
 547             ctrl_tmp.msr(MSR_FE0) <= '0';
 548             ctrl_tmp.msr(MSR_FE1) <= '0';
 549             ctrl_tmp.msr(MSR_IR) <= '0';
 550             ctrl_tmp.msr(MSR_DR) <= '0';
 551             ctrl_tmp.msr(MSR_RI) <= '0';
 552             ctrl_tmp.msr(MSR_LE) <= '1';
 553             v.e.valid := '1';
 554             v.trace_next := '0';
 555             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 556
 557         elsif r.trace_next = '1' and valid_in = '1' then
 558             -- Generate a trace interrupt rather than executing the next instruction
 559             -- or taking any asynchronous interrupt
 560             v.f.redirect_nia := std_logic_vector(to_unsigned(16#d00#, 64));
 561             ctrl_tmp.srr1(63 - 33) <= '1';
 562             if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 563                 r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 564                 ctrl_tmp.srr1(63 - 35) <= '1';
 565             elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 566                 ctrl_tmp.srr1(63 - 36) <= '1';
 567             end if;
 568             exception := '1';
 569
 570         elsif irq_valid = '1' and valid_in = '1' then
 571             -- we need two cycles to write srr0 and 1
 572             -- will need more when we have to write HEIR
 573             -- Don't deliver the interrupt until we have a valid instruction
 574             -- coming in, so we have a valid NIA to put in SRR0.
 575             exception := '1';
 576
 577         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 578             instr_is_privileged(e_in.insn_type, e_in.insn) then
 579             -- generate a program interrupt
 580             exception := '1';
 581             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 582             -- set bit 45 to indicate privileged instruction type interrupt
 583             ctrl_tmp.srr1(63 - 45) <= '1';
 584             report "privileged instruction";
 585
 586         elsif not HAS_FPU and valid_in = '1' and
 587             (e_in.insn_type = OP_FPLOAD or e_in.insn_type = OP_FPSTORE) then
 588             -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 589             illegal := '1';
 590
 591         elsif HAS_FPU and valid_in = '1' and ctrl.msr(MSR_FP) = '0' and
 592             (e_in.insn_type = OP_FPLOAD or e_in.insn_type = OP_FPSTORE) then
 593             -- generate a floating-point unavailable interrupt
 594             exception := '1';
 595             v.f.redirect_nia := std_logic_vector(to_unsigned(16#800#, 64));
 596             report "FP unavailable interrupt";
 597
 598         elsif valid_in = '1' and e_in.unit = ALU then
 599
 600             report "execute nia " & to_hstring(e_in.nia);
 601
 602             v.e.valid := '1';
 603             v.e.write_reg := e_in.write_reg;
 604             v.slow_op_insn := e_in.insn_type;
 605             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 606             v.slow_op_rc := e_in.rc;
 607             v.slow_op_oe := e_in.oe;
 608             v.slow_op_xerc := v.e.xerc;
 609
 610             case_0: case e_in.insn_type is
 611
 612             when OP_ILLEGAL =>
 613                 -- we need two cycles to write srr0 and 1
 614                 -- will need more when we have to write HEIR
 615                 illegal := '1';
 616             when OP_SC =>
 617                 -- check bit 1 of the instruction is 1 so we know this is sc;
 618                 -- 0 would mean scv, so generate an illegal instruction interrupt
 619                 -- we need two cycles to write srr0 and 1
 620                 if e_in.insn(1) = '1' then
 621                     exception := '1';
 622                     exception_nextpc := '1';
 623                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
 624                     report "sc";
 625                 else
 626                     illegal := '1';
 627                 end if;
 628             when OP_ATTN =>
 629                 -- check bits 1-10 of the instruction to make sure it's attn
 630                 -- if not then it is illegal
 631                 if e_in.insn(10 downto 1) = "0100000000" then
 632                     v.terminate := '1';
 633                     report "ATTN";
 634                 else
 635                     illegal := '1';
 636                 end if;
 637             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 638                 -- Do nothing
 639             when OP_ADD | OP_CMP | OP_TRAP =>
 640                 result := sum_with_carry(63 downto 0);
 641                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 642                 carry_64 := sum_with_carry(64);
 643                 if e_in.insn_type = OP_ADD then
 644                     if e_in.output_carry = '1' then
 645                         if e_in.input_carry /= OV then
 646                             set_carry(v.e, carry_32, carry_64);
 647                         else
 648                             v.e.xerc.ov := carry_64;
 649                             v.e.xerc.ov32 := carry_32;
 650                             v.e.write_xerc_enable := '1';
 651                         end if;
 652                     end if;
 653                     if e_in.oe = '1' then
 654                         set_ov(v.e,
 655                                calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 656                                calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 657                     end if;
 658                     result_en := '1';
 659                 else
 660                     -- trap, CMP and CMPL instructions
 661                     -- Note, we have done RB - RA, not RA - RB
 662                     if e_in.insn_type = OP_CMP then
 663                         l := insn_l(e_in.insn);
 664                     else
 665                         l := not e_in.is_32bit;
 666                     end if;
 667                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 668                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 669                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 670                         -- values are equal
 671                         trapval := "00100";
 672                     else
 673                         if l = '1' then
 674                             -- 64-bit comparison
 675                             msb_a := a_in(63);
 676                             msb_b := b_in(63);
 677                         else
 678                             -- 32-bit comparison
 679                             msb_a := a_in(31);
 680                             msb_b := b_in(31);
 681                         end if;
 682                         if msb_a /= msb_b then
 683                             -- Subtraction might overflow, but
 684                             -- comparison is clear from MSB difference.
 685                             -- for signed, 0 is greater; for unsigned, 1 is greater
 686                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 687                         else
 688                             -- Subtraction cannot overflow since MSBs are equal.
 689                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 690                             a_lt := (not l and carry_32) or (l and carry_64);
 691                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 692                         end if;
 693                     end if;
 694                     if e_in.insn_type = OP_CMP then
 695                         if e_in.is_signed = '1' then
 696                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 697                         else
 698                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 699                         end if;
 700                         bf := insn_bf(e_in.insn);
 701                         crnum := to_integer(unsigned(bf));
 702                         v.e.write_cr_enable := '1';
 703                         v.e.write_cr_mask := num_to_fxm(crnum);
 704                         for i in 0 to 7 loop
 705                             lo := i*4;
 706                             hi := lo + 3;
 707                             v.e.write_cr_data(hi downto lo) := newcrf;
 708                         end loop;
 709                     else
 710                         -- trap instructions (tw, twi, td, tdi)
 711                         v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 712                         -- set bit 46 to say trap occurred
 713                         ctrl_tmp.srr1(63 - 46) <= '1';
 714                         if or (trapval and insn_to(e_in.insn)) = '1' then
 715                             -- generate trap-type program interrupt
 716                             exception := '1';
 717                             report "trap";
 718                         end if;
 719                     end if;
 720                 end if;
 721             when OP_ADDG6S =>
 722                 result := (others => '0');
 723                 for i in 0 to 14 loop
 724                     lo := i * 4;
 725                     hi := (i + 1) * 4;
 726                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 727                         result(lo + 3 downto lo) := "0110";
 728                     end if;
 729                 end loop;
 730                 if sum_with_carry(64) = '0' then
 731                     result(63 downto 60) := "0110";
 732                 end if;
 733                 result_en := '1';
 734             when OP_CMPRB =>
 735                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 736                 bf := insn_bf(e_in.insn);
 737                 crnum := to_integer(unsigned(bf));
 738                 v.e.write_cr_enable := '1';
 739                 v.e.write_cr_mask := num_to_fxm(crnum);
 740                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 741                                      newcrf & newcrf & newcrf & newcrf;
 742             when OP_CMPEQB =>
 743                 newcrf := ppc_cmpeqb(a_in, b_in);
 744                 bf := insn_bf(e_in.insn);
 745                 crnum := to_integer(unsigned(bf));
 746                 v.e.write_cr_enable := '1';
 747                 v.e.write_cr_mask := num_to_fxm(crnum);
 748                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 749                                      newcrf & newcrf & newcrf & newcrf;
 750             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 751                     OP_BPERM | OP_BCD =>
 752                 result := logical_result;
 753                 result_en := '1';
 754             when OP_B =>
 755                 is_branch := '1';
 756                 taken_branch := '1';
 757                 abs_branch := insn_aa(e_in.insn);
 758                 if ctrl.msr(MSR_BE) = '1' then
 759                     do_trace := '1';
 760                 end if;
 761             when OP_BC =>
 762                 -- read_data1 is CTR
 763                 bo := insn_bo(e_in.insn);
 764                 bi := insn_bi(e_in.insn);
 765                 if bo(4-2) = '0' then
 766                     result := std_ulogic_vector(unsigned(a_in) - 1);
 767                     result_en := '1';
 768                     v.e.write_reg := fast_spr_num(SPR_CTR);
 769                 end if;
 770                 is_branch := '1';
 771                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 772                 abs_branch := insn_aa(e_in.insn);
 773                 if ctrl.msr(MSR_BE) = '1' then
 774                     do_trace := '1';
 775                 end if;
 776             when OP_BCREG =>
 777                 -- read_data1 is CTR
 778                 -- read_data2 is target register (CTR, LR or TAR)
 779                 bo := insn_bo(e_in.insn);
 780                 bi := insn_bi(e_in.insn);
 781                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 782                     result := std_ulogic_vector(unsigned(a_in) - 1);
 783                     result_en := '1';
 784                     v.e.write_reg := fast_spr_num(SPR_CTR);
 785                 end if;
 786                 is_branch := '1';
 787                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 788                 abs_branch := '1';
 789                 if ctrl.msr(MSR_BE) = '1' then
 790                     do_trace := '1';
 791                 end if;
 792
 793             when OP_RFID =>
 794                 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
 795                 v.f.priv_mode := not a_in(MSR_PR);
 796                 v.f.big_endian := not a_in(MSR_LE);
 797                 v.f.mode_32bit := not a_in(MSR_SF);
 798                 -- Can't use msr_copy here because the partial function MSR
 799                 -- bits should be left unchanged, not zeroed.
 800                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 801                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 802                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 803                 if a_in(MSR_PR) = '1' then
 804                     ctrl_tmp.msr(MSR_EE) <= '1';
 805                     ctrl_tmp.msr(MSR_IR) <= '1';
 806                     ctrl_tmp.msr(MSR_DR) <= '1';
 807                 end if;
 808                 -- mark this as a branch so CFAR gets updated
 809                 is_branch := '1';
 810                 taken_branch := '1';
 811                 abs_branch := '1';
 812                 do_trace := '0';
 813
 814             when OP_CNTZ =>
 815                 v.e.valid := '0';
 816                 v.cntz_in_progress := '1';
 817                 v.busy := '1';
 818             when OP_ISEL =>
 819                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 820                 if cr_in(31-crbit) = '1' then
 821                     result := a_in;
 822                 else
 823                     result := b_in;
 824                 end if;
 825                 result_en := '1';
 826             when OP_CROP =>
 827                 cr_op := insn_cr(e_in.insn);
 828                 report "CR OP " & to_hstring(cr_op);
 829                 if cr_op(0) = '0' then -- MCRF
 830                     bf := insn_bf(e_in.insn);
 831                     bfa := insn_bfa(e_in.insn);
 832                     v.e.write_cr_enable := '1';
 833                     crnum := to_integer(unsigned(bf));
 834                     scrnum := to_integer(unsigned(bfa));
 835                     v.e.write_cr_mask := num_to_fxm(crnum);
 836                     for i in 0 to 7 loop
 837                         lo := (7-i)*4;
 838                         hi := lo + 3;
 839                         if i = scrnum then
 840                             newcrf := cr_in(hi downto lo);
 841                         end if;
 842                     end loop;
 843                     for i in 0 to 7 loop
 844                         lo := i*4;
 845                         hi := lo + 3;
 846                         v.e.write_cr_data(hi downto lo) := newcrf;
 847                     end loop;
 848                 else
 849                     v.e.write_cr_enable := '1';
 850                     bt := insn_bt(e_in.insn);
 851                     ba := insn_ba(e_in.insn);
 852                     bb := insn_bb(e_in.insn);
 853                     btnum := 31 - to_integer(unsigned(bt));
 854                     banum := 31 - to_integer(unsigned(ba));
 855                     bbnum := 31 - to_integer(unsigned(bb));
 856                     -- Bits 5-8 of cr_op give the truth table of the requested
 857                     -- logical operation
 858                     cr_operands := cr_in(banum) & cr_in(bbnum);
 859                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 860                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 861                     for i in 0 to 31 loop
 862                         if i = btnum then
 863                             v.e.write_cr_data(i) := crresult;
 864                         else
 865                             v.e.write_cr_data(i) := cr_in(i);
 866                         end if;
 867                     end loop;
 868                 end if;
 869             when OP_MCRXRX =>
 870                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 871                 bf := insn_bf(e_in.insn);
 872                 crnum := to_integer(unsigned(bf));
 873                 v.e.write_cr_enable := '1';
 874                 v.e.write_cr_mask := num_to_fxm(crnum);
 875                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 876                                      newcrf & newcrf & newcrf & newcrf;
 877             when OP_DARN =>
 878                 if random_err = '0' then
 879                     case e_in.insn(17 downto 16) is
 880                         when "00" =>
 881                             result := x"00000000" & random_cond(31 downto 0);
 882                         when "10" =>
 883                             result := random_raw;
 884                         when others =>
 885                             result := random_cond;
 886                     end case;
 887                 else
 888                     result := (others => '1');
 889                 end if;
 890                 result_en := '1';
 891             when OP_MFMSR =>
 892                 result := ctrl.msr;
 893                 result_en := '1';
 894             when OP_MFSPR =>
 895                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 896                     "=" & to_hstring(a_in);
 897                 result_en := '1';
 898                 if is_fast_spr(e_in.read_reg1) then
 899                     result := a_in;
 900                     if decode_spr_num(e_in.insn) = SPR_XER then
 901                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 902                         result(63 downto 32) := (others => '0');
 903                         result(63-32) := v.e.xerc.so;
 904                         result(63-33) := v.e.xerc.ov;
 905                         result(63-34) := v.e.xerc.ca;
 906                         result(63-35 downto 63-43) := "000000000";
 907                         result(63-44) := v.e.xerc.ov32;
 908                         result(63-45) := v.e.xerc.ca32;
 909                     end if;
 910                 else
 911                     spr_val := c_in;
 912                     case decode_spr_num(e_in.insn) is
 913                     when SPR_TB =>
 914                         spr_val := ctrl.tb;
 915                     when SPR_TBU =>
 916                         spr_val(63 downto 32) := (others => '0');
 917                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 918                     when SPR_DEC =>
 919                         spr_val := ctrl.dec;
 920                     when SPR_CFAR =>
 921                         spr_val := ctrl.cfar;
 922                     when SPR_PVR =>
 923                         spr_val(63 downto 32) := (others => '0');
 924                         spr_val(31 downto 0) := PVR_MICROWATT;
 925                     when 724 =>     -- LOG_ADDR SPR
 926                         spr_val := log_wr_addr & r.log_addr_spr;
 927                     when 725 =>     -- LOG_DATA SPR
 928                         spr_val := log_rd_data;
 929                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 930                     when others =>
 931                         -- mfspr from unimplemented SPRs should be a nop in
 932                         -- supervisor mode and a program interrupt for user mode
 933                         if ctrl.msr(MSR_PR) = '1' then
 934                             illegal := '1';
 935                         end if;
 936                     end case;
 937                     result := spr_val;
 938                 end if;
 939             when OP_MFCR =>
 940                 if e_in.insn(20) = '0' then
 941                     -- mfcr
 942                     result := x"00000000" & cr_in;
 943                 else
 944                     -- mfocrf
 945                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 946                     result := (others => '0');
 947                     for i in 0 to 7 loop
 948                         lo := (7-i)*4;
 949                         hi := lo + 3;
 950                         if crnum = i then
 951                             result(hi downto lo) := cr_in(hi downto lo);
 952                         end if;
 953                     end loop;
 954                 end if;
 955                 result_en := '1';
 956             when OP_MTCRF =>
 957                 v.e.write_cr_enable := '1';
 958                 if e_in.insn(20) = '0' then
 959                     -- mtcrf
 960                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 961                 else
 962                     -- mtocrf: We require one hot priority encoding here
 963                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 964                     v.e.write_cr_mask := num_to_fxm(crnum);
 965                 end if;
 966                 v.e.write_cr_data := c_in(31 downto 0);
 967             when OP_MTMSRD =>
 968                 if e_in.insn(16) = '1' then
 969                     -- just update EE and RI
 970                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 971                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 972                 else
 973                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 974                     -- and 63 (LE) (IBM bit numbering)
 975                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 976                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 977                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 978                     if c_in(MSR_PR) = '1' then
 979                         ctrl_tmp.msr(MSR_EE) <= '1';
 980                         ctrl_tmp.msr(MSR_IR) <= '1';
 981                         ctrl_tmp.msr(MSR_DR) <= '1';
 982                     end if;
 983                 end if;
 984             when OP_MTSPR =>
 985                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 986                     "=" & to_hstring(c_in);
 987                 if is_fast_spr(e_in.write_reg) then
 988                     result := c_in;
 989                     result_en := '1';
 990                     if decode_spr_num(e_in.insn) = SPR_XER then
 991                         v.e.xerc.so := c_in(63-32);
 992                         v.e.xerc.ov := c_in(63-33);
 993                         v.e.xerc.ca := c_in(63-34);
 994                         v.e.xerc.ov32 := c_in(63-44);
 995                         v.e.xerc.ca32 := c_in(63-45);
 996                         v.e.write_xerc_enable := '1';
 997                     end if;
 998                 else
 999                     -- slow spr
1000                     case decode_spr_num(e_in.insn) is
1001                     when SPR_DEC =>
1002                         ctrl_tmp.dec <= c_in;
1003                     when 724 =>     -- LOG_ADDR SPR
1004                         v.log_addr_spr := c_in(31 downto 0);
1005                     when others =>
1006                         -- mtspr to unimplemented SPRs should be a nop in
1007                         -- supervisor mode and a program interrupt for user mode
1008                         if ctrl.msr(MSR_PR) = '1' then
1009                             illegal := '1';
1010                         end if;
1011                     end case;
1012                 end if;
1013             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1014                 result := rotator_result;
1015                 if e_in.output_carry = '1' then
1016                     set_carry(v.e, rotator_carry, rotator_carry);
1017                 end if;
1018                 result_en := '1';
1019             when OP_SETB =>
1020                 bfa := insn_bfa(e_in.insn);
1021                 crbit := to_integer(unsigned(bfa)) * 4;
1022                 result := (others => '0');
1023                 if cr_in(31 - crbit) = '1' then
1024                     result := (others => '1');
1025                 elsif cr_in(30 - crbit) = '1' then
1026                     result(0) := '1';
1027                 end if;
1028
1029             when OP_ISYNC =>
1030                 v.f.redirect := '1';
1031                 v.f.redirect_nia := next_nia;
1032
1033             when OP_ICBI =>
1034                 icache_inval <= '1';
1035
1036             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1037                 v.e.valid := '0';
1038                 v.mul_in_progress := '1';
1039                 v.busy := '1';
1040                 x_to_multiply.valid <= '1';
1041
1042             when OP_DIV | OP_DIVE | OP_MOD =>
1043                 v.e.valid := '0';
1044                 v.div_in_progress := '1';
1045                 v.busy := '1';
1046                 x_to_divider.valid <= '1';
1047
1048             when others =>
1049                 v.terminate := '1';
1050                 report "illegal";
1051             end case;
1052
1053             v.e.rc := e_in.rc and valid_in;
1054
1055             -- Mispredicted branches cause a redirect
1056             if is_branch = '1' then
1057                 if taken_branch = '1' then
1058                     ctrl_tmp.cfar <= e_in.nia;
1059                 end if;
1060                 if e_in.br_pred = '0' then
1061                     if abs_branch = '1' then
1062                         v.f.redirect_nia := b_in;
1063                     else
1064                         v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
1065                     end if;
1066                 else
1067                     v.f.redirect_nia := next_nia;
1068                 end if;
1069                 if taken_branch /= e_in.br_pred then
1070                     v.f.redirect := '1';
1071                 end if;
1072             end if;
1073
1074             -- Update LR on the next cycle after a branch link
1075             -- If we're not writing back anything else, we can write back LR
1076             -- this cycle, otherwise we take an extra cycle.  We use the
1077             -- exc_write path since next_nia is written through that path
1078             -- in other places.
1079             if e_in.lr = '1' then
1080                 if result_en = '0' then
1081                     v.e.exc_write_enable := '1';
1082                     v.e.exc_write_data := next_nia;
1083                     v.e.exc_write_reg := fast_spr_num(SPR_LR);
1084                 else
1085                     v.lr_update := '1';
1086                     v.next_lr := next_nia;
1087                     v.e.valid := '0';
1088                     report "Delayed LR update to " & to_hstring(next_nia);
1089                     v.busy := '1';
1090                 end if;
1091             end if;
1092
1093         elsif valid_in = '1' then
1094             -- instruction for other units, i.e. LDST
1095             if e_in.unit = LDST then
1096                 lv.valid := '1';
1097             elsif e_in.unit = NONE then
1098                 illegal := '1';
1099             end if;
1100
1101         elsif r.f.redirect = '1' then
1102             v.e.valid := '1';
1103         elsif r.lr_update = '1' then
1104             v.e.exc_write_enable := '1';
1105             v.e.exc_write_data := r.next_lr;
1106             v.e.exc_write_reg := fast_spr_num(SPR_LR);
1107             v.e.valid := '1';
1108         elsif r.cntz_in_progress = '1' then
1109             -- cnt[lt]z always takes two cycles
1110             result := countzero_result;
1111             result_en := '1';
1112             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1113             v.e.rc := r.slow_op_rc;
1114             v.e.xerc := r.slow_op_xerc;
1115             v.e.valid := '1';
1116         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1117             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1118                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1119                 if r.mul_in_progress = '1' then
1120                     overflow := '0';
1121                     case r.slow_op_insn is
1122                         when OP_MUL_H32 =>
1123                             result := multiply_to_x.result(63 downto 32) &
1124                                       multiply_to_x.result(63 downto 32);
1125                         when OP_MUL_H64 =>
1126                             result := multiply_to_x.result(127 downto 64);
1127                         when others =>
1128                             -- i.e. OP_MUL_L64
1129                             result := multiply_to_x.result(63 downto 0);
1130                     end case;
1131                 else
1132                     result := divider_to_x.write_reg_data;
1133                     overflow := divider_to_x.overflow;
1134                 end if;
1135                 if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
1136                     -- have to wait until next cycle for overflow indication
1137                     v.mul_finish := '1';
1138                     v.busy := '1';
1139                 else
1140                     result_en := '1';
1141                     v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1142                     v.e.rc := r.slow_op_rc;
1143                     v.e.xerc := r.slow_op_xerc;
1144                     v.e.write_xerc_enable := r.slow_op_oe;
1145                     -- We must test oe because the RC update code in writeback
1146                     -- will use the xerc value to set CR0:SO so we must not clobber
1147                     -- xerc if OE wasn't set.
1148                     if r.slow_op_oe = '1' then
1149                         v.e.xerc.ov := overflow;
1150                         v.e.xerc.ov32 := overflow;
1151                         v.e.xerc.so := r.slow_op_xerc.so or overflow;
1152                     end if;
1153                     v.e.valid := '1';
1154                 end if;
1155             else
1156                 v.busy := '1';
1157                 v.mul_in_progress := r.mul_in_progress;
1158                 v.div_in_progress := r.div_in_progress;
1159             end if;
1160         elsif r.mul_finish = '1' then
1161             result := r.e.write_data;
1162             result_en := '1';
1163             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1164             v.e.rc := r.slow_op_rc;
1165             v.e.xerc := r.slow_op_xerc;
1166             v.e.write_xerc_enable := r.slow_op_oe;
1167             v.e.xerc.ov := multiply_to_x.overflow;
1168             v.e.xerc.ov32 := multiply_to_x.overflow;
1169             v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
1170             v.e.valid := '1';
1171         end if;
1172
1173         if illegal = '1' then
1174             exception := '1';
1175             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1176             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1177             -- set bit 44 to indicate we have an illegal
1178             ctrl_tmp.srr1(63 - 44) <= '1';
1179             report "illegal";
1180         end if;
1181         if exception = '1' then
1182             v.e.exc_write_enable := '1';
1183             if exception_nextpc = '1' then
1184                 v.e.exc_write_data := next_nia;
1185             end if;
1186         end if;
1187
1188         if do_trace = '1' then
1189             v.trace_next := '1';
1190         end if;
1191
1192         v.e.write_data := result;
1193         v.e.write_enable := result_en and not exception;
1194
1195         -- generate DSI or DSegI for load/store exceptions
1196         -- or ISI or ISegI for instruction fetch exceptions
1197         if l_in.exception = '1' then
1198             if l_in.alignment = '1' then
1199                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#600#, 64));
1200             elsif l_in.instr_fault = '0' then
1201                 if l_in.segment_fault = '0' then
1202                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1203                 else
1204                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1205                 end if;
1206             else
1207                 if l_in.segment_fault = '0' then
1208                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1209                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1210                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1211                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1212                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1213                 else
1214                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1215                 end if;
1216             end if;
1217             v.e.exc_write_enable := '1';
1218             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1219             v.e.exc_write_data := r.last_nia;
1220             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1221         end if;
1222
1223         if exception = '1' or l_in.exception = '1' then
1224             ctrl_tmp.irq_state <= WRITE_SRR1;
1225             v.f.redirect := '1';
1226             v.f.virt_mode := '0';
1227             v.f.priv_mode := '1';
1228             -- XXX need an interrupt LE bit here, e.g. from LPCR
1229             v.f.big_endian := '0';
1230             v.f.mode_32bit := '0';
1231         end if;
1232
1233         if v.f.redirect = '1' then
1234             v.busy := '1';
1235             v.e.valid := '0';
1236         end if;
1237
1238         -- Outputs to loadstore1 (async)
1239         lv.op := e_in.insn_type;
1240         lv.nia := e_in.nia;
1241         lv.addr1 := a_in;
1242         lv.addr2 := b_in;
1243         lv.data := c_in;
1244         lv.write_reg := e_in.write_reg;
1245         lv.length := e_in.data_len;
1246         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1247         lv.sign_extend := e_in.sign_extend;
1248         lv.update := e_in.update;
1249         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1250         lv.xerc := v.e.xerc;
1251         lv.reserve := e_in.reserve;
1252         lv.rc := e_in.rc;
1253         lv.insn := e_in.insn;
1254         -- decode l*cix and st*cix instructions here
1255         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1256             e_in.insn(5 downto 1) = "10101" then
1257             lv.ci := '1';
1258         end if;
1259         lv.virt_mode := ctrl.msr(MSR_DR);
1260         lv.priv_mode := not ctrl.msr(MSR_PR);
1261         lv.mode_32bit := not ctrl.msr(MSR_SF);
1262         lv.is_32bit := e_in.is_32bit;
1263
1264         -- Update registers
1265         rin <= v;
1266
1267         -- update outputs
1268         f_out <= r.f;
1269         l_out <= lv;
1270         e_out <= r.e;
1271         flush_out <= f_out.redirect;
1272
1273         exception_log <= exception;
1274         irq_valid_log <= irq_valid;
1275     end process;
1276
1277     e1_log: if LOG_LENGTH > 0 generate
1278         signal log_data : std_ulogic_vector(14 downto 0);
1279     begin
1280         ex1_log : process(clk)
1281         begin
1282             if rising_edge(clk) then
1283                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1284                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1285                             exception_log &
1286                             irq_valid_log &
1287                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1288                             "000" &
1289                             r.e.write_enable &
1290                             r.e.valid &
1291                             f_out.redirect &
1292                             r.busy &
1293                             flush_out;
1294             end if;
1295         end process;
1296         log_out <= log_data;
1297     end generate;
1298 end architecture behaviour;